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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_wb_tpram.v] - Blame information for rev 77

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of pci bridge project                     ////
////  http://www.opencores.org/cvsweb.shtml/pci/                  ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Miha Dolenc, mihad@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2002/10/18 03:36:37  tadejm
// Changed wrong signal name scanb_sen into scanb_en.
//
// Revision 1.6  2002/10/17 22:49:22  tadejm
// Changed BIST signals for RAMs.
//
// Revision 1.5  2002/10/11 10:09:01  mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.4  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
//
// Revision 1.3  2002/09/30 17:22:27  mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.2  2002/08/19 16:51:36  mihad
// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module pci_wb_tpram
(
        // Generic synchronous two-port RAM interface
        clk_a,
    rst_a,
    ce_a,
    we_a,
    oe_a,
    addr_a,
    di_a,
    do_a,
        clk_b,
    rst_b,
    ce_b,
    we_b,
    oe_b,
    addr_b,
    di_b,
    do_b
`ifdef PCI_BIST
    ,
    // debug chain signals
    scanb_rst,      // bist scan reset
    scanb_clk,      // bist scan clock
    scanb_si,       // bist scan serial in
    scanb_so,       // bist scan serial out
    scanb_en        // bist scan shift enable
`endif
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
`ifdef PCI_BIST
// debug chain signals
input   scanb_rst;      // bist scan reset
input   scanb_clk;      // bist scan clock
input   scanb_si;       // bist scan serial in
output  scanb_so;       // bist scan serial out
input   scanb_en;       // bist scan shift enable
`endif
 
//
// Internal wires and registers
//
 
`ifdef WB_VS_STP
    `define PCI_WB_RAM_SELECTED
    `ifdef PCI_BIST
        vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
    `else
        vs_hdtp_64x40 i_vs_hdtp_64x40
    `endif
        (
            .RCK        (clk_b),
            .WCK        (clk_a),
            .RADR       (addr_b),
            .WADR       (addr_a),
            .DI         (di_a),
            .DOUT       (do_b),
            .REN        (1'b0),
            .WEN        (!we_a)
        `ifdef PCI_BIST
            ,
            // debug chain signals
            .scanb_rst  (scanb_rst),
            .scanb_clk  (scanb_clk),
            .scanb_si   (scanb_si),
            .scanb_so   (scanb_so),
            .scanb_en   (scanb_en)
        `endif
        );
 
    assign do_a = 0 ;
`endif
 
`ifdef WB_ARTISAN_SDP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Artisan Synchronous Double-Port RAM (ra2sh)
    //
    art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
    (
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
    );
 
`endif
 
`ifdef AVANT_ATP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Avant! Asynchronous Two-Port RAM
    //
    avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
    );
 
`endif
 
`ifdef VIRAGE_STP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Virage Synchronous 2-port R/W RAM
    //
    virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
    );
 
`endif
 
`ifdef WB_XILINX_DIST_RAM
    `define PCI_WB_RAM_SELECTED
 
    reg [(aw-1):0] out_address ;
    always@(posedge clk_b or posedge rst_b)
    begin
        if ( rst_b )
            out_address <= #1 0 ;
        else if (ce_b)
            out_address <= #1 addr_b ;
    end
 
    pci_ram_16x40d #(aw) wb_distributed_ram
    (
        .data_out       (do_b),
        .we             (we_a),
        .data_in        (di_a),
        .read_address   (out_address),
        .write_address  (addr_a),
        .wclk           (clk_a)
    );
    assign do_a = 0 ;
`endif
`ifdef WB_XILINX_RAMB4
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of FPGA memory:
    //
    // Virtex/Spartan2
    //
 
    //
    // Block 0
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
    );
 
    //
    // Block 1
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
    );
 
    //
    // Block 2
    //
    // block ram2 wires - non generic width of block rams
    wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
    wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
    wire [15:0] blk2_do_a ;
    wire [15:0] blk2_do_b ;
 
    assign do_a[39:32] = blk2_do_a[7:0] ;
    assign do_b[39:32] = blk2_do_b[7:0] ;
 
    RAMB4_S16_S16 ramb4_s16_s16_2(
            .CLKA(clk_a),
            .RSTA(rst_a),
            .ADDRA(addr_a),
            .DIA(blk2_di_a),
            .ENA(ce_a),
            .WEA(we_a),
            .DOA(blk2_do_a),
 
            .CLKB(clk_b),
            .RSTB(rst_b),
            .ADDRB(addr_b),
            .DIB(blk2_di_b),
            .ENB(ce_b),
            .WEB(we_b),
            .DOB(blk2_do_b)
    );
 
`endif
 
`ifdef PCI_WB_RAM_SELECTED
`else
    //
    // Generic two-port synchronous RAM model
    //
 
    //
    // Generic RAM's registers and wires
    //
    reg [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
    reg [dw-1:0] do_reg_a;               // RAM data output register
    reg [dw-1:0] do_reg_b;               // RAM data output register
 
    //
    // Data output drivers
    //
    assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
    assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
    //
    // RAM read and write
    //
    always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
    //
    // RAM read and write
    //
    always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
    if (dw !== 40)
    begin
        $display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
        $finish ;
    end
    `ifdef XILINX_RAMB4
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
    // currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
    `ifdef ARTISAN_SDP
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
end
// synopsys translate_on
 
endmodule

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[/] [pci/] [tags/] [rel_10/] [rtl/] [verilog/] [pci_wb_tpram.v] - Blame information for rev 77

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of pci bridge project ////`
6			`//// http://www.opencores.org/cvsweb.shtml/pci/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// - Miha Dolenc, mihad@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.7 2002/10/18 03:36:37 tadejm`
66			`// Changed wrong signal name scanb_sen into scanb_en.`
67			`//`
68			`// Revision 1.6 2002/10/17 22:49:22 tadejm`
69			`// Changed BIST signals for RAMs.`
70			`//`
71			`// Revision 1.5 2002/10/11 10:09:01 mihad`
72			`// Added additional testcase and changed rst name in BIST to trst`
73			`//`
74			`// Revision 1.4 2002/10/08 17:17:06 mihad`
75			`// Added BIST signals for RAMs.`
76			`//`
77			`// Revision 1.3 2002/09/30 17:22:27 mihad`
78			`// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!`
79			`//`
80			`// Revision 1.2 2002/08/19 16:51:36 mihad`
81			`// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives`
82			`//`
83			`// Revision 1.1 2002/02/01 14:43:31 mihad`
84			`// * empty log message *`
85			`//`
86			`//`
87
88			`// synopsys translate_off`
89			`include "timescale.v"
90			`// synopsys translate_on`
91			`include "pci_constants.v"
92
93			`module pci_wb_tpram`
94			`(`
95			`// Generic synchronous two-port RAM interface`
96			`clk_a,`
97			`rst_a,`
98			`ce_a,`
99			`we_a,`
100			`oe_a,`
101			`addr_a,`
102			`di_a,`
103			`do_a,`
104			`clk_b,`
105			`rst_b,`
106			`ce_b,`
107			`we_b,`
108			`oe_b,`
109			`addr_b,`
110			`di_b,`
111			`do_b`
112			`ifdef PCI_BIST
113			`,`
114			`// debug chain signals`
115			`scanb_rst, // bist scan reset`
116			`scanb_clk, // bist scan clock`
117			`scanb_si, // bist scan serial in`
118			`scanb_so, // bist scan serial out`
119			`scanb_en // bist scan shift enable`
120			`endif
121			`);`
122
123			`//`
124			`// Default address and data buses width`
125			`//`
126			`parameter aw = 8;`
127			`parameter dw = 40;`
128
129			`//`
130			`// Generic synchronous two-port RAM interface`
131			`//`
132			`input clk_a; // Clock`
133			`input rst_a; // Reset`
134			`input ce_a; // Chip enable input`
135			`input we_a; // Write enable input`
136			`input oe_a; // Output enable input`
137			`input [aw-1:0] addr_a; // address bus inputs`
138			`input [dw-1:0] di_a; // input data bus`
139			`output [dw-1:0] do_a; // output data bus`
140			`input clk_b; // Clock`
141			`input rst_b; // Reset`
142			`input ce_b; // Chip enable input`
143			`input we_b; // Write enable input`
144			`input oe_b; // Output enable input`
145			`input [aw-1:0] addr_b; // address bus inputs`
146			`input [dw-1:0] di_b; // input data bus`
147			`output [dw-1:0] do_b; // output data bus`
148
149			`ifdef PCI_BIST
150			`// debug chain signals`
151			`input scanb_rst; // bist scan reset`
152			`input scanb_clk; // bist scan clock`
153			`input scanb_si; // bist scan serial in`
154			`output scanb_so; // bist scan serial out`
155			`input scanb_en; // bist scan shift enable`
156			`endif
157
158			`//`
159			`// Internal wires and registers`
160			`//`
161
162			`ifdef WB_VS_STP
163			`define PCI_WB_RAM_SELECTED
164			`ifdef PCI_BIST
165			`vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist`
166			`else
167			`vs_hdtp_64x40 i_vs_hdtp_64x40`
168			`endif
169			`(`
170			`.RCK (clk_b),`
171			`.WCK (clk_a),`
172			`.RADR (addr_b),`
173			`.WADR (addr_a),`
174			`.DI (di_a),`
175			`.DOUT (do_b),`
176			`.REN (1'b0),`
177			`.WEN (!we_a)`
178			`ifdef PCI_BIST
179			`,`
180			`// debug chain signals`
181			`.scanb_rst (scanb_rst),`
182			`.scanb_clk (scanb_clk),`
183			`.scanb_si (scanb_si),`
184			`.scanb_so (scanb_so),`
185			`.scanb_en (scanb_en)`
186			`endif
187			`);`
188
189			`assign do_a = 0 ;`
190			`endif
191
192			`ifdef WB_ARTISAN_SDP
193			`define PCI_WB_RAM_SELECTED
194			`//`
195			`// Instantiation of ASIC memory:`
196			`//`
197			`// Artisan Synchronous Double-Port RAM (ra2sh)`
198			`//`
199			`art_hsdp_256x40 /#(dw, 1<<aw, aw) / artisan_sdp`
200			`(`
201			`.qa(do_a),`
202			`.clka(clk_a),`
203			`.cena(~ce_a),`
204			`.wena(~we_a),`
205			`.aa(addr_a),`
206			`.da(di_a),`
207			`.oena(~oe_a),`
208			`.qb(do_b),`
209			`.clkb(clk_b),`
210			`.cenb(~ce_b),`
211			`.wenb(~we_b),`
212			`.ab(addr_b),`
213			`.db(di_b),`
214			`.oenb(~oe_b)`
215			`);`
216
217			`endif
218
219			`ifdef AVANT_ATP
220			`define PCI_WB_RAM_SELECTED
221			`//`
222			`// Instantiation of ASIC memory:`
223			`//`
224			`// Avant! Asynchronous Two-Port RAM`
225			`//`
226			`avant_atp avant_atp(`
227			`.web(~we),`
228			`.reb(),`
229			`.oeb(~oe),`
230			`.rcsb(),`
231			`.wcsb(),`
232			`.ra(addr),`
233			`.wa(addr),`
234			`.di(di),`
235			`.do(do)`
236			`);`
237
238			`endif
239
240			`ifdef VIRAGE_STP
241			`define PCI_WB_RAM_SELECTED
242			`//`
243			`// Instantiation of ASIC memory:`
244			`//`
245			`// Virage Synchronous 2-port R/W RAM`
246			`//`
247			`virage_stp virage_stp(`
248			`.QA(do_a),`
249			`.QB(do_b),`
250
251			`.ADRA(addr_a),`
252			`.DA(di_a),`
253			`.WEA(we_a),`
254			`.OEA(oe_a),`
255			`.MEA(ce_a),`
256			`.CLKA(clk_a),`
257
258			`.ADRB(adr_b),`
259			`.DB(di_b),`
260			`.WEB(we_b),`
261			`.OEB(oe_b),`
262			`.MEB(ce_b),`
263			`.CLKB(clk_b)`
264			`);`
265
266			`endif
267
268			`ifdef WB_XILINX_DIST_RAM
269			`define PCI_WB_RAM_SELECTED
270
271			`reg [(aw-1):0] out_address ;`
272			`always@(posedge clk_b or posedge rst_b)`
273			`begin`
274			`if ( rst_b )`
275			`out_address <= #1 0 ;`
276			`else if (ce_b)`
277			`out_address <= #1 addr_b ;`
278			`end`
279
280			`pci_ram_16x40d #(aw) wb_distributed_ram`
281			`(`
282			`.data_out (do_b),`
283			`.we (we_a),`
284			`.data_in (di_a),`
285			`.read_address (out_address),`
286			`.write_address (addr_a),`
287			`.wclk (clk_a)`
288			`);`
289			`assign do_a = 0 ;`
290			`endif
291			`ifdef WB_XILINX_RAMB4
292			`define PCI_WB_RAM_SELECTED
293			`//`
294			`// Instantiation of FPGA memory:`
295			`//`
296			`// Virtex/Spartan2`
297			`//`
298
299			`//`
300			`// Block 0`
301			`//`
302
303			`RAMB4_S16_S16 ramb4_s16_s16_0(`
304			`.CLKA(clk_a),`
305			`.RSTA(rst_a),`
306			`.ADDRA(addr_a),`
307			`.DIA(di_a[15:0]),`
308			`.ENA(ce_a),`
309			`.WEA(we_a),`
310			`.DOA(do_a[15:0]),`
311
312			`.CLKB(clk_b),`
313			`.RSTB(rst_b),`
314			`.ADDRB(addr_b),`
315			`.DIB(di_b[15:0]),`
316			`.ENB(ce_b),`
317			`.WEB(we_b),`
318			`.DOB(do_b[15:0])`
319			`);`
320
321			`//`
322			`// Block 1`
323			`//`
324
325			`RAMB4_S16_S16 ramb4_s16_s16_1(`
326			`.CLKA(clk_a),`
327			`.RSTA(rst_a),`
328			`.ADDRA(addr_a),`
329			`.DIA(di_a[31:16]),`
330			`.ENA(ce_a),`
331			`.WEA(we_a),`
332			`.DOA(do_a[31:16]),`
333
334			`.CLKB(clk_b),`
335			`.RSTB(rst_b),`
336			`.ADDRB(addr_b),`
337			`.DIB(di_b[31:16]),`
338			`.ENB(ce_b),`
339			`.WEB(we_b),`
340			`.DOB(do_b[31:16])`
341			`);`
342
343			`//`
344			`// Block 2`
345			`//`
346			`// block ram2 wires - non generic width of block rams`
347			`wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;`
348			`wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;`
349
350			`wire [15:0] blk2_do_a ;`
351			`wire [15:0] blk2_do_b ;`
352
353			`assign do_a[39:32] = blk2_do_a[7:0] ;`
354			`assign do_b[39:32] = blk2_do_b[7:0] ;`
355
356			`RAMB4_S16_S16 ramb4_s16_s16_2(`
357			`.CLKA(clk_a),`
358			`.RSTA(rst_a),`
359			`.ADDRA(addr_a),`
360			`.DIA(blk2_di_a),`
361			`.ENA(ce_a),`
362			`.WEA(we_a),`
363			`.DOA(blk2_do_a),`
364
365			`.CLKB(clk_b),`
366			`.RSTB(rst_b),`
367			`.ADDRB(addr_b),`
368			`.DIB(blk2_di_b),`
369			`.ENB(ce_b),`
370			`.WEB(we_b),`
371			`.DOB(blk2_do_b)`
372			`);`
373
374			`endif
375
376			`ifdef PCI_WB_RAM_SELECTED
377			`else
378			`//`
379			`// Generic two-port synchronous RAM model`
380			`//`
381
382			`//`
383			`// Generic RAM's registers and wires`
384			`//`
385			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
386			`reg [dw-1:0] do_reg_a; // RAM data output register`
387			`reg [dw-1:0] do_reg_b; // RAM data output register`
388
389			`//`
390			`// Data output drivers`
391			`//`
392			`assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};`
393			`assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};`
394
395			`//`
396			`// RAM read and write`
397			`//`
398			`always @(posedge clk_a)`
399			`if (ce_a && !we_a)`
400			`do_reg_a <= #1 mem[addr_a];`
401			`else if (ce_a && we_a)`
402			`mem[addr_a] <= #1 di_a;`
403
404			`//`
405			`// RAM read and write`
406			`//`
407			`always @(posedge clk_b)`
408			`if (ce_b && !we_b)`
409			`do_reg_b <= #1 mem[addr_b];`
410			`else if (ce_b && we_b)`
411			`mem[addr_b] <= #1 di_b;`
412			`endif
413
414			`// synopsys translate_off`
415			`initial`
416			`begin`
417			`if (dw !== 40)`
418			`begin`
419			`$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;`
420			`$finish ;`
421			`end`
422			`ifdef XILINX_RAMB4
423			`if (aw !== 8)`
424			`begin`
425			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
426			`$finish ;`
427			`end`
428			`endif
429			`// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models`
430			`ifdef ARTISAN_SDP
431			`if (aw !== 8)`
432			`begin`
433			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
434			`$finish ;`
435			`end`
436			`endif
437			`end`
438			`// synopsys translate_on`
439
440			`endmodule`