URL
https://opencores.org/ocsvn/pci/pci/trunk
[/] [pci/] [tags/] [rel_10/] [syn/] [scr/] [cons_vs_umc18.inc] - Blame information for rev 154
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
18 |
mihad |
/* Constraints */
|
| 2 |
|
|
CLK_UNCERTAINTY = 0.1 /* 100 ps */
|
| 3 |
|
|
DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
|
| 4 |
|
|
DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
|
| 5 |
|
|
|
| 6 |
|
|
/* Clocks constraints */
|
| 7 |
|
|
set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
|
| 8 |
|
|
set_dont_touch_network all_clocks()
|
| 9 |
|
|
|
| 10 |
|
|
/* Reset constraints */
|
| 11 |
|
|
set_driving_cell -none RST
|
| 12 |
|
|
set_drive 0 RST
|
| 13 |
|
|
set_dont_touch_network RST
|
| 14 |
|
|
|
| 15 |
|
|
/* All inputs except reset and clock */
|
| 16 |
|
|
all_inputs_wo_rst_clk = all_inputs() - PCI_CLK - WB_CLK - RST
|
| 17 |
|
|
|
| 18 |
|
|
/* Set output delays and load for output signals
|
| 19 |
|
|
*
|
| 20 |
|
|
* All outputs are assumed to go directly into
|
| 21 |
|
|
* external flip-flops for the purpose of this
|
| 22 |
|
|
* synthesis
|
| 23 |
|
|
*/
|
| 24 |
|
|
set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
|
| 25 |
|
|
|
| 26 |
|
|
/* Input delay and driving cell of all inputs
|
| 27 |
|
|
*
|
| 28 |
|
|
* All these signals are assumed to come directly from
|
| 29 |
|
|
* flip-flops for the purpose of this synthesis
|
| 30 |
|
|
*
|
| 31 |
|
|
*/
|
| 32 |
|
|
set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
|
| 33 |
|
|
|
| 34 |
|
|
/* Set design fanout */
|
| 35 |
|
|
/*
|
| 36 |
|
|
set_max_fanout 10 TOPLEVEL
|
| 37 |
|
|
*/
|
| 38 |
|
|
|
| 39 |
|
|
/* Set area constraint */
|
| 40 |
|
|
set_max_area MAX_AREA
|
| 41 |
|
|
|
| 42 |
|
|
set_operating_conditions -max WORST -max_library umcl18u250t2_wc
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.