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[/] [pci/] [tags/] [rel_10/] [syn/] [scr/] [set_env.inc] - Blame information for rev 154

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/* Enable Verilog HDL preprocessor */
hdlin_enable_vpp = true
 
/* Set log path */
LOG_PATH = "../logs/"
 
/* Set gate-level netlist path */
GATE_PATH = "../gate/"
 
/* Set RAMS_PATH */
RAMS_PATH = "../../lib/"
 
/* Set RTL source path */
RTL_PATH = "../../rtl/verilog/"
 
/* Optimize adders */
synlib_model_map_effort = high
hlo_share_effort = medium

Line No.	Rev	Author	Line
1	18	mihad	`/* Enable Verilog HDL preprocessor */`
2			`hdlin_enable_vpp = true`
3
4			`/* Set log path */`
5			`LOG_PATH = "../logs/"`
6
7			`/* Set gate-level netlist path */`
8			`GATE_PATH = "../gate/"`
9
10			`/* Set RAMS_PATH */`
11			`RAMS_PATH = "../../lib/"`
12
13			`/* Set RTL source path */`
14			`RTL_PATH = "../../rtl/verilog/"`
15
16			`/* Optimize adders */`
17			`synlib_model_map_effort = high`
18			`hlo_share_effort = medium`

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [syn/] [scr/] [set_env.inc] - Blame information for rev 154