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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "pci_bench_common_tasks.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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task pci_configure_pci_target_image ;
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input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
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input [2:0] image_num ; // image number
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input [31:0] ba ; // base address
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input [31:0] am ; // address mask
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input [31:0] ta ; // translation address
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input io_nmem ; // io/mem mapping select
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input pref_en ; // prefetch enable
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input at_en ; // address translation enable
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output ok ; // finished succesfully
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reg in_use ;
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reg [11:0] ctrl_offset ;
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reg [11:0] ba_offset ;
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reg [11:0] am_offset ;
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reg [11:0] ta_offset ;
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begin:main
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if (in_use === 1'b1)
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begin
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$display("Time %t", $time) ;
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$display("pci_configure_pci_target_image task re-entered") ;
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ok = 0 ;
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disable main ;
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end
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in_use = 1'b1 ;
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if (use_bus !== 1'b0)
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begin
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if (image_num === 0)
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begin
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ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
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ba_offset = {4'h1, `P_BA0_ADDR, 2'b00} ;
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am_offset = {4'h1, `P_AM0_ADDR, 2'b00} ;
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ta_offset = {4'h1, `P_TA0_ADDR, 2'b00} ;
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end
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else if (image_num === 1)
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begin
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ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
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ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
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am_offset = {4'h1, `P_AM1_ADDR, 2'b00} ;
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ta_offset = {4'h1, `P_TA1_ADDR, 2'b00} ;
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end
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else if (image_num === 2)
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begin
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ctrl_offset = {4'h1, `P_IMG_CTRL2_ADDR, 2'b00} ;
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ba_offset = {4'h1, `P_BA2_ADDR, 2'b00} ;
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am_offset = {4'h1, `P_AM2_ADDR, 2'b00} ;
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ta_offset = {4'h1, `P_TA2_ADDR, 2'b00} ;
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end
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else if (image_num === 3)
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begin
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ctrl_offset = {4'h1, `P_IMG_CTRL3_ADDR, 2'b00} ;
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ba_offset = {4'h1, `P_BA3_ADDR, 2'b00} ;
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am_offset = {4'h1, `P_AM3_ADDR, 2'b00} ;
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ta_offset = {4'h1, `P_TA3_ADDR, 2'b00} ;
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end
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else if (image_num === 4)
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begin
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ctrl_offset = {4'h1, `P_IMG_CTRL4_ADDR, 2'b00} ;
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ba_offset = {4'h1, `P_BA4_ADDR, 2'b00} ;
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am_offset = {4'h1, `P_AM4_ADDR, 2'b00} ;
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ta_offset = {4'h1, `P_TA4_ADDR, 2'b00} ;
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end
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else if (image_num === 5)
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begin
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ctrl_offset = {4'h1, `P_IMG_CTRL5_ADDR, 2'b00} ;
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ba_offset = {4'h1, `P_BA5_ADDR, 2'b00} ;
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am_offset = {4'h1, `P_AM5_ADDR, 2'b00} ;
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ta_offset = {4'h1, `P_TA5_ADDR, 2'b00} ;
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end
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// Set Base Address of IMAGE
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config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
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if ( ok !== 1 )
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begin
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in_use = 1'b0 ;
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disable main ;
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end
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// Set Address Mask of IMAGE
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config_write( am_offset, am, 4'hF, ok ) ;
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if ( ok !== 1 )
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begin
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in_use = 1'b0 ;
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disable main ;
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end
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// Set Translation Address of IMAGE
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config_write( ta_offset, ta, 4'hF, ok ) ;
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if ( ok !== 1 )
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begin
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in_use = 1'b0 ;
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disable main ;
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end
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// Set IMAGE Control Register
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config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
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if ( ok !== 1 )
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begin
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in_use = 1'b0 ;
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disable main ;
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end
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end
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else
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begin
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if (image_num === 0)
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begin
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`ifdef HOST
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`ifdef NO_CNF_IMAGE
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`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
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// set base address
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
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// set control register
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl0_bit2_1 = {at_en, pref_en} ;
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// set memory map - part of base address
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit0 = io_nmem ;
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// set address mask
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am0 = am[31:12] ;
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// set translation address
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta0 = ta[31:12] ;
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`endif
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`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
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`endif
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`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
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`endif
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end
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else if (image_num === 1)
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begin
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl1_bit2_1 = {at_en, pref_en} ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit31_12 = ba[31:12] ;
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`ifdef HOST
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit0 = io_nmem ;
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`endif
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am1 = am[31:12] ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta1 = ta[31:12] ;
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end
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else if (image_num === 2)
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begin
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`ifdef PCI_IMAGE2
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl2_bit2_1 = {at_en, pref_en} ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit31_12 = ba[31:12] ;
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`ifdef HOST
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit0 = io_nmem ;
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`endif
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am2 = am[31:12] ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta2 = ta[31:12] ;
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`endif
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end
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else if (image_num === 3)
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begin
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`ifdef PCI_IMAGE3
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl3_bit2_1 = {at_en, pref_en} ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit31_12 = ba[31:12] ;
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`ifdef HOST
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit0 = io_nmem ;
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`endif
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am3 = am[31:12] ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta3 = ta[31:12] ;
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`endif
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end
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else if (image_num === 4)
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begin
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`ifdef PCI_IMAGE4
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl4_bit2_1 = {at_en, pref_en} ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit31_12 = ba[31:12] ;
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`ifdef HOST
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit0 = io_nmem ;
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`endif
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am4 = am[31:12] ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta4 = ta[31:12] ;
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`endif
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end
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else if (image_num === 5)
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begin
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`ifdef PCI_IMAGE5
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl5_bit2_1 = {at_en, pref_en} ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit31_12 = ba[31:12] ;
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`ifdef HOST
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit0 = io_nmem ;
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`endif
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am5 = am[31:12] ;
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`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta5 = ta[31:12] ;
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`endif
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end
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end
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in_use = 1'b0 ;
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end
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endtask // pci_configure_pci_target_image
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task pci_configure_wb_slave_image ;
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input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
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input [2:0] image_num ; // image number
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input [31:0] ba ; // base address
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input [31:0] am ; // address mask
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input [31:0] ta ; // translation address
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input io_nmem ; // io/mem mapping select
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input pref_en ; // prefetch enable
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input at_en ; // address translation enable
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input mrl_en ; // memory read line enable
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output ok ; // finished succesfully
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reg in_use ;
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reg [11:0] ctrl_offset ;
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reg [11:0] ba_offset ;
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reg [11:0] am_offset ;
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reg [11:0] ta_offset ;
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begin:main
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if (in_use === 1'b1)
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begin
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$display("Time %t", $time) ;
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$display("pci_configure_wb_slave_image task re-entered") ;
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ok = 0 ;
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disable main ;
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end
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in_use = 1'b1 ;
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if (use_bus !== 1'b0)
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begin
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if (image_num === 1)
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begin
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ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
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ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
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am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
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ta_offset = {4'h1, `W_TA1_ADDR, 2'b00} ;
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end
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else if (image_num === 2)
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begin
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ctrl_offset = {4'h1, `W_IMG_CTRL2_ADDR, 2'b00} ;
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ba_offset = {4'h1, `W_BA2_ADDR, 2'b00} ;
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am_offset = {4'h1, `W_AM2_ADDR, 2'b00} ;
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ta_offset = {4'h1, `W_TA2_ADDR, 2'b00} ;
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end
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else if (image_num === 3)
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begin
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ctrl_offset = {4'h1, `W_IMG_CTRL3_ADDR, 2'b00} ;
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ba_offset = {4'h1, `W_BA3_ADDR, 2'b00} ;
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am_offset = {4'h1, `W_AM3_ADDR, 2'b00} ;
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ta_offset = {4'h1, `W_TA3_ADDR, 2'b00} ;
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end
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else if (image_num === 4)
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begin
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ctrl_offset = {4'h1, `W_IMG_CTRL4_ADDR, 2'b00} ;
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ba_offset = {4'h1, `W_BA4_ADDR, 2'b00} ;
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am_offset = {4'h1, `W_AM4_ADDR, 2'b00} ;
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ta_offset = {4'h1, `W_TA4_ADDR, 2'b00} ;
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end
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else if (image_num === 5)
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begin
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ctrl_offset = {4'h1, `W_IMG_CTRL5_ADDR, 2'b00} ;
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ba_offset = {4'h1, `W_BA5_ADDR, 2'b00} ;
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am_offset = {4'h1, `W_AM5_ADDR, 2'b00} ;
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ta_offset = {4'h1, `W_TA5_ADDR, 2'b00} ;
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end
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299 |
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300 |
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// Set Base Address of IMAGE
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301 |
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config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
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302 |
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if ( ok !== 1 )
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303 |
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begin
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304 |
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in_use = 1'b0 ;
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305 |
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disable main ;
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306 |
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end
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307 |
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308 |
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// Set Address Mask of IMAGE
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309 |
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config_write( am_offset, am, 4'hF, ok ) ;
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310 |
|
|
if ( ok !== 1 )
|
311 |
|
|
begin
|
312 |
|
|
in_use = 1'b0 ;
|
313 |
|
|
disable main ;
|
314 |
|
|
end
|
315 |
|
|
|
316 |
|
|
// Set Translation Address of IMAGE
|
317 |
|
|
config_write( ta_offset, ta, 4'hF, ok ) ;
|
318 |
|
|
if ( ok !== 1 )
|
319 |
|
|
begin
|
320 |
|
|
in_use = 1'b0 ;
|
321 |
|
|
disable main ;
|
322 |
|
|
end
|
323 |
|
|
|
324 |
|
|
// Set IMAGE Control Register
|
325 |
|
|
config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
|
326 |
|
|
if ( ok !== 1 )
|
327 |
|
|
begin
|
328 |
|
|
in_use = 1'b0 ;
|
329 |
|
|
disable main ;
|
330 |
|
|
end
|
331 |
|
|
end
|
332 |
|
|
else
|
333 |
|
|
begin
|
334 |
|
|
if (image_num === 1)
|
335 |
|
|
begin
|
336 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl1_bit2_0 = {at_en, pref_en, mrl_en} ;
|
337 |
|
|
|
338 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit31_12 = ba[31:12] ;
|
339 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit0 = io_nmem ;
|
340 |
|
|
|
341 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am1 = am[31:12] ;
|
342 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta1 = ta[31:12] ;
|
343 |
|
|
end
|
344 |
|
|
else if (image_num === 2)
|
345 |
|
|
begin
|
346 |
|
|
`ifdef WB_IMAGE2
|
347 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl2_bit2_0 = {at_en, pref_en, mrl_en} ;
|
348 |
|
|
|
349 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit31_12 = ba[31:12] ;
|
350 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit0 = io_nmem ;
|
351 |
|
|
|
352 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am2 = am[31:12] ;
|
353 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta2 = ta[31:12] ;
|
354 |
|
|
`endif
|
355 |
|
|
end
|
356 |
|
|
else if (image_num === 3)
|
357 |
|
|
begin
|
358 |
|
|
`ifdef WB_IMAGE3
|
359 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl3_bit2_0 = {at_en, pref_en, mrl_en} ;
|
360 |
|
|
|
361 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit31_12 = ba[31:12] ;
|
362 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit0 = io_nmem ;
|
363 |
|
|
|
364 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am3 = am[31:12] ;
|
365 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta3 = ta[31:12] ;
|
366 |
|
|
`endif
|
367 |
|
|
end
|
368 |
|
|
else if (image_num === 4)
|
369 |
|
|
begin
|
370 |
|
|
`ifdef WB_IMAGE4
|
371 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl4_bit2_0 = {at_en, pref_en, mrl_en} ;
|
372 |
|
|
|
373 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit31_12 = ba[31:12] ;
|
374 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit0 = io_nmem ;
|
375 |
|
|
|
376 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am4 = am[31:12] ;
|
377 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta4 = ta[31:12] ;
|
378 |
|
|
`endif
|
379 |
|
|
end
|
380 |
|
|
else if (image_num === 5)
|
381 |
|
|
begin
|
382 |
|
|
`ifdef WB_IMAGE5
|
383 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl5_bit2_0 = {at_en, pref_en, mrl_en} ;
|
384 |
|
|
|
385 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit31_12 = ba[31:12] ;
|
386 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit0 = io_nmem ;
|
387 |
|
|
|
388 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am5 = am[31:12] ;
|
389 |
|
|
`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta5 = ta[31:12] ;
|
390 |
|
|
`endif
|
391 |
|
|
end
|
392 |
|
|
end
|
393 |
|
|
|
394 |
|
|
in_use = 1'b0 ;
|
395 |
|
|
end
|
396 |
|
|
endtask // pci_configure_wb_slave_image
|