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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "conf_cyc_addr_dec.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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//
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//
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// module is a simple decoder which decodes device num field of configuration address
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// for type0 configuration cycles. If type 1 configuration cycle is
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// initiated then address goes through unchanged
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module pci_conf_cyc_addr_dec
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(
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ccyc_addr_in,
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ccyc_addr_out
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) ;
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input [31:0] ccyc_addr_in ;
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output [31:0] ccyc_addr_out ;
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reg [31:11] ccyc_addr_31_11 ;
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// lower 11 address lines are alweys going through unchanged
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assign ccyc_addr_out = {ccyc_addr_31_11, ccyc_addr_in[10:0]} ;
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// configuration cycle type indicator
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wire ccyc_type = ccyc_addr_in[0] ;
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always@(ccyc_addr_in or ccyc_type)
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begin
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if (ccyc_type)
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// type 1 cycle - address goes through unchanged
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ccyc_addr_31_11 = ccyc_addr_in[31:11] ;
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else
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begin
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// type 0 conf. cycle - decode device number field to appropriate value
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case (ccyc_addr_in[15:11])
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5'h00:ccyc_addr_31_11 = 21'h00_0001 ;
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5'h01:ccyc_addr_31_11 = 21'h00_0002 ;
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5'h02:ccyc_addr_31_11 = 21'h00_0004 ;
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5'h03:ccyc_addr_31_11 = 21'h00_0008 ;
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5'h04:ccyc_addr_31_11 = 21'h00_0010 ;
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5'h05:ccyc_addr_31_11 = 21'h00_0020 ;
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5'h06:ccyc_addr_31_11 = 21'h00_0040 ;
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5'h07:ccyc_addr_31_11 = 21'h00_0080 ;
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5'h08:ccyc_addr_31_11 = 21'h00_0100 ;
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5'h09:ccyc_addr_31_11 = 21'h00_0200 ;
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5'h0A:ccyc_addr_31_11 = 21'h00_0400 ;
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5'h0B:ccyc_addr_31_11 = 21'h00_0800 ;
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5'h0C:ccyc_addr_31_11 = 21'h00_1000 ;
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5'h0D:ccyc_addr_31_11 = 21'h00_2000 ;
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5'h0E:ccyc_addr_31_11 = 21'h00_4000 ;
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5'h0F:ccyc_addr_31_11 = 21'h00_8000 ;
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5'h10:ccyc_addr_31_11 = 21'h01_0000 ;
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5'h11:ccyc_addr_31_11 = 21'h02_0000 ;
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5'h12:ccyc_addr_31_11 = 21'h04_0000 ;
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5'h13:ccyc_addr_31_11 = 21'h08_0000 ;
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5'h14:ccyc_addr_31_11 = 21'h10_0000 ;
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default: ccyc_addr_31_11 = 21'h00_0000 ;
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endcase
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end
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end
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endmodule
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