URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] [pci_io_mux.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_io_mux.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// this module instantiates output flip flops for PCI interface and
// some fanout downsizing logic because of heavily constrained PCI signals
`include "constants.v"
module PCI_IO_MUX
(
    reset_in,
    clk_in,
    frame_in,
    frame_en_in,
    frame_load_in,
    irdy_in,
    irdy_en_in,
    devsel_in,
    devsel_en_in,
    trdy_in,
    trdy_en_in,
    stop_in,
    stop_en_in,
    master_load_in,
    target_load_in,
    cbe_in,
    cbe_en_in,
    mas_ad_in,
    tar_ad_in,
 
    par_in,
    par_en_in,
    perr_in,
    perr_en_in,
    serr_in,
    serr_en_in,
 
    req_in,
 
    mas_ad_en_in,
    tar_ad_en_in,
    tar_ad_en_reg_in,
 
    ad_en_out,
    frame_en_out,
    irdy_en_out,
    devsel_en_out,
    trdy_en_out,
    stop_en_out,
    cbe_en_out,
 
    frame_out,
    irdy_out,
    devsel_out,
    trdy_out,
    stop_out,
    cbe_out,
    ad_out,
 
    par_out,
    par_en_out,
    perr_out,
    perr_en_out,
    serr_out,
    serr_en_out,
 
    req_out,
    req_en_out
 
);
 
input reset_in, clk_in ;
 
input           frame_in ;
input           frame_en_in ;
input           frame_load_in ;
input           irdy_in ;
input           irdy_en_in ;
input           devsel_in ;
input           devsel_en_in ;
input           trdy_in ;
input           trdy_en_in ;
input           stop_in ;
input           stop_en_in ;
input           master_load_in ;
input           target_load_in ;
 
input [3:0]     cbe_in ;
input           cbe_en_in ;
input [31:0]    mas_ad_in ;
input [31:0]    tar_ad_in ;
 
input           mas_ad_en_in ;
input           tar_ad_en_in ;
input           tar_ad_en_reg_in ;
 
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
 
output          frame_en_out ;
output          irdy_en_out ;
output          devsel_en_out ;
output          trdy_en_out ;
output          stop_en_out ;
output [31:0]   ad_en_out ;
output [3:0]    cbe_en_out ;
 
output          frame_out ;
output          irdy_out ;
output          devsel_out ;
output          trdy_out ;
output          stop_out ;
output [3:0]    cbe_out ;
output [31:0]   ad_out ;
 
output          par_out ;
output          par_en_out ;
output          perr_out ;
output          perr_en_out ;
output          serr_out ;
output          serr_en_out ;
 
input           req_in ;
 
output          req_out ;
output          req_en_out ;
 
 
wire   [31:0]   temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
 
wire ad_en_ctrl_low ;
IO_MUX_EN_MULT ad_en_low_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_low)) ;
 
wire ad_en_ctrl_mlow ;
IO_MUX_EN_MULT ad_en_mlow_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mlow)) ;
 
wire ad_en_ctrl_mhigh ;
IO_MUX_EN_MULT ad_en_mhigh_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mhigh)) ;
 
wire ad_en_ctrl_high ;
IO_MUX_EN_MULT ad_en_high_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_high)) ;
 
wire ad_load_ctrl_low ;
IO_MUX_LOAD_MUX ad_load_low_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_low));
 
wire ad_load_ctrl_mlow ;
IO_MUX_LOAD_MUX ad_load_mlow_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mlow));
 
wire ad_load_ctrl_mhigh ;
IO_MUX_LOAD_MUX ad_load_mhigh_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mhigh));
 
wire ad_load_ctrl_high ;
IO_MUX_LOAD_MUX ad_load_high_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_high)) ;
 
OUT_REG ad_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[0] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[0] ),
    .dat_out      ( ad_out[0] )
);
 
OUT_REG ad_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[1] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[1] ),
    .dat_out      ( ad_out[1] )
);
 
OUT_REG ad_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[2] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[2] ),
    .dat_out      ( ad_out[2] )
);
 
OUT_REG ad_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[3] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[3] ),
    .dat_out      ( ad_out[3] )
);
 
OUT_REG ad_iob4
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[4] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[4] ),
    .dat_out      ( ad_out[4] )
);
 
OUT_REG ad_iob5
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[5] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[5] ),
    .dat_out      ( ad_out[5] )
);
 
OUT_REG ad_iob6
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[6] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[6] ),
    .dat_out      ( ad_out[6] )
);
 
OUT_REG ad_iob7
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[7] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[7] ),
    .dat_out      ( ad_out[7] )
);
 
OUT_REG ad_iob8
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[8] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[8] ),
    .dat_out      ( ad_out[8] )
);
 
OUT_REG ad_iob9
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[9] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[9] ),
    .dat_out      ( ad_out[9] )
);
 
OUT_REG ad_iob10
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[10] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[10] ),
    .dat_out      ( ad_out[10] )
);
 
OUT_REG ad_iob11
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[11] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[11] ),
    .dat_out      ( ad_out[11] )
);
 
OUT_REG ad_iob12
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[12] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[12] ),
    .dat_out      ( ad_out[12] )
);
 
OUT_REG ad_iob13
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[13] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[13] ),
    .dat_out      ( ad_out[13] )
);
 
OUT_REG ad_iob14
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[14] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[14] ),
    .dat_out      ( ad_out[14] )
);
 
OUT_REG ad_iob15
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[15] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[15] ),
    .dat_out      ( ad_out[15] )
);
 
OUT_REG ad_iob16
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[16] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[16] ),
    .dat_out      ( ad_out[16] )
);
 
OUT_REG ad_iob17
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[17] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[17] ),
    .dat_out      ( ad_out[17] )
);
 
OUT_REG ad_iob18
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[18] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[18] ),
    .dat_out      ( ad_out[18] )
);
 
OUT_REG ad_iob19
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[19] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[19] ),
    .dat_out      ( ad_out[19] )
);
 
OUT_REG ad_iob20
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[20] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[20] ),
    .dat_out      ( ad_out[20] )
);
 
OUT_REG ad_iob21
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[21] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[21] ),
    .dat_out      ( ad_out[21] )
);
 
OUT_REG ad_iob22
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[22] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[22] ),
    .dat_out      ( ad_out[22] )
);
 
OUT_REG ad_iob23
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[23] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[23] ),
    .dat_out      ( ad_out[23] )
);
 
OUT_REG ad_iob24
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[24] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[24] ),
    .dat_out      ( ad_out[24] )
);
 
OUT_REG ad_iob25
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[25] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[25] ),
    .dat_out      ( ad_out[25] )
);
 
OUT_REG ad_iob26
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[26] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[26] ),
    .dat_out      ( ad_out[26] )
);
 
OUT_REG ad_iob27
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[27] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[27] ),
    .dat_out      ( ad_out[27] )
);
 
OUT_REG ad_iob28
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[28] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[28] ),
    .dat_out      ( ad_out[28] )
);
 
OUT_REG ad_iob29
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[29] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[29] ),
    .dat_out      ( ad_out[29] )
);
 
OUT_REG ad_iob30
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[30] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[30] ),
    .dat_out      ( ad_out[30] )
);
 
OUT_REG ad_iob31
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[31] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[31] ),
    .dat_out      ( ad_out[31] )
);
 
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
wire [3:0] cbe_en_ctrl   = {4{ cbe_en_in }} ;
 
OUT_REG cbe_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[0] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[0] ) ,
    .en_in        ( cbe_en_ctrl[0] ) ,
    .en_out       ( cbe_en_out[0] ),
    .dat_out      ( cbe_out[0] )
);
 
OUT_REG cbe_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[1] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[1] ) ,
    .en_in        ( cbe_en_ctrl[1] ) ,
    .en_out       ( cbe_en_out[1] ),
    .dat_out      ( cbe_out[1] )
);
 
OUT_REG cbe_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[2] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[2] ) ,
    .en_in        ( cbe_en_ctrl[2] ) ,
    .en_out       ( cbe_en_out[2] ),
    .dat_out      ( cbe_out[2] )
);
 
OUT_REG cbe_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[3] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[3] ) ,
    .en_in        ( cbe_en_ctrl[3] ) ,
    .en_out       ( cbe_en_out[3] ),
    .dat_out      ( cbe_out[3] )
);
 
OUT_REG frame_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( frame_load_in ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( frame_in ) ,
    .en_in        ( frame_en_in ) ,
    .en_out       ( frame_en_out ),
    .dat_out      ( frame_out )
);
 
OUT_REG irdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( irdy_in ) ,
    .en_in        ( irdy_en_in ) ,
    .en_out       ( irdy_en_out ),
    .dat_out      ( irdy_out )
);
 
OUT_REG trdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( trdy_in ) ,
    .en_in        ( trdy_en_in ) ,
    .en_out       ( trdy_en_out ),
    .dat_out      ( trdy_out )
);
 
OUT_REG stop_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( stop_in ) ,
    .en_in        ( stop_en_in ) ,
    .en_out       ( stop_en_out ),
    .dat_out      ( stop_out )
);
 
OUT_REG devsel_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( devsel_in ) ,
    .en_in        ( devsel_en_in ) ,
    .en_out       ( devsel_en_out ),
    .dat_out      ( devsel_out )
);
 
OUT_REG par_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( par_in ) ,
    .en_in        ( par_en_in ) ,
    .en_out       ( par_en_out ),
    .dat_out      ( par_out )
);
 
OUT_REG perr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( perr_in ) ,
    .en_in        ( perr_en_in ) ,
    .en_out       ( perr_en_out ),
    .dat_out      ( perr_out )
);
 
OUT_REG serr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( serr_in ) ,
    .en_in        ( serr_en_in ) ,
    .en_out       ( serr_en_out ),
    .dat_out      ( serr_out )
);
 
OUT_REG req_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( req_in ) ,
    .en_in        ( 1'b1 ) ,
    .en_out       ( req_en_out ),
    .dat_out      ( req_out )
);
 
endmodule

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] [rtl/] [verilog/] [pci_io_mux.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_io_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`//`
46
47			`// this module instantiates output flip flops for PCI interface and`
48			`// some fanout downsizing logic because of heavily constrained PCI signals`
49			`include "constants.v"
50			`module PCI_IO_MUX`
51			`(`
52			`reset_in,`
53			`clk_in,`
54			`frame_in,`
55			`frame_en_in,`
56			`frame_load_in,`
57			`irdy_in,`
58			`irdy_en_in,`
59			`devsel_in,`
60			`devsel_en_in,`
61			`trdy_in,`
62			`trdy_en_in,`
63			`stop_in,`
64			`stop_en_in,`
65			`master_load_in,`
66			`target_load_in,`
67			`cbe_in,`
68			`cbe_en_in,`
69			`mas_ad_in,`
70			`tar_ad_in,`
71
72			`par_in,`
73			`par_en_in,`
74			`perr_in,`
75			`perr_en_in,`
76			`serr_in,`
77			`serr_en_in,`
78
79			`req_in,`
80
81			`mas_ad_en_in,`
82			`tar_ad_en_in,`
83			`tar_ad_en_reg_in,`
84
85			`ad_en_out,`
86			`frame_en_out,`
87			`irdy_en_out,`
88			`devsel_en_out,`
89			`trdy_en_out,`
90			`stop_en_out,`
91			`cbe_en_out,`
92
93			`frame_out,`
94			`irdy_out,`
95			`devsel_out,`
96			`trdy_out,`
97			`stop_out,`
98			`cbe_out,`
99			`ad_out,`
100
101			`par_out,`
102			`par_en_out,`
103			`perr_out,`
104			`perr_en_out,`
105			`serr_out,`
106			`serr_en_out,`
107
108			`req_out,`
109			`req_en_out`
110
111			`);`
112
113			`input reset_in, clk_in ;`
114
115			`input frame_in ;`
116			`input frame_en_in ;`
117			`input frame_load_in ;`
118			`input irdy_in ;`
119			`input irdy_en_in ;`
120			`input devsel_in ;`
121			`input devsel_en_in ;`
122			`input trdy_in ;`
123			`input trdy_en_in ;`
124			`input stop_in ;`
125			`input stop_en_in ;`
126			`input master_load_in ;`
127			`input target_load_in ;`
128
129			`input [3:0] cbe_in ;`
130			`input cbe_en_in ;`
131			`input [31:0] mas_ad_in ;`
132			`input [31:0] tar_ad_in ;`
133
134			`input mas_ad_en_in ;`
135			`input tar_ad_en_in ;`
136			`input tar_ad_en_reg_in ;`
137
138			`input par_in ;`
139			`input par_en_in ;`
140			`input perr_in ;`
141			`input perr_en_in ;`
142			`input serr_in ;`
143			`input serr_en_in ;`
144
145			`output frame_en_out ;`
146			`output irdy_en_out ;`
147			`output devsel_en_out ;`
148			`output trdy_en_out ;`
149			`output stop_en_out ;`
150			`output [31:0] ad_en_out ;`
151			`output [3:0] cbe_en_out ;`
152
153			`output frame_out ;`
154			`output irdy_out ;`
155			`output devsel_out ;`
156			`output trdy_out ;`
157			`output stop_out ;`
158			`output [3:0] cbe_out ;`
159			`output [31:0] ad_out ;`
160
161			`output par_out ;`
162			`output par_en_out ;`
163			`output perr_out ;`
164			`output perr_en_out ;`
165			`output serr_out ;`
166			`output serr_en_out ;`
167
168			`input req_in ;`
169
170			`output req_out ;`
171			`output req_en_out ;`
172
173
174			`wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;`
175
176			`wire ad_en_ctrl_low ;`
177			`IO_MUX_EN_MULT ad_en_low_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_low)) ;`
178
179			`wire ad_en_ctrl_mlow ;`
180			`IO_MUX_EN_MULT ad_en_mlow_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mlow)) ;`
181
182			`wire ad_en_ctrl_mhigh ;`
183			`IO_MUX_EN_MULT ad_en_mhigh_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mhigh)) ;`
184
185			`wire ad_en_ctrl_high ;`
186			`IO_MUX_EN_MULT ad_en_high_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_high)) ;`
187
188			`wire ad_load_ctrl_low ;`
189			`IO_MUX_LOAD_MUX ad_load_low_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_low));`
190
191			`wire ad_load_ctrl_mlow ;`
192			`IO_MUX_LOAD_MUX ad_load_mlow_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mlow));`
193
194			`wire ad_load_ctrl_mhigh ;`
195			`IO_MUX_LOAD_MUX ad_load_mhigh_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mhigh));`
196
197			`wire ad_load_ctrl_high ;`
198			`IO_MUX_LOAD_MUX ad_load_high_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_high)) ;`
199
200			`OUT_REG ad_iob0`
201			`(`
202			`.reset_in ( reset_in ),`
203			`.clk_in ( clk_in) ,`
204			`.dat_en_in ( ad_load_ctrl_low ),`
205			`.en_en_in ( 1'b1 ),`
206			`.dat_in ( temp_ad[0] ) ,`
207			`.en_in ( ad_en_ctrl_low ) ,`
208			`.en_out ( ad_en_out[0] ),`
209			`.dat_out ( ad_out[0] )`
210			`);`
211
212			`OUT_REG ad_iob1`
213			`(`
214			`.reset_in ( reset_in ),`
215			`.clk_in ( clk_in) ,`
216			`.dat_en_in ( ad_load_ctrl_low ),`
217			`.en_en_in ( 1'b1 ),`
218			`.dat_in ( temp_ad[1] ) ,`
219			`.en_in ( ad_en_ctrl_low ) ,`
220			`.en_out ( ad_en_out[1] ),`
221			`.dat_out ( ad_out[1] )`
222			`);`
223
224			`OUT_REG ad_iob2`
225			`(`
226			`.reset_in ( reset_in ),`
227			`.clk_in ( clk_in) ,`
228			`.dat_en_in ( ad_load_ctrl_low ),`
229			`.en_en_in ( 1'b1 ),`
230			`.dat_in ( temp_ad[2] ) ,`
231			`.en_in ( ad_en_ctrl_low ) ,`
232			`.en_out ( ad_en_out[2] ),`
233			`.dat_out ( ad_out[2] )`
234			`);`
235
236			`OUT_REG ad_iob3`
237			`(`
238			`.reset_in ( reset_in ),`
239			`.clk_in ( clk_in) ,`
240			`.dat_en_in ( ad_load_ctrl_low ),`
241			`.en_en_in ( 1'b1 ),`
242			`.dat_in ( temp_ad[3] ) ,`
243			`.en_in ( ad_en_ctrl_low ) ,`
244			`.en_out ( ad_en_out[3] ),`
245			`.dat_out ( ad_out[3] )`
246			`);`
247
248			`OUT_REG ad_iob4`
249			`(`
250			`.reset_in ( reset_in ),`
251			`.clk_in ( clk_in) ,`
252			`.dat_en_in ( ad_load_ctrl_low ),`
253			`.en_en_in ( 1'b1 ),`
254			`.dat_in ( temp_ad[4] ) ,`
255			`.en_in ( ad_en_ctrl_low ) ,`
256			`.en_out ( ad_en_out[4] ),`
257			`.dat_out ( ad_out[4] )`
258			`);`
259
260			`OUT_REG ad_iob5`
261			`(`
262			`.reset_in ( reset_in ),`
263			`.clk_in ( clk_in) ,`
264			`.dat_en_in ( ad_load_ctrl_low ),`
265			`.en_en_in ( 1'b1 ),`
266			`.dat_in ( temp_ad[5] ) ,`
267			`.en_in ( ad_en_ctrl_low ) ,`
268			`.en_out ( ad_en_out[5] ),`
269			`.dat_out ( ad_out[5] )`
270			`);`
271
272			`OUT_REG ad_iob6`
273			`(`
274			`.reset_in ( reset_in ),`
275			`.clk_in ( clk_in) ,`
276			`.dat_en_in ( ad_load_ctrl_low ),`
277			`.en_en_in ( 1'b1 ),`
278			`.dat_in ( temp_ad[6] ) ,`
279			`.en_in ( ad_en_ctrl_low ) ,`
280			`.en_out ( ad_en_out[6] ),`
281			`.dat_out ( ad_out[6] )`
282			`);`
283
284			`OUT_REG ad_iob7`
285			`(`
286			`.reset_in ( reset_in ),`
287			`.clk_in ( clk_in) ,`
288			`.dat_en_in ( ad_load_ctrl_low ),`
289			`.en_en_in ( 1'b1 ),`
290			`.dat_in ( temp_ad[7] ) ,`
291			`.en_in ( ad_en_ctrl_low ) ,`
292			`.en_out ( ad_en_out[7] ),`
293			`.dat_out ( ad_out[7] )`
294			`);`
295
296			`OUT_REG ad_iob8`
297			`(`
298			`.reset_in ( reset_in ),`
299			`.clk_in ( clk_in) ,`
300			`.dat_en_in ( ad_load_ctrl_mlow ),`
301			`.en_en_in ( 1'b1 ),`
302			`.dat_in ( temp_ad[8] ) ,`
303			`.en_in ( ad_en_ctrl_mlow ) ,`
304			`.en_out ( ad_en_out[8] ),`
305			`.dat_out ( ad_out[8] )`
306			`);`
307
308			`OUT_REG ad_iob9`
309			`(`
310			`.reset_in ( reset_in ),`
311			`.clk_in ( clk_in) ,`
312			`.dat_en_in ( ad_load_ctrl_mlow ),`
313			`.en_en_in ( 1'b1 ),`
314			`.dat_in ( temp_ad[9] ) ,`
315			`.en_in ( ad_en_ctrl_mlow ) ,`
316			`.en_out ( ad_en_out[9] ),`
317			`.dat_out ( ad_out[9] )`
318			`);`
319
320			`OUT_REG ad_iob10`
321			`(`
322			`.reset_in ( reset_in ),`
323			`.clk_in ( clk_in) ,`
324			`.dat_en_in ( ad_load_ctrl_mlow ),`
325			`.en_en_in ( 1'b1 ),`
326			`.dat_in ( temp_ad[10] ) ,`
327			`.en_in ( ad_en_ctrl_mlow ) ,`
328			`.en_out ( ad_en_out[10] ),`
329			`.dat_out ( ad_out[10] )`
330			`);`
331
332			`OUT_REG ad_iob11`
333			`(`
334			`.reset_in ( reset_in ),`
335			`.clk_in ( clk_in) ,`
336			`.dat_en_in ( ad_load_ctrl_mlow ),`
337			`.en_en_in ( 1'b1 ),`
338			`.dat_in ( temp_ad[11] ) ,`
339			`.en_in ( ad_en_ctrl_mlow ) ,`
340			`.en_out ( ad_en_out[11] ),`
341			`.dat_out ( ad_out[11] )`
342			`);`
343
344			`OUT_REG ad_iob12`
345			`(`
346			`.reset_in ( reset_in ),`
347			`.clk_in ( clk_in) ,`
348			`.dat_en_in ( ad_load_ctrl_mlow ),`
349			`.en_en_in ( 1'b1 ),`
350			`.dat_in ( temp_ad[12] ) ,`
351			`.en_in ( ad_en_ctrl_mlow ) ,`
352			`.en_out ( ad_en_out[12] ),`
353			`.dat_out ( ad_out[12] )`
354			`);`
355
356			`OUT_REG ad_iob13`
357			`(`
358			`.reset_in ( reset_in ),`
359			`.clk_in ( clk_in) ,`
360			`.dat_en_in ( ad_load_ctrl_mlow ),`
361			`.en_en_in ( 1'b1 ),`
362			`.dat_in ( temp_ad[13] ) ,`
363			`.en_in ( ad_en_ctrl_mlow ) ,`
364			`.en_out ( ad_en_out[13] ),`
365			`.dat_out ( ad_out[13] )`
366			`);`
367
368			`OUT_REG ad_iob14`
369			`(`
370			`.reset_in ( reset_in ),`
371			`.clk_in ( clk_in) ,`
372			`.dat_en_in ( ad_load_ctrl_mlow ),`
373			`.en_en_in ( 1'b1 ),`
374			`.dat_in ( temp_ad[14] ) ,`
375			`.en_in ( ad_en_ctrl_mlow ) ,`
376			`.en_out ( ad_en_out[14] ),`
377			`.dat_out ( ad_out[14] )`
378			`);`
379
380			`OUT_REG ad_iob15`
381			`(`
382			`.reset_in ( reset_in ),`
383			`.clk_in ( clk_in) ,`
384			`.dat_en_in ( ad_load_ctrl_mlow ),`
385			`.en_en_in ( 1'b1 ),`
386			`.dat_in ( temp_ad[15] ) ,`
387			`.en_in ( ad_en_ctrl_mlow ) ,`
388			`.en_out ( ad_en_out[15] ),`
389			`.dat_out ( ad_out[15] )`
390			`);`
391
392			`OUT_REG ad_iob16`
393			`(`
394			`.reset_in ( reset_in ),`
395			`.clk_in ( clk_in) ,`
396			`.dat_en_in ( ad_load_ctrl_mhigh ),`
397			`.en_en_in ( 1'b1 ),`
398			`.dat_in ( temp_ad[16] ) ,`
399			`.en_in ( ad_en_ctrl_mhigh ) ,`
400			`.en_out ( ad_en_out[16] ),`
401			`.dat_out ( ad_out[16] )`
402			`);`
403
404			`OUT_REG ad_iob17`
405			`(`
406			`.reset_in ( reset_in ),`
407			`.clk_in ( clk_in) ,`
408			`.dat_en_in ( ad_load_ctrl_mhigh ),`
409			`.en_en_in ( 1'b1 ),`
410			`.dat_in ( temp_ad[17] ) ,`
411			`.en_in ( ad_en_ctrl_mhigh ) ,`
412			`.en_out ( ad_en_out[17] ),`
413			`.dat_out ( ad_out[17] )`
414			`);`
415
416			`OUT_REG ad_iob18`
417			`(`
418			`.reset_in ( reset_in ),`
419			`.clk_in ( clk_in) ,`
420			`.dat_en_in ( ad_load_ctrl_mhigh ),`
421			`.en_en_in ( 1'b1 ),`
422			`.dat_in ( temp_ad[18] ) ,`
423			`.en_in ( ad_en_ctrl_mhigh ) ,`
424			`.en_out ( ad_en_out[18] ),`
425			`.dat_out ( ad_out[18] )`
426			`);`
427
428			`OUT_REG ad_iob19`
429			`(`
430			`.reset_in ( reset_in ),`
431			`.clk_in ( clk_in) ,`
432			`.dat_en_in ( ad_load_ctrl_mhigh ),`
433			`.en_en_in ( 1'b1 ),`
434			`.dat_in ( temp_ad[19] ) ,`
435			`.en_in ( ad_en_ctrl_mhigh ) ,`
436			`.en_out ( ad_en_out[19] ),`
437			`.dat_out ( ad_out[19] )`
438			`);`
439
440			`OUT_REG ad_iob20`
441			`(`
442			`.reset_in ( reset_in ),`
443			`.clk_in ( clk_in) ,`
444			`.dat_en_in ( ad_load_ctrl_mhigh ),`
445			`.en_en_in ( 1'b1 ),`
446			`.dat_in ( temp_ad[20] ) ,`
447			`.en_in ( ad_en_ctrl_mhigh ) ,`
448			`.en_out ( ad_en_out[20] ),`
449			`.dat_out ( ad_out[20] )`
450			`);`
451
452			`OUT_REG ad_iob21`
453			`(`
454			`.reset_in ( reset_in ),`
455			`.clk_in ( clk_in) ,`
456			`.dat_en_in ( ad_load_ctrl_mhigh ),`
457			`.en_en_in ( 1'b1 ),`
458			`.dat_in ( temp_ad[21] ) ,`
459			`.en_in ( ad_en_ctrl_mhigh ) ,`
460			`.en_out ( ad_en_out[21] ),`
461			`.dat_out ( ad_out[21] )`
462			`);`
463
464			`OUT_REG ad_iob22`
465			`(`
466			`.reset_in ( reset_in ),`
467			`.clk_in ( clk_in) ,`
468			`.dat_en_in ( ad_load_ctrl_mhigh ),`
469			`.en_en_in ( 1'b1 ),`
470			`.dat_in ( temp_ad[22] ) ,`
471			`.en_in ( ad_en_ctrl_mhigh ) ,`
472			`.en_out ( ad_en_out[22] ),`
473			`.dat_out ( ad_out[22] )`
474			`);`
475
476			`OUT_REG ad_iob23`
477			`(`
478			`.reset_in ( reset_in ),`
479			`.clk_in ( clk_in) ,`
480			`.dat_en_in ( ad_load_ctrl_mhigh ),`
481			`.en_en_in ( 1'b1 ),`
482			`.dat_in ( temp_ad[23] ) ,`
483			`.en_in ( ad_en_ctrl_mhigh ) ,`
484			`.en_out ( ad_en_out[23] ),`
485			`.dat_out ( ad_out[23] )`
486			`);`
487
488			`OUT_REG ad_iob24`
489			`(`
490			`.reset_in ( reset_in ),`
491			`.clk_in ( clk_in) ,`
492			`.dat_en_in ( ad_load_ctrl_high ),`
493			`.en_en_in ( 1'b1 ),`
494			`.dat_in ( temp_ad[24] ) ,`
495			`.en_in ( ad_en_ctrl_high ) ,`
496			`.en_out ( ad_en_out[24] ),`
497			`.dat_out ( ad_out[24] )`
498			`);`
499
500			`OUT_REG ad_iob25`
501			`(`
502			`.reset_in ( reset_in ),`
503			`.clk_in ( clk_in) ,`
504			`.dat_en_in ( ad_load_ctrl_high ),`
505			`.en_en_in ( 1'b1 ),`
506			`.dat_in ( temp_ad[25] ) ,`
507			`.en_in ( ad_en_ctrl_high ) ,`
508			`.en_out ( ad_en_out[25] ),`
509			`.dat_out ( ad_out[25] )`
510			`);`
511
512			`OUT_REG ad_iob26`
513			`(`
514			`.reset_in ( reset_in ),`
515			`.clk_in ( clk_in) ,`
516			`.dat_en_in ( ad_load_ctrl_high ),`
517			`.en_en_in ( 1'b1 ),`
518			`.dat_in ( temp_ad[26] ) ,`
519			`.en_in ( ad_en_ctrl_high ) ,`
520			`.en_out ( ad_en_out[26] ),`
521			`.dat_out ( ad_out[26] )`
522			`);`
523
524			`OUT_REG ad_iob27`
525			`(`
526			`.reset_in ( reset_in ),`
527			`.clk_in ( clk_in) ,`
528			`.dat_en_in ( ad_load_ctrl_high ),`
529			`.en_en_in ( 1'b1 ),`
530			`.dat_in ( temp_ad[27] ) ,`
531			`.en_in ( ad_en_ctrl_high ) ,`
532			`.en_out ( ad_en_out[27] ),`
533			`.dat_out ( ad_out[27] )`
534			`);`
535
536			`OUT_REG ad_iob28`
537			`(`
538			`.reset_in ( reset_in ),`
539			`.clk_in ( clk_in) ,`
540			`.dat_en_in ( ad_load_ctrl_high ),`
541			`.en_en_in ( 1'b1 ),`
542			`.dat_in ( temp_ad[28] ) ,`
543			`.en_in ( ad_en_ctrl_high ) ,`
544			`.en_out ( ad_en_out[28] ),`
545			`.dat_out ( ad_out[28] )`
546			`);`
547
548			`OUT_REG ad_iob29`
549			`(`
550			`.reset_in ( reset_in ),`
551			`.clk_in ( clk_in) ,`
552			`.dat_en_in ( ad_load_ctrl_high ),`
553			`.en_en_in ( 1'b1 ),`
554			`.dat_in ( temp_ad[29] ) ,`
555			`.en_in ( ad_en_ctrl_high ) ,`
556			`.en_out ( ad_en_out[29] ),`
557			`.dat_out ( ad_out[29] )`
558			`);`
559
560			`OUT_REG ad_iob30`
561			`(`
562			`.reset_in ( reset_in ),`
563			`.clk_in ( clk_in) ,`
564			`.dat_en_in ( ad_load_ctrl_high ),`
565			`.en_en_in ( 1'b1 ),`
566			`.dat_in ( temp_ad[30] ) ,`
567			`.en_in ( ad_en_ctrl_high ) ,`
568			`.en_out ( ad_en_out[30] ),`
569			`.dat_out ( ad_out[30] )`
570			`);`
571
572			`OUT_REG ad_iob31`
573			`(`
574			`.reset_in ( reset_in ),`
575			`.clk_in ( clk_in) ,`
576			`.dat_en_in ( ad_load_ctrl_high ),`
577			`.en_en_in ( 1'b1 ),`
578			`.dat_in ( temp_ad[31] ) ,`
579			`.en_in ( ad_en_ctrl_high ) ,`
580			`.en_out ( ad_en_out[31] ),`
581			`.dat_out ( ad_out[31] )`
582			`);`
583
584			`wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;`
585			`wire [3:0] cbe_en_ctrl = {4{ cbe_en_in }} ;`
586
587			`OUT_REG cbe_iob0`
588			`(`
589			`.reset_in ( reset_in ),`
590			`.clk_in ( clk_in) ,`
591			`.dat_en_in ( cbe_load_ctrl[0] ),`
592			`.en_en_in ( 1'b1 ),`
593			`.dat_in ( cbe_in[0] ) ,`
594			`.en_in ( cbe_en_ctrl[0] ) ,`
595			`.en_out ( cbe_en_out[0] ),`
596			`.dat_out ( cbe_out[0] )`
597			`);`
598
599			`OUT_REG cbe_iob1`
600			`(`
601			`.reset_in ( reset_in ),`
602			`.clk_in ( clk_in) ,`
603			`.dat_en_in ( cbe_load_ctrl[1] ),`
604			`.en_en_in ( 1'b1 ),`
605			`.dat_in ( cbe_in[1] ) ,`
606			`.en_in ( cbe_en_ctrl[1] ) ,`
607			`.en_out ( cbe_en_out[1] ),`
608			`.dat_out ( cbe_out[1] )`
609			`);`
610
611			`OUT_REG cbe_iob2`
612			`(`
613			`.reset_in ( reset_in ),`
614			`.clk_in ( clk_in) ,`
615			`.dat_en_in ( cbe_load_ctrl[2] ),`
616			`.en_en_in ( 1'b1 ),`
617			`.dat_in ( cbe_in[2] ) ,`
618			`.en_in ( cbe_en_ctrl[2] ) ,`
619			`.en_out ( cbe_en_out[2] ),`
620			`.dat_out ( cbe_out[2] )`
621			`);`
622
623			`OUT_REG cbe_iob3`
624			`(`
625			`.reset_in ( reset_in ),`
626			`.clk_in ( clk_in) ,`
627			`.dat_en_in ( cbe_load_ctrl[3] ),`
628			`.en_en_in ( 1'b1 ),`
629			`.dat_in ( cbe_in[3] ) ,`
630			`.en_in ( cbe_en_ctrl[3] ) ,`
631			`.en_out ( cbe_en_out[3] ),`
632			`.dat_out ( cbe_out[3] )`
633			`);`
634
635			`OUT_REG frame_iob`
636			`(`
637			`.reset_in ( reset_in ),`
638			`.clk_in ( clk_in) ,`
639			`.dat_en_in ( frame_load_in ),`
640			`.en_en_in ( 1'b1 ),`
641			`.dat_in ( frame_in ) ,`
642			`.en_in ( frame_en_in ) ,`
643			`.en_out ( frame_en_out ),`
644			`.dat_out ( frame_out )`
645			`);`
646
647			`OUT_REG irdy_iob`
648			`(`
649			`.reset_in ( reset_in ),`
650			`.clk_in ( clk_in) ,`
651			`.dat_en_in ( 1'b1 ),`
652			`.en_en_in ( 1'b1 ),`
653			`.dat_in ( irdy_in ) ,`
654			`.en_in ( irdy_en_in ) ,`
655			`.en_out ( irdy_en_out ),`
656			`.dat_out ( irdy_out )`
657			`);`
658
659			`OUT_REG trdy_iob`
660			`(`
661			`.reset_in ( reset_in ),`
662			`.clk_in ( clk_in) ,`
663			`.dat_en_in ( 1'b1 ),`
664			`.en_en_in ( 1'b1 ),`
665			`.dat_in ( trdy_in ) ,`
666			`.en_in ( trdy_en_in ) ,`
667			`.en_out ( trdy_en_out ),`
668			`.dat_out ( trdy_out )`
669			`);`
670
671			`OUT_REG stop_iob`
672			`(`
673			`.reset_in ( reset_in ),`
674			`.clk_in ( clk_in) ,`
675			`.dat_en_in ( 1'b1 ),`
676			`.en_en_in ( 1'b1 ),`
677			`.dat_in ( stop_in ) ,`
678			`.en_in ( stop_en_in ) ,`
679			`.en_out ( stop_en_out ),`
680			`.dat_out ( stop_out )`
681			`);`
682
683			`OUT_REG devsel_iob`
684			`(`
685			`.reset_in ( reset_in ),`
686			`.clk_in ( clk_in) ,`
687			`.dat_en_in ( 1'b1 ),`
688			`.en_en_in ( 1'b1 ),`
689			`.dat_in ( devsel_in ) ,`
690			`.en_in ( devsel_en_in ) ,`
691			`.en_out ( devsel_en_out ),`
692			`.dat_out ( devsel_out )`
693			`);`
694
695			`OUT_REG par_iob`
696			`(`
697			`.reset_in ( reset_in ),`
698			`.clk_in ( clk_in) ,`
699			`.dat_en_in ( 1'b1 ),`
700			`.en_en_in ( 1'b1 ),`
701			`.dat_in ( par_in ) ,`
702			`.en_in ( par_en_in ) ,`
703			`.en_out ( par_en_out ),`
704			`.dat_out ( par_out )`
705			`);`
706
707			`OUT_REG perr_iob`
708			`(`
709			`.reset_in ( reset_in ),`
710			`.clk_in ( clk_in) ,`
711			`.dat_en_in ( 1'b1 ),`
712			`.en_en_in ( 1'b1 ),`
713			`.dat_in ( perr_in ) ,`
714			`.en_in ( perr_en_in ) ,`
715			`.en_out ( perr_en_out ),`
716			`.dat_out ( perr_out )`
717			`);`
718
719			`OUT_REG serr_iob`
720			`(`
721			`.reset_in ( reset_in ),`
722			`.clk_in ( clk_in) ,`
723			`.dat_en_in ( 1'b1 ),`
724			`.en_en_in ( 1'b1 ),`
725			`.dat_in ( serr_in ) ,`
726			`.en_in ( serr_en_in ) ,`
727			`.en_out ( serr_en_out ),`
728			`.dat_out ( serr_out )`
729			`);`
730
731			`OUT_REG req_iob`
732			`(`
733			`.reset_in ( reset_in ),`
734			`.clk_in ( clk_in) ,`
735			`.dat_en_in ( 1'b1 ),`
736			`.en_en_in ( 1'b1 ),`
737			`.dat_in ( req_in ) ,`
738			`.en_in ( 1'b1 ) ,`
739			`.en_out ( req_en_out ),`
740			`.dat_out ( req_out )`
741			`);`
742
743			`endmodule`