1 |
2 |
mihad |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// File name: pci_target_unit.v ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// This file is part of the "PCI bridge" project ////
|
6 |
|
|
//// http://www.opencores.org/cores/pci/ ////
|
7 |
|
|
//// ////
|
8 |
|
|
//// Author(s): ////
|
9 |
|
|
//// - Tadej Markovic, tadej@opencores.org ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// All additional information is avaliable in the README.txt ////
|
12 |
|
|
//// file. ////
|
13 |
|
|
//// ////
|
14 |
|
|
//// ////
|
15 |
|
|
//////////////////////////////////////////////////////////////////////
|
16 |
|
|
//// ////
|
17 |
|
|
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
|
18 |
|
|
//// ////
|
19 |
|
|
//// This source file may be used and distributed without ////
|
20 |
|
|
//// restriction provided that this copyright statement is not ////
|
21 |
|
|
//// removed from the file and that any derivative work contains ////
|
22 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
23 |
|
|
//// ////
|
24 |
|
|
//// This source file is free software; you can redistribute it ////
|
25 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
26 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
27 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
28 |
|
|
//// later version. ////
|
29 |
|
|
//// ////
|
30 |
|
|
//// This source is distributed in the hope that it will be ////
|
31 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
32 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
33 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
34 |
|
|
//// details. ////
|
35 |
|
|
//// ////
|
36 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
37 |
|
|
//// Public License along with this source; if not, download it ////
|
38 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
39 |
|
|
//// ////
|
40 |
|
|
//////////////////////////////////////////////////////////////////////
|
41 |
|
|
//
|
42 |
|
|
// CVS Revision History
|
43 |
|
|
//
|
44 |
|
|
// $Log: not supported by cvs2svn $
|
45 |
108 |
tadejm |
// Revision 1.11 2003/01/27 16:49:31 mihad
|
46 |
|
|
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
|
47 |
|
|
//
|
48 |
77 |
mihad |
// Revision 1.10 2002/10/18 03:36:37 tadejm
|
49 |
|
|
// Changed wrong signal name scanb_sen into scanb_en.
|
50 |
|
|
//
|
51 |
68 |
tadejm |
// Revision 1.9 2002/10/17 22:51:08 tadejm
|
52 |
|
|
// Changed BIST signals for RAMs.
|
53 |
|
|
//
|
54 |
67 |
tadejm |
// Revision 1.8 2002/10/11 10:09:01 mihad
|
55 |
|
|
// Added additional testcase and changed rst name in BIST to trst
|
56 |
|
|
//
|
57 |
63 |
mihad |
// Revision 1.7 2002/10/08 17:17:05 mihad
|
58 |
|
|
// Added BIST signals for RAMs.
|
59 |
|
|
//
|
60 |
62 |
mihad |
// Revision 1.6 2002/09/25 15:53:52 mihad
|
61 |
|
|
// Removed all logic from asynchronous reset network
|
62 |
|
|
//
|
63 |
58 |
mihad |
// Revision 1.5 2002/03/05 11:53:47 mihad
|
64 |
|
|
// Added some testcases, removed un-needed fifo signals
|
65 |
|
|
//
|
66 |
33 |
mihad |
// Revision 1.4 2002/02/19 16:32:37 mihad
|
67 |
|
|
// Modified testbench and fixed some bugs
|
68 |
|
|
//
|
69 |
26 |
mihad |
// Revision 1.3 2002/02/01 15:25:13 mihad
|
70 |
|
|
// Repaired a few bugs, updated specification, added test bench files and design document
|
71 |
|
|
//
|
72 |
21 |
mihad |
// Revision 1.2 2001/10/05 08:14:30 mihad
|
73 |
|
|
// Updated all files with inclusion of timescale file for simulation purposes.
|
74 |
|
|
//
|
75 |
6 |
mihad |
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
|
76 |
|
|
// New project directory structure
|
77 |
2 |
mihad |
//
|
78 |
6 |
mihad |
//
|
79 |
2 |
mihad |
|
80 |
|
|
// Module instantiates and connects other modules lower in hierarcy
|
81 |
|
|
// PCI target unit consists of modules that together form datapath
|
82 |
|
|
// between external WISHBONE slaves and external PCI initiators
|
83 |
21 |
mihad |
`include "pci_constants.v"
|
84 |
|
|
|
85 |
|
|
// synopsys translate_off
|
86 |
6 |
mihad |
`include "timescale.v"
|
87 |
21 |
mihad |
// synopsys translate_on
|
88 |
2 |
mihad |
|
89 |
77 |
mihad |
module pci_target_unit
|
90 |
2 |
mihad |
(
|
91 |
|
|
reset_in,
|
92 |
|
|
wb_clock_in,
|
93 |
|
|
pci_clock_in,
|
94 |
|
|
ADR_O,
|
95 |
|
|
MDATA_O,
|
96 |
|
|
MDATA_I,
|
97 |
|
|
CYC_O,
|
98 |
|
|
STB_O,
|
99 |
|
|
WE_O,
|
100 |
|
|
SEL_O,
|
101 |
|
|
ACK_I,
|
102 |
|
|
RTY_I,
|
103 |
|
|
ERR_I,
|
104 |
|
|
CAB_O,
|
105 |
21 |
mihad |
pciu_mem_enable_in,
|
106 |
|
|
pciu_io_enable_in,
|
107 |
2 |
mihad |
pciu_map_in,
|
108 |
|
|
pciu_pref_en_in,
|
109 |
21 |
mihad |
pciu_conf_data_in,
|
110 |
2 |
mihad |
pciu_wbw_fifo_empty_in,
|
111 |
21 |
mihad |
pciu_wbu_del_read_comp_pending_in,
|
112 |
2 |
mihad |
pciu_wbu_frame_en_in,
|
113 |
21 |
mihad |
pciu_bar0_in,
|
114 |
|
|
pciu_bar1_in,
|
115 |
|
|
pciu_bar2_in,
|
116 |
|
|
pciu_bar3_in,
|
117 |
|
|
pciu_bar4_in,
|
118 |
|
|
pciu_bar5_in,
|
119 |
|
|
pciu_am0_in,
|
120 |
|
|
pciu_am1_in,
|
121 |
|
|
pciu_am2_in,
|
122 |
|
|
pciu_am3_in,
|
123 |
|
|
pciu_am4_in,
|
124 |
|
|
pciu_am5_in,
|
125 |
|
|
pciu_ta0_in,
|
126 |
|
|
pciu_ta1_in,
|
127 |
|
|
pciu_ta2_in,
|
128 |
|
|
pciu_ta3_in,
|
129 |
|
|
pciu_ta4_in,
|
130 |
|
|
pciu_ta5_in,
|
131 |
|
|
pciu_at_en_in,
|
132 |
|
|
pciu_cache_line_size_in,
|
133 |
|
|
pciu_cache_lsize_not_zero_in,
|
134 |
|
|
pciu_pciif_frame_in,
|
135 |
|
|
pciu_pciif_irdy_in,
|
136 |
|
|
pciu_pciif_idsel_in,
|
137 |
|
|
pciu_pciif_frame_reg_in,
|
138 |
|
|
pciu_pciif_irdy_reg_in,
|
139 |
|
|
pciu_pciif_idsel_reg_in,
|
140 |
|
|
pciu_pciif_ad_reg_in,
|
141 |
|
|
pciu_pciif_cbe_reg_in,
|
142 |
108 |
tadejm |
pciu_pciif_cbe_in,
|
143 |
21 |
mihad |
pciu_pciif_bckp_trdy_en_in,
|
144 |
|
|
pciu_pciif_bckp_devsel_in,
|
145 |
|
|
pciu_pciif_bckp_trdy_in,
|
146 |
|
|
pciu_pciif_bckp_stop_in,
|
147 |
|
|
pciu_pciif_trdy_reg_in,
|
148 |
|
|
pciu_pciif_stop_reg_in,
|
149 |
|
|
pciu_pciif_trdy_out,
|
150 |
|
|
pciu_pciif_stop_out,
|
151 |
|
|
pciu_pciif_devsel_out,
|
152 |
|
|
pciu_pciif_trdy_en_out,
|
153 |
|
|
pciu_pciif_stop_en_out,
|
154 |
|
|
pciu_pciif_devsel_en_out,
|
155 |
|
|
pciu_ad_load_out,
|
156 |
|
|
pciu_ad_load_on_transfer_out,
|
157 |
|
|
pciu_pciif_ad_out,
|
158 |
|
|
pciu_pciif_ad_en_out,
|
159 |
|
|
pciu_pciif_tabort_set_out,
|
160 |
|
|
pciu_err_addr_out,
|
161 |
2 |
mihad |
pciu_err_bc_out,
|
162 |
|
|
pciu_err_data_out,
|
163 |
21 |
mihad |
pciu_err_be_out,
|
164 |
|
|
pciu_err_signal_out,
|
165 |
|
|
pciu_err_source_out,
|
166 |
2 |
mihad |
pciu_err_rty_exp_out,
|
167 |
|
|
pciu_conf_offset_out,
|
168 |
|
|
pciu_conf_renable_out,
|
169 |
|
|
pciu_conf_wenable_out,
|
170 |
21 |
mihad |
pciu_conf_be_out,
|
171 |
|
|
pciu_conf_data_out,
|
172 |
2 |
mihad |
pciu_conf_select_out,
|
173 |
|
|
pciu_pci_drcomp_pending_out,
|
174 |
|
|
pciu_pciw_fifo_empty_out
|
175 |
62 |
mihad |
|
176 |
|
|
`ifdef PCI_BIST
|
177 |
|
|
,
|
178 |
|
|
// debug chain signals
|
179 |
67 |
tadejm |
scanb_rst, // bist scan reset
|
180 |
|
|
scanb_clk, // bist scan clock
|
181 |
|
|
scanb_si, // bist scan serial in
|
182 |
|
|
scanb_so, // bist scan serial out
|
183 |
68 |
tadejm |
scanb_en // bist scan shift enable
|
184 |
62 |
mihad |
`endif
|
185 |
2 |
mihad |
);
|
186 |
|
|
|
187 |
|
|
input reset_in,
|
188 |
|
|
wb_clock_in,
|
189 |
|
|
pci_clock_in ;
|
190 |
|
|
|
191 |
21 |
mihad |
output [31:0] ADR_O ;
|
192 |
2 |
mihad |
output [31:0] MDATA_O ;
|
193 |
|
|
input [31:0] MDATA_I ;
|
194 |
|
|
output CYC_O ;
|
195 |
|
|
output STB_O ;
|
196 |
|
|
output WE_O ;
|
197 |
|
|
output [3:0] SEL_O ;
|
198 |
|
|
input ACK_I ;
|
199 |
|
|
input RTY_I ;
|
200 |
|
|
input ERR_I ;
|
201 |
|
|
output CAB_O ;
|
202 |
|
|
|
203 |
|
|
input pciu_wbw_fifo_empty_in ;
|
204 |
21 |
mihad |
input pciu_wbu_del_read_comp_pending_in ;
|
205 |
|
|
input pciu_wbu_frame_en_in ;
|
206 |
2 |
mihad |
|
207 |
|
|
input pciu_mem_enable_in ;
|
208 |
|
|
input pciu_io_enable_in ;
|
209 |
|
|
input [5:0] pciu_map_in ;
|
210 |
|
|
input [5:0] pciu_pref_en_in ;
|
211 |
|
|
input [31:0] pciu_conf_data_in ;
|
212 |
|
|
|
213 |
21 |
mihad |
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar0_in ;
|
214 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar1_in ;
|
215 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar2_in ;
|
216 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar3_in ;
|
217 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar4_in ;
|
218 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar5_in ;
|
219 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am0_in ;
|
220 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am1_in ;
|
221 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am2_in ;
|
222 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am3_in ;
|
223 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am4_in ;
|
224 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am5_in ;
|
225 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta0_in ;
|
226 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta1_in ;
|
227 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta2_in ;
|
228 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta3_in ;
|
229 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta4_in ;
|
230 |
|
|
input [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta5_in ;
|
231 |
2 |
mihad |
input [5:0] pciu_at_en_in ;
|
232 |
|
|
|
233 |
|
|
input [7:0] pciu_cache_line_size_in ;
|
234 |
21 |
mihad |
input pciu_cache_lsize_not_zero_in ;
|
235 |
2 |
mihad |
|
236 |
21 |
mihad |
input pciu_pciif_frame_in ;
|
237 |
|
|
input pciu_pciif_irdy_in ;
|
238 |
2 |
mihad |
input pciu_pciif_idsel_in ;
|
239 |
|
|
input pciu_pciif_frame_reg_in ;
|
240 |
|
|
input pciu_pciif_irdy_reg_in ;
|
241 |
|
|
input pciu_pciif_idsel_reg_in ;
|
242 |
|
|
input [31:0] pciu_pciif_ad_reg_in ;
|
243 |
|
|
input [3:0] pciu_pciif_cbe_reg_in ;
|
244 |
108 |
tadejm |
input [3:0] pciu_pciif_cbe_in;
|
245 |
21 |
mihad |
input pciu_pciif_bckp_trdy_en_in ;
|
246 |
|
|
input pciu_pciif_bckp_devsel_in ;
|
247 |
|
|
input pciu_pciif_bckp_trdy_in ;
|
248 |
|
|
input pciu_pciif_bckp_stop_in ;
|
249 |
|
|
input pciu_pciif_trdy_reg_in ;
|
250 |
|
|
input pciu_pciif_stop_reg_in ;
|
251 |
2 |
mihad |
|
252 |
|
|
|
253 |
21 |
mihad |
output pciu_pciif_trdy_out ;
|
254 |
|
|
output pciu_pciif_stop_out ;
|
255 |
|
|
output pciu_pciif_devsel_out ;
|
256 |
2 |
mihad |
output pciu_pciif_trdy_en_out ;
|
257 |
|
|
output pciu_pciif_stop_en_out ;
|
258 |
|
|
output pciu_pciif_devsel_en_out ;
|
259 |
21 |
mihad |
output pciu_ad_load_out ;
|
260 |
|
|
output pciu_ad_load_on_transfer_out ;
|
261 |
|
|
output [31:0] pciu_pciif_ad_out ;
|
262 |
|
|
output pciu_pciif_ad_en_out ;
|
263 |
|
|
output pciu_pciif_tabort_set_out ;
|
264 |
2 |
mihad |
|
265 |
|
|
output [31:0] pciu_err_addr_out ;
|
266 |
|
|
output [3:0] pciu_err_bc_out ;
|
267 |
21 |
mihad |
output [31:0] pciu_err_data_out ;
|
268 |
|
|
output [3:0] pciu_err_be_out ;
|
269 |
2 |
mihad |
output pciu_err_signal_out ;
|
270 |
|
|
output pciu_err_source_out ;
|
271 |
|
|
output pciu_err_rty_exp_out ;
|
272 |
|
|
|
273 |
21 |
mihad |
output pciu_conf_select_out ;
|
274 |
2 |
mihad |
output [11:0] pciu_conf_offset_out ;
|
275 |
|
|
output pciu_conf_renable_out ;
|
276 |
|
|
output pciu_conf_wenable_out ;
|
277 |
|
|
output [3:0] pciu_conf_be_out ;
|
278 |
|
|
output [31:0] pciu_conf_data_out ;
|
279 |
|
|
|
280 |
21 |
mihad |
output pciu_pci_drcomp_pending_out ;
|
281 |
|
|
output pciu_pciw_fifo_empty_out ;
|
282 |
2 |
mihad |
|
283 |
62 |
mihad |
`ifdef PCI_BIST
|
284 |
|
|
/*-----------------------------------------------------
|
285 |
|
|
BIST debug chain port signals
|
286 |
|
|
-----------------------------------------------------*/
|
287 |
67 |
tadejm |
input scanb_rst; // bist scan reset
|
288 |
|
|
input scanb_clk; // bist scan clock
|
289 |
|
|
input scanb_si; // bist scan serial in
|
290 |
|
|
output scanb_so; // bist scan serial out
|
291 |
68 |
tadejm |
input scanb_en; // bist scan shift enable
|
292 |
62 |
mihad |
`endif
|
293 |
2 |
mihad |
|
294 |
62 |
mihad |
|
295 |
2 |
mihad |
// pci target state machine and interface outputs
|
296 |
|
|
wire pcit_sm_trdy_out ;
|
297 |
|
|
wire pcit_sm_stop_out ;
|
298 |
|
|
wire pcit_sm_devsel_out ;
|
299 |
|
|
wire pcit_sm_trdy_en_out ;
|
300 |
|
|
wire pcit_sm_stop_en_out ;
|
301 |
|
|
wire pcit_sm_devsel_en_out ;
|
302 |
21 |
mihad |
wire pcit_sm_ad_load_out ;
|
303 |
|
|
wire pcit_sm_ad_load_on_transfer_out ;
|
304 |
2 |
mihad |
wire [31:0] pcit_sm_ad_out ;
|
305 |
|
|
wire pcit_sm_ad_en_out ;
|
306 |
|
|
wire [31:0] pcit_sm_address_out ;
|
307 |
|
|
wire [3:0] pcit_sm_bc_out ;
|
308 |
21 |
mihad |
wire pcit_sm_bc0_out ;
|
309 |
2 |
mihad |
wire [31:0] pcit_sm_data_out ;
|
310 |
|
|
wire [3:0] pcit_sm_be_out ;
|
311 |
108 |
tadejm |
wire [3:0] pcit_sm_next_be_out ;
|
312 |
2 |
mihad |
wire pcit_sm_req_out ;
|
313 |
|
|
wire pcit_sm_rdy_out ;
|
314 |
21 |
mihad |
wire pcit_sm_addr_phase_out ;
|
315 |
|
|
wire pcit_sm_bckp_devsel_out ;
|
316 |
|
|
wire pcit_sm_bckp_trdy_out ;
|
317 |
|
|
wire pcit_sm_bckp_stop_out ;
|
318 |
|
|
wire pcit_sm_last_reg_out ;
|
319 |
|
|
wire pcit_sm_frame_reg_out ;
|
320 |
|
|
wire pcit_sm_fetch_pcir_fifo_out ;
|
321 |
|
|
wire pcit_sm_load_medium_reg_out ;
|
322 |
|
|
wire pcit_sm_sel_fifo_mreg_out ;
|
323 |
|
|
wire pcit_sm_sel_conf_fifo_out ;
|
324 |
|
|
wire pcit_sm_fetch_conf_out ;
|
325 |
|
|
wire pcit_sm_load_to_pciw_fifo_out ;
|
326 |
|
|
wire pcit_sm_load_to_conf_out ;
|
327 |
2 |
mihad |
|
328 |
21 |
mihad |
wire pcit_sm_target_abort_set_out ; // to conf space
|
329 |
2 |
mihad |
|
330 |
21 |
mihad |
assign pciu_pciif_trdy_out = pcit_sm_trdy_out ;
|
331 |
|
|
assign pciu_pciif_stop_out = pcit_sm_stop_out ;
|
332 |
|
|
assign pciu_pciif_devsel_out = pcit_sm_devsel_out ;
|
333 |
|
|
assign pciu_pciif_trdy_en_out = pcit_sm_trdy_en_out ;
|
334 |
|
|
assign pciu_pciif_stop_en_out = pcit_sm_stop_en_out ;
|
335 |
|
|
assign pciu_pciif_devsel_en_out = pcit_sm_devsel_en_out ;
|
336 |
|
|
assign pciu_ad_load_out = pcit_sm_ad_load_out ;
|
337 |
|
|
assign pciu_ad_load_on_transfer_out = pcit_sm_ad_load_on_transfer_out ;
|
338 |
|
|
assign pciu_pciif_ad_out = pcit_sm_ad_out ;
|
339 |
|
|
assign pciu_pciif_ad_en_out = pcit_sm_ad_en_out ;
|
340 |
|
|
assign pciu_pciif_tabort_set_out = pcit_sm_target_abort_set_out ;
|
341 |
2 |
mihad |
|
342 |
|
|
wire pcit_if_addr_claim_out ;
|
343 |
|
|
wire [31:0] pcit_if_data_out ;
|
344 |
|
|
wire pcit_if_same_read_out ;
|
345 |
|
|
wire pcit_if_norm_access_to_config_out ;
|
346 |
|
|
wire pcit_if_read_completed_out ;
|
347 |
|
|
wire pcit_if_read_processing_out ;
|
348 |
|
|
wire pcit_if_target_abort_out ;
|
349 |
|
|
wire pcit_if_disconect_wo_data_out ;
|
350 |
21 |
mihad |
wire pcit_if_disconect_w_data_out ;
|
351 |
2 |
mihad |
wire pcit_if_pciw_fifo_full_out ;
|
352 |
|
|
wire pcit_if_pcir_fifo_data_err_out ;
|
353 |
|
|
wire pcit_if_wbw_fifo_empty_out ;
|
354 |
21 |
mihad |
wire pcit_if_wbu_del_read_comp_pending_out ;
|
355 |
2 |
mihad |
wire pcit_if_req_out ;
|
356 |
|
|
wire pcit_if_done_out ;
|
357 |
|
|
wire pcit_if_in_progress_out ;
|
358 |
|
|
wire [31:0] pcit_if_addr_out ;
|
359 |
|
|
wire [3:0] pcit_if_be_out ;
|
360 |
|
|
wire pcit_if_we_out ;
|
361 |
|
|
wire [3:0] pcit_if_bc_out ;
|
362 |
21 |
mihad |
wire pcit_if_burst_ok_out ;
|
363 |
2 |
mihad |
wire pcit_if_pcir_fifo_renable_out ;
|
364 |
|
|
wire pcit_if_pcir_fifo_flush_out ;
|
365 |
|
|
wire pcit_if_pciw_fifo_wenable_out ;
|
366 |
|
|
wire [31:0] pcit_if_pciw_fifo_addr_data_out ;
|
367 |
|
|
wire [3:0] pcit_if_pciw_fifo_cbe_out ;
|
368 |
|
|
wire [3:0] pcit_if_pciw_fifo_control_out ;
|
369 |
|
|
wire pcit_if_conf_hit_out ;
|
370 |
|
|
wire [11:0] pcit_if_conf_addr_out ;
|
371 |
|
|
wire [31:0] pcit_if_conf_data_out ;
|
372 |
|
|
wire [3:0] pcit_if_conf_be_out ;
|
373 |
|
|
wire pcit_if_conf_we_out ;
|
374 |
|
|
wire pcit_if_conf_re_out ;
|
375 |
|
|
|
376 |
|
|
// pci target state machine outputs
|
377 |
|
|
// pci interface signals
|
378 |
21 |
mihad |
assign pciu_conf_select_out = pcit_if_conf_hit_out ;
|
379 |
|
|
assign pciu_conf_offset_out = pcit_if_conf_addr_out ;
|
380 |
|
|
assign pciu_conf_renable_out = pcit_if_conf_re_out ;
|
381 |
|
|
assign pciu_conf_wenable_out = pcit_if_conf_we_out ;
|
382 |
|
|
assign pciu_conf_be_out = pcit_if_conf_be_out ;
|
383 |
|
|
assign pciu_conf_data_out = pcit_if_conf_data_out ;
|
384 |
2 |
mihad |
|
385 |
|
|
// wishbone master state machine outputs
|
386 |
21 |
mihad |
wire wbm_sm_wb_read_done ;
|
387 |
26 |
mihad |
wire wbm_sm_write_attempt ;
|
388 |
2 |
mihad |
wire wbm_sm_pcir_fifo_wenable_out ;
|
389 |
|
|
wire [31:0] wbm_sm_pcir_fifo_data_out ;
|
390 |
|
|
wire [3:0] wbm_sm_pcir_fifo_be_out ;
|
391 |
|
|
wire [3:0] wbm_sm_pcir_fifo_control_out ;
|
392 |
|
|
wire wbm_sm_pciw_fifo_renable_out ;
|
393 |
|
|
wire wbm_sm_pci_error_sig_out ;
|
394 |
|
|
wire [3:0] wbm_sm_pci_error_bc ;
|
395 |
|
|
wire wbm_sm_write_rty_cnt_exp_out ;
|
396 |
21 |
mihad |
wire wbm_sm_error_source_out ;
|
397 |
2 |
mihad |
wire wbm_sm_read_rty_cnt_exp_out ;
|
398 |
|
|
wire wbm_sm_cyc_out ;
|
399 |
|
|
wire wbm_sm_stb_out ;
|
400 |
|
|
wire wbm_sm_we_out ;
|
401 |
|
|
wire [3:0] wbm_sm_sel_out ;
|
402 |
|
|
wire [31:0] wbm_sm_adr_out ;
|
403 |
|
|
wire [31:0] wbm_sm_mdata_out ;
|
404 |
|
|
wire wbm_sm_cab_out ;
|
405 |
|
|
|
406 |
21 |
mihad |
assign pciu_err_addr_out = wbm_sm_adr_out ;
|
407 |
|
|
assign pciu_err_bc_out = wbm_sm_pci_error_bc ;
|
408 |
|
|
assign pciu_err_data_out = wbm_sm_mdata_out ;
|
409 |
|
|
assign pciu_err_be_out = ~wbm_sm_sel_out ;
|
410 |
|
|
assign pciu_err_signal_out = wbm_sm_pci_error_sig_out ;
|
411 |
|
|
assign pciu_err_source_out = wbm_sm_error_source_out ;
|
412 |
|
|
assign pciu_err_rty_exp_out = wbm_sm_write_rty_cnt_exp_out ;
|
413 |
2 |
mihad |
|
414 |
21 |
mihad |
assign ADR_O = wbm_sm_adr_out ;
|
415 |
|
|
assign MDATA_O = wbm_sm_mdata_out ;
|
416 |
|
|
assign CYC_O = wbm_sm_cyc_out ;
|
417 |
|
|
assign STB_O = wbm_sm_stb_out ;
|
418 |
|
|
assign WE_O = wbm_sm_we_out ;
|
419 |
|
|
assign SEL_O = wbm_sm_sel_out ;
|
420 |
|
|
assign CAB_O = wbm_sm_cab_out ;
|
421 |
2 |
mihad |
|
422 |
|
|
// pciw_pcir fifo outputs
|
423 |
|
|
|
424 |
|
|
// pciw_fifo_outputs:
|
425 |
|
|
wire [31:0] fifos_pciw_addr_data_out ;
|
426 |
|
|
wire [3:0] fifos_pciw_cbe_out ;
|
427 |
|
|
wire [3:0] fifos_pciw_control_out ;
|
428 |
108 |
tadejm |
wire fifos_pciw_three_left_out ;
|
429 |
21 |
mihad |
wire fifos_pciw_two_left_out ;
|
430 |
2 |
mihad |
wire fifos_pciw_almost_full_out ;
|
431 |
|
|
wire fifos_pciw_full_out ;
|
432 |
21 |
mihad |
wire fifos_pciw_almost_empty_out ;
|
433 |
2 |
mihad |
wire fifos_pciw_empty_out ;
|
434 |
|
|
wire fifos_pciw_transaction_ready_out ;
|
435 |
|
|
|
436 |
26 |
mihad |
assign pciu_pciw_fifo_empty_out = !wbm_sm_write_attempt;
|
437 |
2 |
mihad |
|
438 |
|
|
// pcir_fifo_outputs
|
439 |
|
|
wire [31:0] fifos_pcir_data_out ;
|
440 |
|
|
wire [3:0] fifos_pcir_be_out ;
|
441 |
|
|
wire [3:0] fifos_pcir_control_out ;
|
442 |
|
|
wire fifos_pcir_almost_empty_out ;
|
443 |
21 |
mihad |
wire fifos_pcir_empty_out ;
|
444 |
2 |
mihad |
|
445 |
|
|
// delayed transaction logic outputs
|
446 |
|
|
wire [31:0] del_sync_addr_out ;
|
447 |
|
|
wire [3:0] del_sync_be_out ;
|
448 |
|
|
wire del_sync_we_out ;
|
449 |
|
|
wire del_sync_comp_req_pending_out ;
|
450 |
|
|
wire del_sync_comp_comp_pending_out ;
|
451 |
|
|
wire del_sync_req_req_pending_out ;
|
452 |
|
|
wire del_sync_req_comp_pending_out ;
|
453 |
|
|
wire [3:0] del_sync_bc_out ;
|
454 |
|
|
wire del_sync_status_out ;
|
455 |
|
|
wire del_sync_comp_flush_out ;
|
456 |
|
|
wire del_sync_burst_out ;
|
457 |
|
|
|
458 |
21 |
mihad |
assign pciu_pci_drcomp_pending_out = del_sync_comp_comp_pending_out ;
|
459 |
2 |
mihad |
|
460 |
21 |
mihad |
// WISHBONE master interface inputs
|
461 |
|
|
wire wbm_sm_pci_tar_read_request = del_sync_comp_req_pending_out ;
|
462 |
|
|
wire [31:0] wbm_sm_pci_tar_address = del_sync_addr_out ;
|
463 |
|
|
wire [3:0] wbm_sm_pci_tar_cmd = del_sync_bc_out ;
|
464 |
|
|
wire [3:0] wbm_sm_pci_tar_be = del_sync_be_out ;
|
465 |
|
|
wire wbm_sm_pci_tar_burst_ok = del_sync_burst_out ;
|
466 |
|
|
wire [7:0] wbm_sm_pci_cache_line_size = pciu_cache_line_size_in ;
|
467 |
|
|
wire wbm_sm_cache_lsize_not_zero_in = pciu_cache_lsize_not_zero_in ;
|
468 |
|
|
wire [31:0] wbm_sm_pciw_fifo_addr_data_in = fifos_pciw_addr_data_out ;
|
469 |
|
|
wire [3:0] wbm_sm_pciw_fifo_cbe_in = fifos_pciw_cbe_out ;
|
470 |
|
|
wire [3:0] wbm_sm_pciw_fifo_control_in = fifos_pciw_control_out ;
|
471 |
|
|
wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ;
|
472 |
|
|
wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ;
|
473 |
|
|
wire wbm_sm_pciw_fifo_transaction_ready_in = fifos_pciw_transaction_ready_out ;
|
474 |
|
|
wire [31:0] wbm_sm_mdata_in = MDATA_I ;
|
475 |
|
|
wire wbm_sm_ack_in = ACK_I ;
|
476 |
|
|
wire wbm_sm_rty_in = RTY_I ;
|
477 |
|
|
wire wbm_sm_err_in = ERR_I ;
|
478 |
2 |
mihad |
|
479 |
|
|
// WISHBONE master interface instantiation
|
480 |
77 |
mihad |
pci_wb_master wishbone_master
|
481 |
2 |
mihad |
(
|
482 |
21 |
mihad |
.wb_clock_in (wb_clock_in),
|
483 |
|
|
.reset_in (reset_in),
|
484 |
|
|
.pci_tar_read_request (wbm_sm_pci_tar_read_request), //in
|
485 |
|
|
.pci_tar_address (wbm_sm_pci_tar_address), //in
|
486 |
|
|
.pci_tar_cmd (wbm_sm_pci_tar_cmd), //in
|
487 |
|
|
.pci_tar_be (wbm_sm_pci_tar_be), //in
|
488 |
|
|
.pci_tar_burst_ok (wbm_sm_pci_tar_burst_ok), //in
|
489 |
|
|
.pci_cache_line_size (wbm_sm_pci_cache_line_size), //in
|
490 |
|
|
.cache_lsize_not_zero (wbm_sm_cache_lsize_not_zero_in),
|
491 |
|
|
.wb_read_done_out (wbm_sm_wb_read_done), //out
|
492 |
26 |
mihad |
.w_attempt (wbm_sm_write_attempt), //out
|
493 |
21 |
mihad |
.pcir_fifo_wenable_out (wbm_sm_pcir_fifo_wenable_out),
|
494 |
|
|
.pcir_fifo_data_out (wbm_sm_pcir_fifo_data_out),
|
495 |
|
|
.pcir_fifo_be_out (wbm_sm_pcir_fifo_be_out),
|
496 |
|
|
.pcir_fifo_control_out (wbm_sm_pcir_fifo_control_out),
|
497 |
|
|
.pciw_fifo_renable_out (wbm_sm_pciw_fifo_renable_out),
|
498 |
|
|
.pciw_fifo_addr_data_in (wbm_sm_pciw_fifo_addr_data_in),
|
499 |
|
|
.pciw_fifo_cbe_in (wbm_sm_pciw_fifo_cbe_in),
|
500 |
|
|
.pciw_fifo_control_in (wbm_sm_pciw_fifo_control_in),
|
501 |
|
|
.pciw_fifo_almost_empty_in (wbm_sm_pciw_fifo_almost_empty_in),
|
502 |
|
|
.pciw_fifo_empty_in (wbm_sm_pciw_fifo_empty_in),
|
503 |
|
|
.pciw_fifo_transaction_ready_in (wbm_sm_pciw_fifo_transaction_ready_in),
|
504 |
|
|
.pci_error_sig_out (wbm_sm_pci_error_sig_out),
|
505 |
|
|
.pci_error_bc (wbm_sm_pci_error_bc),
|
506 |
|
|
.write_rty_cnt_exp_out (wbm_sm_write_rty_cnt_exp_out),
|
507 |
|
|
.error_source_out (wbm_sm_error_source_out),
|
508 |
|
|
.read_rty_cnt_exp_out (wbm_sm_read_rty_cnt_exp_out),
|
509 |
|
|
.CYC_O (wbm_sm_cyc_out),
|
510 |
|
|
.STB_O (wbm_sm_stb_out),
|
511 |
|
|
.WE_O (wbm_sm_we_out),
|
512 |
|
|
.SEL_O (wbm_sm_sel_out),
|
513 |
|
|
.ADR_O (wbm_sm_adr_out),
|
514 |
|
|
.MDATA_I (wbm_sm_mdata_in),
|
515 |
|
|
.MDATA_O (wbm_sm_mdata_out),
|
516 |
|
|
.ACK_I (wbm_sm_ack_in),
|
517 |
|
|
.RTY_I (wbm_sm_rty_in),
|
518 |
|
|
.ERR_I (wbm_sm_err_in),
|
519 |
|
|
.CAB_O (wbm_sm_cab_out)
|
520 |
2 |
mihad |
);
|
521 |
|
|
|
522 |
|
|
// pciw_pcir_fifos inputs
|
523 |
|
|
// PCIW_FIFO inputs
|
524 |
21 |
mihad |
wire fifos_pciw_wenable_in = pcit_if_pciw_fifo_wenable_out ;
|
525 |
|
|
wire [31:0] fifos_pciw_addr_data_in = pcit_if_pciw_fifo_addr_data_out ;
|
526 |
|
|
wire [3:0] fifos_pciw_cbe_in = pcit_if_pciw_fifo_cbe_out ;
|
527 |
|
|
wire [3:0] fifos_pciw_control_in = pcit_if_pciw_fifo_control_out ;
|
528 |
|
|
wire fifos_pciw_renable_in = wbm_sm_pciw_fifo_renable_out ;
|
529 |
58 |
mihad |
//wire fifos_pciw_flush_in = 1'b0 ; // flush not used for write fifo
|
530 |
2 |
mihad |
|
531 |
|
|
// PCIR_FIFO inputs
|
532 |
21 |
mihad |
wire fifos_pcir_wenable_in = wbm_sm_pcir_fifo_wenable_out ;
|
533 |
|
|
wire [31:0] fifos_pcir_data_in = wbm_sm_pcir_fifo_data_out ;
|
534 |
|
|
wire [3:0] fifos_pcir_be_in = wbm_sm_pcir_fifo_be_out ;
|
535 |
|
|
wire [3:0] fifos_pcir_control_in = wbm_sm_pcir_fifo_control_out ;
|
536 |
|
|
wire fifos_pcir_renable_in = pcit_if_pcir_fifo_renable_out ;
|
537 |
|
|
wire fifos_pcir_flush_in = pcit_if_pcir_fifo_flush_out ;
|
538 |
2 |
mihad |
|
539 |
|
|
// PCIW_FIFO and PCIR_FIFO instantiation
|
540 |
77 |
mihad |
pci_pciw_pcir_fifos fifos
|
541 |
2 |
mihad |
(
|
542 |
21 |
mihad |
.wb_clock_in (wb_clock_in),
|
543 |
|
|
.pci_clock_in (pci_clock_in),
|
544 |
|
|
.reset_in (reset_in),
|
545 |
|
|
.pciw_wenable_in (fifos_pciw_wenable_in), //for PCI Target !!!
|
546 |
|
|
.pciw_addr_data_in (fifos_pciw_addr_data_in), //for PCI Target !!!
|
547 |
|
|
.pciw_cbe_in (fifos_pciw_cbe_in), //for PCI Target !!!
|
548 |
|
|
.pciw_control_in (fifos_pciw_control_in), //for PCI Target !!!
|
549 |
|
|
.pciw_renable_in (fifos_pciw_renable_in),
|
550 |
|
|
.pciw_addr_data_out (fifos_pciw_addr_data_out),
|
551 |
|
|
.pciw_cbe_out (fifos_pciw_cbe_out),
|
552 |
|
|
.pciw_control_out (fifos_pciw_control_out),
|
553 |
58 |
mihad |
// .pciw_flush_in (fifos_pciw_flush_in), // flush not used for write fifo
|
554 |
108 |
tadejm |
.pciw_three_left_out (fifos_pciw_three_left_out), //for PCI Target !!!
|
555 |
21 |
mihad |
.pciw_two_left_out (fifos_pciw_two_left_out), //for PCI Target !!!
|
556 |
|
|
.pciw_almost_full_out (fifos_pciw_almost_full_out), //for PCI Target !!!
|
557 |
|
|
.pciw_full_out (fifos_pciw_full_out), //for PCI Target !!!
|
558 |
|
|
.pciw_almost_empty_out (fifos_pciw_almost_empty_out),
|
559 |
|
|
.pciw_empty_out (fifos_pciw_empty_out),
|
560 |
|
|
.pciw_transaction_ready_out (fifos_pciw_transaction_ready_out),
|
561 |
|
|
.pcir_wenable_in (fifos_pcir_wenable_in),
|
562 |
|
|
.pcir_data_in (fifos_pcir_data_in),
|
563 |
|
|
.pcir_be_in (fifos_pcir_be_in),
|
564 |
|
|
.pcir_control_in (fifos_pcir_control_in),
|
565 |
|
|
.pcir_renable_in (fifos_pcir_renable_in), //for PCI Target !!!
|
566 |
|
|
.pcir_data_out (fifos_pcir_data_out), //for PCI Target !!!
|
567 |
|
|
.pcir_be_out (fifos_pcir_be_out), //for PCI Target !!!
|
568 |
|
|
.pcir_control_out (fifos_pcir_control_out), //for PCI Target !!!
|
569 |
|
|
.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
|
570 |
26 |
mihad |
.pcir_full_out (),
|
571 |
21 |
mihad |
.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
|
572 |
|
|
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
|
573 |
|
|
.pcir_transaction_ready_out ()
|
574 |
62 |
mihad |
|
575 |
|
|
`ifdef PCI_BIST
|
576 |
|
|
,
|
577 |
67 |
tadejm |
.scanb_rst (scanb_rst),
|
578 |
|
|
.scanb_clk (scanb_clk),
|
579 |
|
|
.scanb_si (scanb_si),
|
580 |
|
|
.scanb_so (scanb_so),
|
581 |
68 |
tadejm |
.scanb_en (scanb_en)
|
582 |
62 |
mihad |
`endif
|
583 |
2 |
mihad |
) ;
|
584 |
|
|
|
585 |
|
|
// delayed transaction logic inputs
|
586 |
21 |
mihad |
wire del_sync_req_in = pcit_if_req_out ;
|
587 |
|
|
wire del_sync_comp_in = wbm_sm_wb_read_done ;
|
588 |
|
|
wire del_sync_done_in = pcit_if_done_out ;
|
589 |
|
|
wire del_sync_in_progress_in = pcit_if_in_progress_out ;
|
590 |
|
|
wire [31:0] del_sync_addr_in = pcit_if_addr_out ;
|
591 |
|
|
wire [3:0] del_sync_be_in = pcit_if_be_out ;
|
592 |
|
|
wire del_sync_we_in = pcit_if_we_out ;
|
593 |
|
|
wire [3:0] del_sync_bc_in = pcit_if_bc_out ;
|
594 |
|
|
wire del_sync_status_in = 1'b0 ;
|
595 |
|
|
wire del_sync_burst_in = pcit_if_burst_ok_out ;
|
596 |
|
|
wire del_sync_retry_expired_in = wbm_sm_read_rty_cnt_exp_out ;
|
597 |
2 |
mihad |
|
598 |
|
|
// delayed transaction logic instantiation
|
599 |
77 |
mihad |
pci_delayed_sync del_sync
|
600 |
2 |
mihad |
(
|
601 |
21 |
mihad |
.reset_in (reset_in),
|
602 |
|
|
.req_clk_in (pci_clock_in),
|
603 |
|
|
.comp_clk_in (wb_clock_in),
|
604 |
|
|
.req_in (del_sync_req_in),
|
605 |
|
|
.comp_in (del_sync_comp_in),
|
606 |
|
|
.done_in (del_sync_done_in),
|
607 |
|
|
.in_progress_in (del_sync_in_progress_in),
|
608 |
|
|
.comp_req_pending_out (del_sync_comp_req_pending_out),
|
609 |
|
|
.comp_comp_pending_out (del_sync_comp_comp_pending_out),
|
610 |
|
|
.req_req_pending_out (del_sync_req_req_pending_out),
|
611 |
|
|
.req_comp_pending_out (del_sync_req_comp_pending_out),
|
612 |
|
|
.addr_in (del_sync_addr_in),
|
613 |
|
|
.be_in (del_sync_be_in),
|
614 |
|
|
.addr_out (del_sync_addr_out),
|
615 |
|
|
.be_out (del_sync_be_out),
|
616 |
|
|
.we_in (del_sync_we_in),
|
617 |
|
|
.we_out (del_sync_we_out),
|
618 |
|
|
.bc_in (del_sync_bc_in),
|
619 |
|
|
.bc_out (del_sync_bc_out),
|
620 |
|
|
.status_in (del_sync_status_in),
|
621 |
|
|
.status_out (del_sync_status_out),
|
622 |
|
|
.comp_flush_out (del_sync_comp_flush_out),
|
623 |
|
|
.burst_in (del_sync_burst_in),
|
624 |
|
|
.burst_out (del_sync_burst_out),
|
625 |
|
|
.retry_expired_in (del_sync_retry_expired_in)
|
626 |
2 |
mihad |
);
|
627 |
|
|
|
628 |
|
|
// pci target interface inputs
|
629 |
21 |
mihad |
wire [31:0] pcit_if_address_in = pcit_sm_address_out ;
|
630 |
|
|
wire [3:0] pcit_if_bc_in = pcit_sm_bc_out ;
|
631 |
|
|
wire pcit_if_bc0_in = pcit_sm_bc0_out ;
|
632 |
|
|
wire [31:0] pcit_if_data_in = pcit_sm_data_out ;
|
633 |
|
|
wire [3:0] pcit_if_be_in = pcit_sm_be_out ;
|
634 |
108 |
tadejm |
wire [3:0] pcit_if_next_be_in = pcit_sm_next_be_out ;
|
635 |
21 |
mihad |
wire pcit_if_req_in = pcit_sm_req_out ;
|
636 |
|
|
wire pcit_if_rdy_in = pcit_sm_rdy_out ;
|
637 |
|
|
wire pcit_if_addr_phase_in = pcit_sm_addr_phase_out ;
|
638 |
|
|
wire pcit_if_bckp_devsel_in = pcit_sm_bckp_devsel_out ;
|
639 |
|
|
wire pcit_if_bckp_trdy_in = pcit_sm_bckp_trdy_out ;
|
640 |
|
|
wire pcit_if_bckp_stop_in = pcit_sm_bckp_stop_out ;
|
641 |
|
|
wire pcit_if_last_reg_in = pcit_sm_last_reg_out ;
|
642 |
|
|
wire pcit_if_frame_reg_in = pcit_sm_frame_reg_out ;
|
643 |
|
|
wire pcit_if_fetch_pcir_fifo_in = pcit_sm_fetch_pcir_fifo_out ;
|
644 |
|
|
wire pcit_if_load_medium_reg_in = pcit_sm_load_medium_reg_out ;
|
645 |
|
|
wire pcit_if_sel_fifo_mreg_in = pcit_sm_sel_fifo_mreg_out ;
|
646 |
|
|
wire pcit_if_sel_conf_fifo_in = pcit_sm_sel_conf_fifo_out ;
|
647 |
|
|
wire pcit_if_fetch_conf_in = pcit_sm_fetch_conf_out ;
|
648 |
|
|
wire pcit_if_load_to_pciw_fifo_in = pcit_sm_load_to_pciw_fifo_out ;
|
649 |
|
|
wire pcit_if_load_to_conf_in = pcit_sm_load_to_conf_out ;
|
650 |
|
|
wire pcit_if_req_req_pending_in = del_sync_req_req_pending_out ;
|
651 |
|
|
wire pcit_if_req_comp_pending_in = del_sync_req_comp_pending_out ;
|
652 |
|
|
wire pcit_if_status_in = del_sync_status_out ;
|
653 |
|
|
wire [31:0] pcit_if_strd_addr_in = del_sync_addr_out ;
|
654 |
|
|
wire [3:0] pcit_if_strd_bc_in = del_sync_bc_out ;
|
655 |
|
|
wire pcit_if_comp_flush_in = del_sync_comp_flush_out ;
|
656 |
|
|
wire [31:0] pcit_if_pcir_fifo_data_in = fifos_pcir_data_out ;
|
657 |
|
|
wire [3:0] pcit_if_pcir_fifo_be_in = fifos_pcir_be_out ;
|
658 |
|
|
wire [3:0] pcit_if_pcir_fifo_control_in = fifos_pcir_control_out ;
|
659 |
|
|
wire pcit_if_pcir_fifo_almost_empty_in = fifos_pcir_almost_empty_out ;
|
660 |
|
|
wire pcit_if_pcir_fifo_empty_in = fifos_pcir_empty_out ;
|
661 |
108 |
tadejm |
wire pcit_if_pciw_fifo_three_left_in = fifos_pciw_three_left_out ;
|
662 |
21 |
mihad |
wire pcit_if_pciw_fifo_two_left_in = fifos_pciw_two_left_out ;
|
663 |
|
|
wire pcit_if_pciw_fifo_almost_full_in = fifos_pciw_almost_full_out ;
|
664 |
|
|
wire pcit_if_pciw_fifo_full_in = fifos_pciw_full_out ;
|
665 |
|
|
wire pcit_if_wbw_fifo_empty_in = pciu_wbw_fifo_empty_in ;
|
666 |
|
|
wire pcit_if_wbu_del_read_comp_pending_in = pciu_wbu_del_read_comp_pending_in ;
|
667 |
|
|
wire [31:0] pcit_if_conf_data_in = pciu_conf_data_in ;
|
668 |
|
|
wire pcit_if_mem_enable_in = pciu_mem_enable_in ;
|
669 |
|
|
wire pcit_if_io_enable_in = pciu_io_enable_in ;
|
670 |
|
|
wire pcit_if_mem_io_addr_space0_in = pciu_map_in[0] ;
|
671 |
|
|
wire pcit_if_mem_io_addr_space1_in = pciu_map_in[1] ;
|
672 |
|
|
wire pcit_if_mem_io_addr_space2_in = pciu_map_in[2] ;
|
673 |
|
|
wire pcit_if_mem_io_addr_space3_in = pciu_map_in[3] ;
|
674 |
|
|
wire pcit_if_mem_io_addr_space4_in = pciu_map_in[4] ;
|
675 |
|
|
wire pcit_if_mem_io_addr_space5_in = pciu_map_in[5] ;
|
676 |
|
|
wire pcit_if_pre_fetch_en0_in = pciu_pref_en_in[0] ;
|
677 |
|
|
wire pcit_if_pre_fetch_en1_in = pciu_pref_en_in[1] ;
|
678 |
|
|
wire pcit_if_pre_fetch_en2_in = pciu_pref_en_in[2] ;
|
679 |
|
|
wire pcit_if_pre_fetch_en3_in = pciu_pref_en_in[3] ;
|
680 |
|
|
wire pcit_if_pre_fetch_en4_in = pciu_pref_en_in[4] ;
|
681 |
|
|
wire pcit_if_pre_fetch_en5_in = pciu_pref_en_in[5] ;
|
682 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_base_addr0_in = pciu_bar0_in ;
|
683 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_base_addr1_in = pciu_bar1_in ;
|
684 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_base_addr2_in = pciu_bar2_in ;
|
685 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_base_addr3_in = pciu_bar3_in ;
|
686 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_base_addr4_in = pciu_bar4_in ;
|
687 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_base_addr5_in = pciu_bar5_in ;
|
688 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_addr_mask0_in = pciu_am0_in ;
|
689 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_addr_mask1_in = pciu_am1_in ;
|
690 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_addr_mask2_in = pciu_am2_in ;
|
691 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_addr_mask3_in = pciu_am3_in ;
|
692 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_addr_mask4_in = pciu_am4_in ;
|
693 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_addr_mask5_in = pciu_am5_in ;
|
694 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_tran_addr0_in = pciu_ta0_in ;
|
695 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_tran_addr1_in = pciu_ta1_in ;
|
696 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_tran_addr2_in = pciu_ta2_in ;
|
697 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_tran_addr3_in = pciu_ta3_in ;
|
698 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_tran_addr4_in = pciu_ta4_in ;
|
699 |
|
|
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pcit_if_pci_tran_addr5_in = pciu_ta5_in ;
|
700 |
|
|
wire pcit_if_addr_tran_en0_in = pciu_at_en_in[0] ;
|
701 |
|
|
wire pcit_if_addr_tran_en1_in = pciu_at_en_in[1] ;
|
702 |
|
|
wire pcit_if_addr_tran_en2_in = pciu_at_en_in[2] ;
|
703 |
|
|
wire pcit_if_addr_tran_en3_in = pciu_at_en_in[3] ;
|
704 |
|
|
wire pcit_if_addr_tran_en4_in = pciu_at_en_in[4] ;
|
705 |
|
|
wire pcit_if_addr_tran_en5_in = pciu_at_en_in[5] ;
|
706 |
2 |
mihad |
|
707 |
77 |
mihad |
pci_target32_interface pci_target_if
|
708 |
2 |
mihad |
(
|
709 |
21 |
mihad |
.clk_in (pci_clock_in),
|
710 |
|
|
.reset_in (reset_in),
|
711 |
|
|
.address_in (pcit_if_address_in),
|
712 |
|
|
.addr_claim_out (pcit_if_addr_claim_out),
|
713 |
|
|
.bc_in (pcit_if_bc_in),
|
714 |
|
|
.bc0_in (pcit_if_bc0_in),
|
715 |
|
|
.data_in (pcit_if_data_in),
|
716 |
|
|
.data_out (pcit_if_data_out),
|
717 |
|
|
.be_in (pcit_if_be_in),
|
718 |
108 |
tadejm |
.next_be_in (pcit_if_next_be_in),
|
719 |
21 |
mihad |
.req_in (pcit_if_req_in),
|
720 |
|
|
.rdy_in (pcit_if_rdy_in),
|
721 |
|
|
.addr_phase_in (pcit_if_addr_phase_in),
|
722 |
|
|
.bckp_devsel_in (pcit_if_bckp_devsel_in),
|
723 |
|
|
.bckp_trdy_in (pcit_if_bckp_trdy_in),
|
724 |
|
|
.bckp_stop_in (pcit_if_bckp_stop_in),
|
725 |
|
|
.last_reg_in (pcit_if_last_reg_in),
|
726 |
|
|
.frame_reg_in (pcit_if_frame_reg_in),
|
727 |
|
|
.fetch_pcir_fifo_in (pcit_if_fetch_pcir_fifo_in),
|
728 |
|
|
.load_medium_reg_in (pcit_if_load_medium_reg_in),
|
729 |
|
|
.sel_fifo_mreg_in (pcit_if_sel_fifo_mreg_in),
|
730 |
|
|
.sel_conf_fifo_in (pcit_if_sel_conf_fifo_in),
|
731 |
|
|
.fetch_conf_in (pcit_if_fetch_conf_in),
|
732 |
|
|
.load_to_pciw_fifo_in (pcit_if_load_to_pciw_fifo_in),
|
733 |
|
|
.load_to_conf_in (pcit_if_load_to_conf_in),
|
734 |
|
|
.same_read_out (pcit_if_same_read_out),
|
735 |
|
|
.norm_access_to_config_out (pcit_if_norm_access_to_config_out),
|
736 |
|
|
.read_completed_out (pcit_if_read_completed_out),
|
737 |
|
|
.read_processing_out (pcit_if_read_processing_out),
|
738 |
|
|
.target_abort_out (pcit_if_target_abort_out),
|
739 |
|
|
.disconect_wo_data_out (pcit_if_disconect_wo_data_out),
|
740 |
|
|
.disconect_w_data_out (pcit_if_disconect_w_data_out),
|
741 |
|
|
.pciw_fifo_full_out (pcit_if_pciw_fifo_full_out),
|
742 |
|
|
.pcir_fifo_data_err_out (pcit_if_pcir_fifo_data_err_out),
|
743 |
|
|
.wbw_fifo_empty_out (pcit_if_wbw_fifo_empty_out),
|
744 |
|
|
.wbu_del_read_comp_pending_out (pcit_if_wbu_del_read_comp_pending_out),
|
745 |
|
|
.req_out (pcit_if_req_out),
|
746 |
|
|
.done_out (pcit_if_done_out),
|
747 |
|
|
.in_progress_out (pcit_if_in_progress_out),
|
748 |
|
|
.req_req_pending_in (pcit_if_req_req_pending_in),
|
749 |
|
|
.req_comp_pending_in (pcit_if_req_comp_pending_in),
|
750 |
|
|
.addr_out (pcit_if_addr_out),
|
751 |
|
|
.be_out (pcit_if_be_out),
|
752 |
|
|
.we_out (pcit_if_we_out),
|
753 |
|
|
.bc_out (pcit_if_bc_out),
|
754 |
|
|
.burst_ok_out (pcit_if_burst_ok_out),
|
755 |
|
|
.strd_addr_in (pcit_if_strd_addr_in),
|
756 |
|
|
.strd_bc_in (pcit_if_strd_bc_in),
|
757 |
|
|
.status_in (pcit_if_status_in),
|
758 |
|
|
.comp_flush_in (pcit_if_comp_flush_in),
|
759 |
|
|
.pcir_fifo_renable_out (pcit_if_pcir_fifo_renable_out),
|
760 |
|
|
.pcir_fifo_data_in (pcit_if_pcir_fifo_data_in),
|
761 |
|
|
.pcir_fifo_be_in (pcit_if_pcir_fifo_be_in),
|
762 |
|
|
.pcir_fifo_control_in (pcit_if_pcir_fifo_control_in),
|
763 |
|
|
.pcir_fifo_flush_out (pcit_if_pcir_fifo_flush_out),
|
764 |
|
|
.pcir_fifo_almost_empty_in (pcit_if_pcir_fifo_almost_empty_in),
|
765 |
|
|
.pcir_fifo_empty_in (pcit_if_pcir_fifo_empty_in),
|
766 |
|
|
.pciw_fifo_wenable_out (pcit_if_pciw_fifo_wenable_out),
|
767 |
|
|
.pciw_fifo_addr_data_out (pcit_if_pciw_fifo_addr_data_out),
|
768 |
|
|
.pciw_fifo_cbe_out (pcit_if_pciw_fifo_cbe_out),
|
769 |
|
|
.pciw_fifo_control_out (pcit_if_pciw_fifo_control_out),
|
770 |
108 |
tadejm |
.pciw_fifo_three_left_in (pcit_if_pciw_fifo_three_left_in),
|
771 |
21 |
mihad |
.pciw_fifo_two_left_in (pcit_if_pciw_fifo_two_left_in),
|
772 |
|
|
.pciw_fifo_almost_full_in (pcit_if_pciw_fifo_almost_full_in),
|
773 |
|
|
.pciw_fifo_full_in (pcit_if_pciw_fifo_full_in),
|
774 |
|
|
.wbw_fifo_empty_in (pcit_if_wbw_fifo_empty_in),
|
775 |
|
|
.wbu_del_read_comp_pending_in (pcit_if_wbu_del_read_comp_pending_in),
|
776 |
|
|
.conf_hit_out (pcit_if_conf_hit_out),
|
777 |
|
|
.conf_addr_out (pcit_if_conf_addr_out),
|
778 |
|
|
.conf_data_out (pcit_if_conf_data_out),
|
779 |
|
|
.conf_data_in (pcit_if_conf_data_in),
|
780 |
|
|
.conf_be_out (pcit_if_conf_be_out),
|
781 |
|
|
.conf_we_out (pcit_if_conf_we_out),
|
782 |
|
|
.conf_re_out (pcit_if_conf_re_out),
|
783 |
|
|
.mem_enable_in (pcit_if_mem_enable_in),
|
784 |
|
|
.io_enable_in (pcit_if_io_enable_in),
|
785 |
|
|
.mem_io_addr_space0_in (pcit_if_mem_io_addr_space0_in),
|
786 |
|
|
.mem_io_addr_space1_in (pcit_if_mem_io_addr_space1_in),
|
787 |
|
|
.mem_io_addr_space2_in (pcit_if_mem_io_addr_space2_in),
|
788 |
|
|
.mem_io_addr_space3_in (pcit_if_mem_io_addr_space3_in),
|
789 |
|
|
.mem_io_addr_space4_in (pcit_if_mem_io_addr_space4_in),
|
790 |
|
|
.mem_io_addr_space5_in (pcit_if_mem_io_addr_space5_in),
|
791 |
|
|
.pre_fetch_en0_in (pcit_if_pre_fetch_en0_in),
|
792 |
|
|
.pre_fetch_en1_in (pcit_if_pre_fetch_en1_in),
|
793 |
|
|
.pre_fetch_en2_in (pcit_if_pre_fetch_en2_in),
|
794 |
|
|
.pre_fetch_en3_in (pcit_if_pre_fetch_en3_in),
|
795 |
|
|
.pre_fetch_en4_in (pcit_if_pre_fetch_en4_in),
|
796 |
|
|
.pre_fetch_en5_in (pcit_if_pre_fetch_en5_in),
|
797 |
|
|
.pci_base_addr0_in (pcit_if_pci_base_addr0_in),
|
798 |
|
|
.pci_base_addr1_in (pcit_if_pci_base_addr1_in),
|
799 |
|
|
.pci_base_addr2_in (pcit_if_pci_base_addr2_in),
|
800 |
|
|
.pci_base_addr3_in (pcit_if_pci_base_addr3_in),
|
801 |
|
|
.pci_base_addr4_in (pcit_if_pci_base_addr4_in),
|
802 |
|
|
.pci_base_addr5_in (pcit_if_pci_base_addr5_in),
|
803 |
|
|
.pci_addr_mask0_in (pcit_if_pci_addr_mask0_in),
|
804 |
|
|
.pci_addr_mask1_in (pcit_if_pci_addr_mask1_in),
|
805 |
|
|
.pci_addr_mask2_in (pcit_if_pci_addr_mask2_in),
|
806 |
|
|
.pci_addr_mask3_in (pcit_if_pci_addr_mask3_in),
|
807 |
|
|
.pci_addr_mask4_in (pcit_if_pci_addr_mask4_in),
|
808 |
|
|
.pci_addr_mask5_in (pcit_if_pci_addr_mask5_in),
|
809 |
|
|
.pci_tran_addr0_in (pcit_if_pci_tran_addr0_in),
|
810 |
|
|
.pci_tran_addr1_in (pcit_if_pci_tran_addr1_in),
|
811 |
|
|
.pci_tran_addr2_in (pcit_if_pci_tran_addr2_in),
|
812 |
|
|
.pci_tran_addr3_in (pcit_if_pci_tran_addr3_in),
|
813 |
|
|
.pci_tran_addr4_in (pcit_if_pci_tran_addr4_in),
|
814 |
|
|
.pci_tran_addr5_in (pcit_if_pci_tran_addr5_in),
|
815 |
|
|
.addr_tran_en0_in (pcit_if_addr_tran_en0_in),
|
816 |
|
|
.addr_tran_en1_in (pcit_if_addr_tran_en1_in),
|
817 |
|
|
.addr_tran_en2_in (pcit_if_addr_tran_en2_in),
|
818 |
|
|
.addr_tran_en3_in (pcit_if_addr_tran_en3_in),
|
819 |
|
|
.addr_tran_en4_in (pcit_if_addr_tran_en4_in),
|
820 |
|
|
.addr_tran_en5_in (pcit_if_addr_tran_en5_in)
|
821 |
2 |
mihad |
) ;
|
822 |
|
|
|
823 |
|
|
// pci target state machine inputs
|
824 |
21 |
mihad |
wire pcit_sm_frame_in = pciu_pciif_frame_in ;
|
825 |
|
|
wire pcit_sm_irdy_in = pciu_pciif_irdy_in ;
|
826 |
|
|
wire pcit_sm_idsel_in = pciu_pciif_idsel_in ;
|
827 |
|
|
wire pcit_sm_frame_reg_in = pciu_pciif_frame_reg_in ;
|
828 |
|
|
wire pcit_sm_irdy_reg_in = pciu_pciif_irdy_reg_in ;
|
829 |
|
|
wire pcit_sm_idsel_reg_in = pciu_pciif_idsel_reg_in ;
|
830 |
|
|
wire [31:0] pcit_sm_ad_reg_in = pciu_pciif_ad_reg_in ;
|
831 |
|
|
wire [3:0] pcit_sm_cbe_reg_in = pciu_pciif_cbe_reg_in ;
|
832 |
108 |
tadejm |
wire [3:0] pcit_sm_cbe_in = pciu_pciif_cbe_in ;
|
833 |
21 |
mihad |
wire pcit_sm_bckp_trdy_en_in = pciu_pciif_bckp_trdy_en_in ;
|
834 |
|
|
wire pcit_sm_bckp_devsel_in = pciu_pciif_bckp_devsel_in ;
|
835 |
|
|
wire pcit_sm_bckp_trdy_in = pciu_pciif_bckp_trdy_in ;
|
836 |
|
|
wire pcit_sm_bckp_stop_in = pciu_pciif_bckp_stop_in ;
|
837 |
|
|
wire pcit_sm_addr_claim_in = pcit_if_addr_claim_out ;
|
838 |
|
|
wire [31:0] pcit_sm_data_in = pcit_if_data_out ;
|
839 |
|
|
wire pcit_sm_same_read_in = pcit_if_same_read_out ;
|
840 |
|
|
wire pcit_sm_norm_access_to_config_in = pcit_if_norm_access_to_config_out ;
|
841 |
|
|
wire pcit_sm_read_completed_in = pcit_if_read_completed_out ;
|
842 |
|
|
wire pcit_sm_read_processing_in = pcit_if_read_processing_out ;
|
843 |
|
|
wire pcit_sm_target_abort_in = pcit_if_target_abort_out ;
|
844 |
|
|
wire pcit_sm_disconect_wo_data_in = pcit_if_disconect_wo_data_out ;
|
845 |
|
|
wire pcit_sm_disconect_w_data_in = pcit_if_disconect_w_data_out ;
|
846 |
|
|
wire pcit_sm_pciw_fifo_full_in = pcit_if_pciw_fifo_full_out ;
|
847 |
|
|
wire pcit_sm_pcir_fifo_data_err_in = pcit_if_pcir_fifo_data_err_out ;
|
848 |
|
|
wire pcit_sm_wbw_fifo_empty_in = pcit_if_wbw_fifo_empty_out ;
|
849 |
|
|
wire pcit_sm_wbu_del_read_comp_pending_in = pcit_if_wbu_del_read_comp_pending_out ;
|
850 |
|
|
wire pcit_sm_wbu_frame_en_in = pciu_wbu_frame_en_in ;
|
851 |
|
|
wire pcit_sm_trdy_reg_in = pciu_pciif_trdy_reg_in ;
|
852 |
|
|
wire pcit_sm_stop_reg_in = pciu_pciif_stop_reg_in ;
|
853 |
2 |
mihad |
|
854 |
21 |
mihad |
|
855 |
77 |
mihad |
pci_target32_sm pci_target_sm
|
856 |
2 |
mihad |
(
|
857 |
21 |
mihad |
.clk_in (pci_clock_in),
|
858 |
|
|
.reset_in (reset_in),
|
859 |
|
|
.pci_frame_in (pcit_sm_frame_in),
|
860 |
|
|
.pci_irdy_in (pcit_sm_irdy_in),
|
861 |
|
|
.pci_idsel_in (pcit_sm_idsel_in),
|
862 |
|
|
.pci_frame_reg_in (pcit_sm_frame_reg_in),
|
863 |
|
|
.pci_irdy_reg_in (pcit_sm_irdy_reg_in),
|
864 |
|
|
.pci_idsel_reg_in (pcit_sm_idsel_reg_in),
|
865 |
|
|
.pci_trdy_out (pcit_sm_trdy_out),
|
866 |
|
|
.pci_stop_out (pcit_sm_stop_out),
|
867 |
|
|
.pci_devsel_out (pcit_sm_devsel_out),
|
868 |
|
|
.pci_trdy_en_out (pcit_sm_trdy_en_out),
|
869 |
|
|
.pci_stop_en_out (pcit_sm_stop_en_out),
|
870 |
|
|
.pci_devsel_en_out (pcit_sm_devsel_en_out),
|
871 |
|
|
.ad_load_out (pcit_sm_ad_load_out),
|
872 |
|
|
.ad_load_on_transfer_out (pcit_sm_ad_load_on_transfer_out),
|
873 |
|
|
.pci_ad_reg_in (pcit_sm_ad_reg_in),
|
874 |
|
|
.pci_ad_out (pcit_sm_ad_out),
|
875 |
|
|
.pci_ad_en_out (pcit_sm_ad_en_out),
|
876 |
|
|
.pci_cbe_reg_in (pcit_sm_cbe_reg_in),
|
877 |
108 |
tadejm |
.pci_cbe_in (pcit_sm_cbe_in),
|
878 |
21 |
mihad |
.bckp_trdy_en_in (pcit_sm_bckp_trdy_en_in),
|
879 |
|
|
.bckp_devsel_in (pcit_sm_bckp_devsel_in),
|
880 |
|
|
.bckp_trdy_in (pcit_sm_bckp_trdy_in),
|
881 |
|
|
.bckp_stop_in (pcit_sm_bckp_stop_in),
|
882 |
|
|
.pci_trdy_reg_in (pcit_sm_trdy_reg_in),
|
883 |
|
|
.pci_stop_reg_in (pcit_sm_stop_reg_in),
|
884 |
|
|
.address_out (pcit_sm_address_out),
|
885 |
|
|
.addr_claim_in (pcit_sm_addr_claim_in),
|
886 |
|
|
.bc_out (pcit_sm_bc_out),
|
887 |
|
|
.bc0_out (pcit_sm_bc0_out),
|
888 |
|
|
.data_out (pcit_sm_data_out),
|
889 |
|
|
.data_in (pcit_sm_data_in),
|
890 |
|
|
.be_out (pcit_sm_be_out),
|
891 |
108 |
tadejm |
.next_be_out (pcit_sm_next_be_out),
|
892 |
21 |
mihad |
.req_out (pcit_sm_req_out),
|
893 |
|
|
.rdy_out (pcit_sm_rdy_out),
|
894 |
|
|
.addr_phase_out (pcit_sm_addr_phase_out),
|
895 |
|
|
.bckp_devsel_out (pcit_sm_bckp_devsel_out),
|
896 |
|
|
.bckp_trdy_out (pcit_sm_bckp_trdy_out),
|
897 |
|
|
.bckp_stop_out (pcit_sm_bckp_stop_out),
|
898 |
|
|
.last_reg_out (pcit_sm_last_reg_out),
|
899 |
|
|
.frame_reg_out (pcit_sm_frame_reg_out),
|
900 |
|
|
.fetch_pcir_fifo_out (pcit_sm_fetch_pcir_fifo_out),
|
901 |
|
|
.load_medium_reg_out (pcit_sm_load_medium_reg_out),
|
902 |
|
|
.sel_fifo_mreg_out (pcit_sm_sel_fifo_mreg_out),
|
903 |
|
|
.sel_conf_fifo_out (pcit_sm_sel_conf_fifo_out),
|
904 |
|
|
.fetch_conf_out (pcit_sm_fetch_conf_out),
|
905 |
|
|
.load_to_pciw_fifo_out (pcit_sm_load_to_pciw_fifo_out),
|
906 |
|
|
.load_to_conf_out (pcit_sm_load_to_conf_out),
|
907 |
|
|
.same_read_in (pcit_sm_same_read_in),
|
908 |
|
|
.norm_access_to_config_in (pcit_sm_norm_access_to_config_in),
|
909 |
|
|
.read_completed_in (pcit_sm_read_completed_in),
|
910 |
|
|
.read_processing_in (pcit_sm_read_processing_in),
|
911 |
|
|
.target_abort_in (pcit_sm_target_abort_in),
|
912 |
|
|
.disconect_wo_data_in (pcit_sm_disconect_wo_data_in),
|
913 |
|
|
.disconect_w_data_in (pcit_sm_disconect_w_data_in),
|
914 |
|
|
.target_abort_set_out (pcit_sm_target_abort_set_out),
|
915 |
|
|
.pciw_fifo_full_in (pcit_sm_pciw_fifo_full_in),
|
916 |
|
|
.pcir_fifo_data_err_in (pcit_sm_pcir_fifo_data_err_in),
|
917 |
|
|
.wbw_fifo_empty_in (pcit_sm_wbw_fifo_empty_in),
|
918 |
|
|
.wbu_del_read_comp_pending_in (pcit_sm_wbu_del_read_comp_pending_in),
|
919 |
|
|
.wbu_frame_en_in (pcit_sm_wbu_frame_en_in)
|
920 |
2 |
mihad |
) ;
|
921 |
|
|
|
922 |
33 |
mihad |
endmodule
|