1 |
19 |
mihad |
//===========================================================================
|
2 |
107 |
tadejm |
// $Id: pci_behaviorial_master.v,v 1.3 2003-08-08 16:29:00 tadejm Exp $
|
3 |
19 |
mihad |
//
|
4 |
|
|
// Copyright 2001 Blue Beaver. All Rights Reserved.
|
5 |
|
|
//
|
6 |
|
|
// Summary: A PCI Behaviorial Master. This module accepts commands from
|
7 |
|
|
// the top-level Stimulus generator. Based on arguments supplied
|
8 |
|
|
// to it, it generates a reference containing paramaters to the
|
9 |
|
|
// Target in the middle 16 bits of PCI Address. It also arbitrates
|
10 |
|
|
// for the bus, sends data when writing, and compares returned data
|
11 |
|
|
// when reading.
|
12 |
|
|
// This interface does not understand retries after Target Disconnect
|
13 |
|
|
// commands, and does not implement a disconnect counter.
|
14 |
|
|
//
|
15 |
|
|
// This library is free software; you can distribute it and/or modify it
|
16 |
|
|
// under the terms of the GNU Lesser General Public License as published
|
17 |
|
|
// by the Free Software Foundation; either version 2.1 of the License, or
|
18 |
|
|
// (at your option) any later version.
|
19 |
|
|
//
|
20 |
|
|
// This library is distributed in the hope that it will be useful, but
|
21 |
|
|
// WITHOUT ANY WARRANTY; without even the implied warranty of
|
22 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
23 |
|
|
// See the GNU Lesser General Public License for more details.
|
24 |
|
|
//
|
25 |
|
|
// You should have received a copy of the GNU Lesser General Public License
|
26 |
|
|
// along with this library. If not, write to
|
27 |
|
|
// Free Software Foundation, Inc.
|
28 |
|
|
// 59 Temple Place, Suite 330
|
29 |
|
|
// Boston, MA 02111-1307 USA
|
30 |
|
|
//
|
31 |
|
|
// Author's note about this license: The intention of the Author and of
|
32 |
|
|
// the Gnu Lesser General Public License is that users should be able to
|
33 |
|
|
// use this code for any purpose, including combining it with other source
|
34 |
|
|
// code, combining it with other logic, translated it into a gate-level
|
35 |
|
|
// representation, or projected it into gates in a programmable or
|
36 |
|
|
// hardwired chip, as long as the users of the resulting source, compiled
|
37 |
|
|
// source, or chip are given the means to get a copy of this source code
|
38 |
|
|
// with no new restrictions on redistribution of this source.
|
39 |
|
|
//
|
40 |
|
|
// If you make changes, even substantial changes, to this code, or use
|
41 |
|
|
// substantial parts of this code as an inseparable part of another work
|
42 |
|
|
// of authorship, the users of the resulting IP must be given the means
|
43 |
|
|
// to get a copy of the modified or combined source code, with no new
|
44 |
|
|
// restrictions on redistribution of the resulting source.
|
45 |
|
|
//
|
46 |
|
|
// Separate parts of the combined source code, compiled code, or chip,
|
47 |
|
|
// which are NOT derived from this source code do NOT need to be offered
|
48 |
|
|
// to the final user of the chip merely because they are used in
|
49 |
|
|
// combination with this code. Other code is not forced to fall under
|
50 |
|
|
// the GNU Lesser General Public License when it is linked to this code.
|
51 |
|
|
// The license terms of other source code linked to this code might require
|
52 |
|
|
// that it NOT be made available to users. The GNU Lesser General Public
|
53 |
|
|
// License does not prevent this code from being used in such a situation,
|
54 |
|
|
// as long as the user of the resulting IP is given the means to get a
|
55 |
|
|
// copy of this component of the IP with no new restrictions on
|
56 |
|
|
// redistribution of this source.
|
57 |
|
|
//
|
58 |
|
|
// This code was developed using VeriLogger Pro, by Synapticad.
|
59 |
|
|
// Their support is greatly appreciated.
|
60 |
|
|
//
|
61 |
|
|
// NOTE: This Test Chip instantiates one PCI interface and connects it
|
62 |
|
|
// to its IO pads and to logic representing a real application.
|
63 |
|
|
//
|
64 |
|
|
// NOTE TODO: Horrible. Tasks can't depend on their Arguments being safe
|
65 |
|
|
// if there are several instances ofthe tasl running at once.
|
66 |
|
|
// NOTE TODO: Verify that Fast-Back-To-Back references are done correctly
|
67 |
|
|
// NOTE TODO: Verify that PERR and SERR are driven correctly, and that signals
|
68 |
|
|
// reflecting their detection are available for use in the Config Regs
|
69 |
|
|
// Detect and report PERR and SERR reports as enabled. 3.7.4
|
70 |
|
|
// Start adding the address register needed to handle retries
|
71 |
|
|
// Start trying to understand the latency register. Why not simply
|
72 |
|
|
// get off the bus when grant goes away?
|
73 |
|
|
// Do not do a retry or disconnect if all 4 BE wires are 1's. End of 3.8
|
74 |
|
|
// Start adding Latency Counter
|
75 |
|
|
// Complain if SERR caused by address parity error not seen when expected
|
76 |
|
|
// complain if data parity error not seen when expected
|
77 |
|
|
//
|
78 |
|
|
//===========================================================================
|
79 |
|
|
|
80 |
35 |
mihad |
// synopsys translate_off
|
81 |
|
|
`include "timescale.v"
|
82 |
|
|
// synopsys translate_on
|
83 |
19 |
mihad |
|
84 |
|
|
module pci_behaviorial_master (
|
85 |
|
|
ad_now, ad_prev, master_ad_out, master_ad_oe,
|
86 |
|
|
master_cbe_l_out, master_cbe_oe,
|
87 |
|
|
calc_input_parity_prev,
|
88 |
|
|
par_now, par_prev,
|
89 |
|
|
frame_now, frame_prev, master_frame_out, master_frame_oe,
|
90 |
|
|
irdy_now, irdy_prev, master_irdy_out, master_irdy_oe,
|
91 |
|
|
devsel_now, devsel_prev, trdy_now, trdy_prev, stop_now, stop_prev,
|
92 |
|
|
perr_now, perr_prev, master_perr_out, master_perr_oe, master_serr_oe,
|
93 |
|
|
master_req_out, master_gnt_now,
|
94 |
|
|
pci_reset_comb, pci_ext_clk,
|
95 |
|
|
// Signals from the master to the target to set bits in the Status Register
|
96 |
|
|
master_got_parity_error, master_asserted_serr, master_got_master_abort,
|
97 |
|
|
master_got_target_abort, master_caused_parity_error,
|
98 |
|
|
master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable,
|
99 |
|
|
master_latency_value,
|
100 |
|
|
// Signals used by the test bench instead of using "." notation
|
101 |
|
|
master_debug_force_bad_par,
|
102 |
|
|
test_master_number, test_address, test_command,
|
103 |
|
|
test_data, test_byte_enables_l, test_size,
|
104 |
|
|
test_make_addr_par_error, test_make_data_par_error,
|
105 |
|
|
test_master_initial_wait_states, test_master_subsequent_wait_states,
|
106 |
|
|
test_target_initial_wait_states, test_target_subsequent_wait_states,
|
107 |
|
|
test_target_devsel_speed, test_fast_back_to_back,
|
108 |
|
|
test_target_termination,
|
109 |
|
|
test_expect_master_abort,
|
110 |
|
|
test_start, test_accepted_l, test_error_event,
|
111 |
|
|
test_device_id,
|
112 |
|
|
master_received_data,
|
113 |
|
|
master_received_data_valid,
|
114 |
|
|
master_check_received_data
|
115 |
|
|
);
|
116 |
|
|
|
117 |
|
|
`include "pci_blue_options.vh"
|
118 |
|
|
`include "pci_blue_constants.vh"
|
119 |
|
|
|
120 |
|
|
input [PCI_BUS_DATA_RANGE:0] ad_now;
|
121 |
|
|
input [PCI_BUS_DATA_RANGE:0] ad_prev;
|
122 |
|
|
output [PCI_BUS_DATA_RANGE:0] master_ad_out;
|
123 |
|
|
output master_ad_oe;
|
124 |
|
|
output [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
|
125 |
|
|
output master_cbe_oe;
|
126 |
|
|
input calc_input_parity_prev;
|
127 |
|
|
input par_now, par_prev;
|
128 |
|
|
input frame_now, frame_prev;
|
129 |
|
|
output master_frame_out, master_frame_oe;
|
130 |
|
|
input irdy_now, irdy_prev;
|
131 |
|
|
output master_irdy_out, master_irdy_oe;
|
132 |
|
|
input devsel_now, devsel_prev, trdy_now, trdy_prev, stop_now, stop_prev;
|
133 |
|
|
input perr_now, perr_prev;
|
134 |
|
|
output master_perr_out, master_perr_oe, master_serr_oe;
|
135 |
|
|
output master_req_out;
|
136 |
|
|
input master_gnt_now;
|
137 |
|
|
input pci_reset_comb, pci_ext_clk;
|
138 |
|
|
// Signals from the master to the target to set bits in the Status Register
|
139 |
|
|
output master_got_parity_error, master_asserted_serr, master_got_master_abort;
|
140 |
|
|
output master_got_target_abort, master_caused_parity_error;
|
141 |
|
|
input master_enable, master_fast_b2b_en, master_perr_enable, master_serr_enable;
|
142 |
|
|
input [7:0] master_latency_value; // NOTE WORKING
|
143 |
|
|
// Signals used by the test bench instead of using "." notation
|
144 |
|
|
output master_debug_force_bad_par;
|
145 |
|
|
input [2:0] test_master_number;
|
146 |
|
|
input [PCI_BUS_DATA_RANGE:0] test_address;
|
147 |
|
|
input [PCI_BUS_CBE_RANGE:0] test_command;
|
148 |
|
|
input [PCI_BUS_DATA_RANGE:0] test_data;
|
149 |
|
|
input [PCI_BUS_CBE_RANGE:0] test_byte_enables_l;
|
150 |
|
|
input [9:0] test_size;
|
151 |
|
|
input test_make_addr_par_error, test_make_data_par_error;
|
152 |
|
|
input [3:0] test_master_initial_wait_states;
|
153 |
|
|
input [3:0] test_master_subsequent_wait_states;
|
154 |
|
|
input [3:0] test_target_initial_wait_states;
|
155 |
|
|
input [3:0] test_target_subsequent_wait_states;
|
156 |
|
|
input [1:0] test_target_devsel_speed;
|
157 |
|
|
input test_fast_back_to_back;
|
158 |
|
|
input [2:0] test_target_termination;
|
159 |
|
|
input test_expect_master_abort;
|
160 |
|
|
input test_start;
|
161 |
|
|
output test_accepted_l;
|
162 |
|
|
output test_error_event;
|
163 |
|
|
input [2:0] test_device_id;
|
164 |
|
|
output [PCI_BUS_DATA_RANGE:0] master_received_data ;
|
165 |
|
|
output master_received_data_valid ;
|
166 |
|
|
input master_check_received_data ;
|
167 |
|
|
|
168 |
|
|
reg [PCI_BUS_DATA_RANGE:0] master_ad_out;
|
169 |
|
|
reg master_ad_oe;
|
170 |
|
|
reg [PCI_BUS_CBE_RANGE:0] master_cbe_l_out;
|
171 |
|
|
reg master_cbe_oe;
|
172 |
|
|
reg master_frame_out, master_irdy_out;
|
173 |
|
|
wire master_frame_oe, master_irdy_oe, master_perr_oe, master_serr_oe;
|
174 |
|
|
reg master_perr_out;
|
175 |
|
|
reg master_req_out;
|
176 |
|
|
reg master_debug_force_bad_par;
|
177 |
|
|
reg [PCI_BUS_DATA_RANGE:0] master_received_data ;
|
178 |
|
|
reg master_received_data_valid ;
|
179 |
|
|
|
180 |
|
|
// Let test commander know when this PCI Master has accepted the command.
|
181 |
|
|
reg test_accepted_next, test_accepted_int;
|
182 |
|
|
// Display on negative edge so easy to see
|
183 |
|
|
always @(negedge pci_ext_clk or posedge pci_reset_comb)
|
184 |
|
|
begin
|
185 |
|
|
if (pci_reset_comb)
|
186 |
|
|
begin
|
187 |
|
|
test_accepted_int <= 1'b0;
|
188 |
|
|
master_received_data_valid <= 1'b0 ;
|
189 |
|
|
end
|
190 |
|
|
else
|
191 |
|
|
begin
|
192 |
|
|
test_accepted_int <= test_accepted_next;
|
193 |
|
|
end
|
194 |
|
|
end
|
195 |
|
|
assign test_accepted_l = test_accepted_int ? 1'b0 : 1'bZ;
|
196 |
|
|
|
197 |
|
|
// Make temporary Bip every time an error is detected
|
198 |
|
|
reg test_error_event;
|
199 |
|
|
initial test_error_event <= 1'bZ;
|
200 |
|
|
reg error_detected;
|
201 |
|
|
initial error_detected <= 1'b0;
|
202 |
|
|
always @(error_detected)
|
203 |
|
|
begin
|
204 |
|
|
test_error_event <= 1'b0;
|
205 |
|
|
#2;
|
206 |
|
|
test_error_event <= 1'bZ;
|
207 |
|
|
end
|
208 |
|
|
|
209 |
|
|
// Make the FRAME_OE and IRDY_OE output enable signals. They must
|
210 |
|
|
// become asserted as soon as each of those signals become asserted, and
|
211 |
|
|
// must stay asserted one clock after the signal becomes deasserted.
|
212 |
|
|
reg prev_frame_asserted, prev_irdy_asserted;
|
213 |
|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
214 |
|
|
begin
|
215 |
|
|
if (pci_reset_comb)
|
216 |
|
|
begin
|
217 |
|
|
prev_frame_asserted <= 1'b0;
|
218 |
|
|
prev_irdy_asserted <= 1'b0;
|
219 |
|
|
end
|
220 |
|
|
else
|
221 |
|
|
begin
|
222 |
|
|
prev_frame_asserted <= master_frame_out;
|
223 |
|
|
prev_irdy_asserted <= master_irdy_out;
|
224 |
|
|
end
|
225 |
|
|
end
|
226 |
|
|
assign master_frame_oe = master_frame_out | prev_frame_asserted;
|
227 |
|
|
assign master_irdy_oe = master_irdy_out | prev_irdy_asserted;
|
228 |
|
|
|
229 |
|
|
// Make the PERR_OE signal.
|
230 |
|
|
// See the PCI Local Bus Spec Revision 2.2 section 3.7.4.1
|
231 |
|
|
// At time N, master_perr_check_next is set
|
232 |
|
|
// At time N+1, external data is latched, and trdy is also latched
|
233 |
|
|
// At time N+1, master_perr_check is latched
|
234 |
|
|
// At time N+2, calc_input_parity_prev is valid
|
235 |
|
|
// Also at N+2, external parity is valid
|
236 |
|
|
// Target can assert data slowly the first reference.
|
237 |
|
|
// Qualify PERR with TRDY (?)
|
238 |
|
|
reg master_perr_prev, master_perr_check_next, master_perr_check;
|
239 |
|
|
reg master_oe_prev, master_oe_prev_prev;
|
240 |
|
|
reg master_perr_detected, master_target_perr_received;
|
241 |
|
|
reg master_debug_force_bad_perr ;
|
242 |
|
|
|
243 |
|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
244 |
|
|
begin
|
245 |
|
|
if (pci_reset_comb)
|
246 |
|
|
master_debug_force_bad_perr <= 1'b0 ;
|
247 |
|
|
else
|
248 |
|
|
master_debug_force_bad_perr <= master_debug_force_bad_par ;
|
249 |
|
|
end
|
250 |
|
|
|
251 |
|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
252 |
|
|
begin
|
253 |
|
|
if (pci_reset_comb)
|
254 |
|
|
begin
|
255 |
|
|
master_perr_check <= 1'b0;
|
256 |
|
|
master_perr_detected <= 1'b0;
|
257 |
|
|
master_target_perr_received <= 1'b0;
|
258 |
|
|
master_perr_out <= 1'b0;
|
259 |
|
|
master_perr_prev <= 1'b0;
|
260 |
|
|
master_oe_prev <= 1'b0;
|
261 |
|
|
master_oe_prev_prev <= 1'b0;
|
262 |
|
|
end
|
263 |
|
|
else
|
264 |
|
|
begin
|
265 |
|
|
master_perr_check <= master_perr_check_next;
|
266 |
|
|
master_perr_detected <= master_perr_check & trdy_prev
|
267 |
|
|
& (calc_input_parity_prev != par_now);
|
268 |
|
|
master_oe_prev <= master_ad_oe;
|
269 |
|
|
master_oe_prev_prev <= master_oe_prev;
|
270 |
|
|
master_target_perr_received <= master_oe_prev_prev & perr_now;
|
271 |
|
|
master_perr_out <= master_perr_check & trdy_prev & master_perr_enable
|
272 |
|
|
& (calc_input_parity_prev != ( par_now ^ master_debug_force_bad_perr));
|
273 |
|
|
master_perr_prev <= master_perr_out;
|
274 |
|
|
end
|
275 |
|
|
end
|
276 |
|
|
assign master_perr_oe = master_perr_out | master_perr_prev;
|
277 |
|
|
|
278 |
|
|
// Tell the Config Status Register when errors occur
|
279 |
|
|
assign master_got_parity_error = master_perr_detected;
|
280 |
|
|
assign master_serr_oe = 1'b0; // This master NEVER asserts SERR
|
281 |
|
|
assign master_asserted_serr = 1'b0; // This master NEVER asserts SERR
|
282 |
|
|
reg master_got_master_abort, master_got_target_abort, master_got_target_retry; // assigned in state machine
|
283 |
|
|
// PERR_detected or PERR pin seen while master
|
284 |
|
|
// See the PCI Local Bus Spec Revision 2.2 section 6.2.3
|
285 |
|
|
assign master_caused_parity_error = master_perr_out
|
286 |
|
|
| (master_target_perr_received & master_perr_enable);
|
287 |
|
|
|
288 |
|
|
// Remember whether this device drove the AD Bus last clock, which allows
|
289 |
|
|
// Zero-Wait-State Back-to-Back references
|
290 |
|
|
wire This_Master_Drove_The_AD_Bus_The_Last_Clock = master_ad_oe;
|
291 |
|
|
|
292 |
|
|
// Model of a Master Source of Data, which writes whatever it wants on bursts
|
293 |
|
|
task Compare_Read_Data_With_Expected_Data;
|
294 |
|
|
input [PCI_BUS_DATA_RANGE:0] target_read_data;
|
295 |
|
|
input [PCI_BUS_DATA_RANGE:0] master_check_data;
|
296 |
|
|
input [PCI_BUS_CBE_RANGE:0] mask_l;// Added by Tadej M. on 11.12.2001
|
297 |
|
|
begin // Added by Tadej M. on 11.12.2001
|
298 |
|
|
if (~pci_reset_comb & ((target_read_data[31:24] != master_check_data[31:24]) & ~mask_l[3]) &
|
299 |
|
|
((target_read_data[23:16] != master_check_data[23:16]) & ~mask_l[2]) &
|
300 |
|
|
((target_read_data[15:8] != master_check_data[15:8]) & ~mask_l[1]) &
|
301 |
|
|
((target_read_data[7:0] != master_check_data[7:0]) & ~mask_l[0]) )
|
302 |
|
|
begin
|
303 |
|
|
$display ("*** test master %h - Master Read Data 'h%x not as expected 'h%x, at %t",
|
304 |
|
|
test_device_id[2:0], target_read_data[PCI_BUS_DATA_RANGE:0],
|
305 |
|
|
master_check_data[PCI_BUS_DATA_RANGE:0], $time);
|
306 |
|
|
error_detected <= ~error_detected;
|
307 |
|
|
end
|
308 |
|
|
`NO_ELSE;
|
309 |
|
|
end
|
310 |
|
|
endtask
|
311 |
|
|
|
312 |
|
|
// Tasks can't have local storage! have to be module global
|
313 |
|
|
reg [PCI_BUS_DATA_RANGE:0] up_temp;
|
314 |
|
|
task Update_Write_Data;
|
315 |
|
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
316 |
|
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
317 |
|
|
output [PCI_BUS_DATA_RANGE:0] master_write_data_next;
|
318 |
|
|
output [PCI_BUS_CBE_RANGE:0] master_mask_l_next;
|
319 |
|
|
begin
|
320 |
|
|
up_temp[31:24] = master_write_data[31:24] + 8'h01;
|
321 |
|
|
up_temp[23:16] = master_write_data[23:16] + 8'h01;
|
322 |
|
|
up_temp[15: 8] = master_write_data[15: 8] + 8'h01;
|
323 |
|
|
up_temp[ 7: 0] = master_write_data[ 7: 0] + 8'h01;
|
324 |
|
|
// Wrap adds so that things repeat in the 256 Byte (64 Word) Target SRAM
|
325 |
|
|
master_write_data_next[PCI_BUS_DATA_RANGE:0] = up_temp[PCI_BUS_DATA_RANGE:0];// & 32'h3F3F3F3F; commented by Tadej M. on 07.12.2001
|
326 |
|
|
master_mask_l_next[PCI_BUS_CBE_RANGE:0] = {master_mask_l[2:0], master_mask_l[3]};
|
327 |
|
|
end
|
328 |
|
|
endtask
|
329 |
|
|
|
330 |
|
|
// Counter to detect unexpected master aborts
|
331 |
|
|
reg [2:0] Master_Abort_Counter;
|
332 |
|
|
|
333 |
|
|
task Init_Master_Abort_Counter;
|
334 |
|
|
begin
|
335 |
|
|
Master_Abort_Counter <= 3'h1;
|
336 |
|
|
end
|
337 |
|
|
endtask
|
338 |
|
|
|
339 |
|
|
task Inc_Master_Abort_Counter;
|
340 |
|
|
begin
|
341 |
|
|
if (Master_Abort_Counter < 3'h7) // count up cycles since Address
|
342 |
|
|
begin
|
343 |
|
|
Master_Abort_Counter <= Master_Abort_Counter + 3'h1;
|
344 |
|
|
end
|
345 |
|
|
`NO_ELSE;
|
346 |
|
|
end
|
347 |
|
|
endtask
|
348 |
|
|
|
349 |
|
|
task Check_Master_Abort_Counter;
|
350 |
|
|
output got_master_abort;
|
351 |
|
|
begin
|
352 |
|
|
got_master_abort = (Master_Abort_Counter >= 3'h5);
|
353 |
|
|
end
|
354 |
|
|
endtask
|
355 |
|
|
|
356 |
|
|
// Signals used by Master test code to apply correct info to the PCI bus
|
357 |
|
|
reg [23:9] hold_master_address;
|
358 |
|
|
reg [PCI_BUS_CBE_RANGE:0] hold_master_command;
|
359 |
|
|
reg [PCI_BUS_DATA_RANGE:0] hold_master_data;
|
360 |
|
|
reg [PCI_BUS_CBE_RANGE:0] hold_master_byte_enables_l;
|
361 |
|
|
reg [9:0] hold_master_size;
|
362 |
|
|
reg hold_master_addr_par_err, hold_master_data_par_err;
|
363 |
|
|
reg [3:0] hold_master_initial_waitstates;
|
364 |
|
|
reg [3:0] hold_master_subsequent_waitstates;
|
365 |
|
|
reg [3:0] hold_master_target_initial_waitstates;
|
366 |
|
|
reg [3:0] hold_master_target_subsequent_waitstates;
|
367 |
|
|
reg [1:0] hold_master_target_devsel_speed;
|
368 |
|
|
reg hold_master_fast_b2b;
|
369 |
|
|
reg [2:0] hold_master_target_termination;
|
370 |
|
|
reg hold_master_expect_master_abort;
|
371 |
|
|
reg [PCI_BUS_DATA_RANGE:0] modified_master_address;
|
372 |
|
|
|
373 |
|
|
// Tasks to do behaviorial PCI references
|
374 |
|
|
// NOTE all tasks end with an @(posedge pci_ext_clk) statement
|
375 |
|
|
// to let any signals asserted during that task settle out.
|
376 |
|
|
// If a task DOESN'T end with @(posedge pci_ext_clk), then it must
|
377 |
|
|
// be called just before some other task which does.
|
378 |
|
|
|
379 |
|
|
parameter TEST_MASTER_SPINLOOP_MAX = 20;
|
380 |
|
|
|
381 |
|
|
task Clock_Wait_Unless_Reset;
|
382 |
|
|
begin
|
383 |
|
|
if (~pci_reset_comb)
|
384 |
|
|
begin
|
385 |
|
|
@ (posedge pci_ext_clk or posedge pci_reset_comb) ;
|
386 |
|
|
end
|
387 |
|
|
`NO_ELSE;
|
388 |
|
|
end
|
389 |
|
|
endtask
|
390 |
|
|
|
391 |
|
|
task Assert_FRAME;
|
392 |
|
|
begin
|
393 |
|
|
master_frame_out <= 1'b1;
|
394 |
|
|
end
|
395 |
|
|
endtask
|
396 |
|
|
|
397 |
|
|
task Deassert_FRAME;
|
398 |
|
|
begin
|
399 |
|
|
master_frame_out <= 1'b0;
|
400 |
|
|
end
|
401 |
|
|
endtask
|
402 |
|
|
|
403 |
|
|
task Assert_IRDY;
|
404 |
|
|
begin
|
405 |
|
|
master_irdy_out <= 1'b1;
|
406 |
|
|
end
|
407 |
|
|
endtask
|
408 |
|
|
|
409 |
|
|
task Deassert_IRDY;
|
410 |
|
|
begin
|
411 |
|
|
master_irdy_out <= 1'b0;
|
412 |
|
|
end
|
413 |
|
|
endtask
|
414 |
|
|
|
415 |
|
|
task Assert_Master_Continue_Or_Terminate;
|
416 |
|
|
input do_master_terminate;
|
417 |
|
|
begin
|
418 |
|
|
if (do_master_terminate)
|
419 |
|
|
begin
|
420 |
|
|
Deassert_FRAME; Assert_IRDY;
|
421 |
|
|
end
|
422 |
|
|
else
|
423 |
|
|
begin
|
424 |
|
|
Assert_FRAME; Assert_IRDY;
|
425 |
|
|
end
|
426 |
|
|
end
|
427 |
|
|
endtask
|
428 |
|
|
|
429 |
|
|
task Indicate_Start;
|
430 |
|
|
begin
|
431 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
432 |
|
|
$display (" test %h - Task Started, at %t", test_device_id[2:0], $time);
|
433 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
434 |
|
|
test_accepted_next <= 1'b1;
|
435 |
|
|
end
|
436 |
|
|
endtask
|
437 |
|
|
|
438 |
|
|
task Indicate_Done;
|
439 |
|
|
begin
|
440 |
|
|
// `ifdef VERBOSE_TEST_DEVICE
|
441 |
|
|
// $display (" test %h - Task Done, at %t", test_device_id[2:0], $time);
|
442 |
|
|
// `endif // VERBOSE_TEST_DEVICE
|
443 |
|
|
test_accepted_next <= 1'b0;
|
444 |
|
|
end
|
445 |
|
|
endtask
|
446 |
|
|
|
447 |
|
|
task Master_Req_Bus; // must be followed by an address assertion task
|
448 |
|
|
begin
|
449 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
450 |
|
|
$display (" test %h - Requesting the bus, at %t",
|
451 |
|
|
test_device_id[2:0], $time);
|
452 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
453 |
|
|
master_req_out <= 1'b1;
|
454 |
|
|
end
|
455 |
|
|
endtask
|
456 |
|
|
|
457 |
|
|
task Master_Unreq_Bus; // must be followed by SOMETHING???
|
458 |
|
|
begin
|
459 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
460 |
|
|
$display (" test %h - Un-Requesting the bus, at %t",
|
461 |
|
|
test_device_id[2:0], $time);
|
462 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
463 |
|
|
master_req_out <= 1'b0;
|
464 |
|
|
end
|
465 |
|
|
endtask
|
466 |
|
|
|
467 |
|
|
parameter TEST_MASTER_IMMEDIATE_ADDRESS = 1'b0;
|
468 |
|
|
parameter TEST_MASTER_STEP_ADDRESS = 1'b1;
|
469 |
|
|
|
470 |
|
|
// Tasks can't have local storage! have to be module global
|
471 |
|
|
integer ii; // sequential code, so OK to use "=" assignment operator
|
472 |
|
|
reg first_step_delay;
|
473 |
|
|
task Master_Assert_Address;
|
474 |
|
|
input [PCI_BUS_DATA_RANGE:0] address;
|
475 |
|
|
input [PCI_BUS_CBE_RANGE:0] command;
|
476 |
|
|
input address_speed, enable_fast_back_to_back, force_addr_par_error;
|
477 |
|
|
begin
|
478 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
479 |
|
|
$display (" test %h - Driving Address 'h%x, CBE 'h%x, at %t",
|
480 |
|
|
test_device_id[2:0], address[PCI_BUS_DATA_RANGE:0],
|
481 |
|
|
command[PCI_BUS_CBE_RANGE:0], $time);
|
482 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
483 |
|
|
first_step_delay = (address_speed == TEST_MASTER_STEP_ADDRESS);
|
484 |
|
|
for (ii = 0; ii < TEST_MASTER_SPINLOOP_MAX; ii = ii + 1)
|
485 |
|
|
begin
|
486 |
|
|
if (master_gnt_now
|
487 |
|
|
& ( (~frame_now & ~irdy_now) // and bus previously idle
|
488 |
|
|
// ... or we previously were driving data, so fast back-to-back is possible.
|
489 |
|
|
| ( ~frame_now & irdy_now
|
490 |
|
|
& This_Master_Drove_The_AD_Bus_The_Last_Clock
|
491 |
|
|
& enable_fast_back_to_back & master_fast_b2b_en) ) )
|
492 |
|
|
begin
|
493 |
|
|
if (first_step_delay == 1'b1)
|
494 |
|
|
begin // stepping, so drive address with some unknown bits
|
495 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= address[PCI_BUS_DATA_RANGE:0] ^ 32'hXX00XX00;
|
496 |
|
|
master_ad_oe <= 1'b1;
|
497 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= command[PCI_BUS_CBE_RANGE:0] ^ 4'bX0X0;
|
498 |
|
|
master_cbe_oe <= 1'b1;
|
499 |
|
|
master_debug_force_bad_par <= 1'b1;
|
500 |
|
|
master_got_master_abort <= 1'b0;
|
501 |
|
|
master_got_target_abort <= 1'b0;
|
502 |
|
|
master_got_target_retry <= 1'b0;
|
503 |
|
|
master_perr_check_next <= 1'b0;
|
504 |
|
|
Deassert_FRAME;
|
505 |
|
|
Deassert_IRDY;
|
506 |
|
|
first_step_delay = 1'b0; // next time through, make frame
|
507 |
|
|
end
|
508 |
|
|
else
|
509 |
|
|
begin // drive address AND frame
|
510 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= address[PCI_BUS_DATA_RANGE:0];
|
511 |
|
|
master_ad_oe <= 1'b1;
|
512 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= command[PCI_BUS_CBE_RANGE:0];
|
513 |
|
|
master_cbe_oe <= 1'b1;
|
514 |
|
|
master_debug_force_bad_par <= force_addr_par_error;
|
515 |
|
|
master_got_master_abort <= 1'b0;
|
516 |
|
|
master_got_target_abort <= 1'b0;
|
517 |
|
|
master_got_target_retry <= 1'b0;
|
518 |
|
|
master_perr_check_next <= 1'b0;
|
519 |
|
|
Assert_FRAME;
|
520 |
|
|
Deassert_IRDY;
|
521 |
|
|
Init_Master_Abort_Counter; // just completed master cycle 1
|
522 |
|
|
first_step_delay = 1'b0; // next time through, make frame
|
523 |
|
|
ii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
524 |
|
|
end
|
525 |
|
|
end
|
526 |
|
|
else
|
527 |
|
|
begin // might have lost things after first step. Undrive everything.
|
528 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
529 |
|
|
master_ad_oe <= 1'b0;
|
530 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
531 |
|
|
master_cbe_oe <= 1'b0;
|
532 |
|
|
master_debug_force_bad_par <= 1'b0;
|
533 |
|
|
master_got_master_abort <= 1'b0;
|
534 |
|
|
master_got_target_abort <= 1'b0;
|
535 |
|
|
master_got_target_retry <= 1'b0;
|
536 |
|
|
master_perr_check_next <= 1'b0;
|
537 |
|
|
Deassert_FRAME;
|
538 |
|
|
Deassert_IRDY;
|
539 |
|
|
first_step_delay = (address_speed == TEST_MASTER_STEP_ADDRESS);
|
540 |
|
|
end
|
541 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
542 |
|
|
Indicate_Done; // indicate done as early as possible, while still after start
|
543 |
|
|
end
|
544 |
|
|
`ifdef NORMAL_PCI_CHECKS
|
545 |
|
|
if (~pci_reset_comb & (ii == TEST_MASTER_SPINLOOP_MAX))
|
546 |
|
|
begin
|
547 |
|
|
$display ("*** test %h - PCI Gnt never arrived, at %t",
|
548 |
|
|
test_device_id[2:0], $time);
|
549 |
|
|
error_detected <= ~error_detected;
|
550 |
|
|
end
|
551 |
|
|
`NO_ELSE;
|
552 |
|
|
`endif // NORMAL_PCI_CHECKS
|
553 |
|
|
end
|
554 |
|
|
endtask
|
555 |
|
|
|
556 |
|
|
// While asserting FRAME, wait zero or more clocks as commanded by master
|
557 |
|
|
// tasks can't have local storage! have to be module global
|
558 |
|
|
reg [3:0] cnt;
|
559 |
|
|
task Execute_Master_Waitstates_But_Quit_On_Target_Abort;
|
560 |
|
|
input drive_ad_bus;
|
561 |
|
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
562 |
|
|
input [3:0] num_waitstates;
|
563 |
|
|
begin
|
564 |
|
|
for (cnt = 4'h0; cnt < num_waitstates[3:0]; cnt = cnt + 4'h1)
|
565 |
|
|
begin
|
566 |
|
|
if (~devsel_now & stop_now)
|
567 |
|
|
begin
|
568 |
|
|
cnt = num_waitstates[3:0]; // immediate exit on Target Abort
|
569 |
|
|
end
|
570 |
|
|
else
|
571 |
|
|
begin
|
572 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_WAIT_STATE_VALUE;
|
573 |
|
|
master_ad_oe <= drive_ad_bus;
|
574 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
575 |
|
|
master_cbe_oe <= 1'b1;
|
576 |
|
|
master_debug_force_bad_par <= 1'b0;
|
577 |
|
|
master_got_master_abort <= 1'b0;
|
578 |
|
|
master_got_target_abort <= 1'b0;
|
579 |
|
|
master_got_target_retry <= 1'b0;
|
580 |
|
|
master_perr_check_next <= ~drive_ad_bus;
|
581 |
|
|
Assert_FRAME; // frame, but no action
|
582 |
|
|
Deassert_IRDY;
|
583 |
|
|
Inc_Master_Abort_Counter;
|
584 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
585 |
|
|
end
|
586 |
|
|
end
|
587 |
|
|
end
|
588 |
|
|
endtask
|
589 |
|
|
|
590 |
|
|
task Check_Target_Abort;
|
591 |
|
|
input got_target_abort;
|
592 |
|
|
input [9:0] words_transferred;
|
593 |
|
|
input [9:0] words_expected;
|
594 |
|
|
begin
|
595 |
|
|
if (~got_target_abort)
|
596 |
|
|
begin
|
597 |
|
|
$display ("*** test master %h - Target Abort not received when expected, at %t",
|
598 |
|
|
test_device_id[2:0], $time);
|
599 |
|
|
error_detected <= ~error_detected;
|
600 |
|
|
end
|
601 |
|
|
else if (words_transferred[9:0] != words_expected[9:0])
|
602 |
|
|
begin
|
603 |
|
|
$display ("*** test master %h - Target Abort received, but Word Count %d not %d, at %t",
|
604 |
|
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
605 |
|
|
error_detected <= ~error_detected;
|
606 |
|
|
end
|
607 |
|
|
`NO_ELSE;
|
608 |
|
|
end
|
609 |
|
|
endtask
|
610 |
|
|
|
611 |
|
|
task Check_Target_Retry;
|
612 |
|
|
input got_target_retry;
|
613 |
|
|
input [9:0] words_transferred;
|
614 |
|
|
input [9:0] words_expected;
|
615 |
|
|
begin
|
616 |
|
|
if (~got_target_retry)
|
617 |
|
|
begin
|
618 |
|
|
$display ("*** test master %h - Target Retry not received when expected, at %t",
|
619 |
|
|
test_device_id[2:0], $time);
|
620 |
|
|
error_detected <= ~error_detected;
|
621 |
|
|
end
|
622 |
|
|
else if (words_transferred[9:0] != words_expected[9:0])
|
623 |
|
|
begin
|
624 |
|
|
$display ("*** test master %h - Target Retry received, but Word Count %d not %d, at %t",
|
625 |
|
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
626 |
|
|
error_detected <= ~error_detected;
|
627 |
|
|
end
|
628 |
|
|
`NO_ELSE;
|
629 |
|
|
end
|
630 |
|
|
endtask
|
631 |
|
|
|
632 |
|
|
task Check_Target_Stop;
|
633 |
|
|
input got_target_stop;
|
634 |
|
|
input [9:0] words_transferred;
|
635 |
|
|
input [9:0] words_expected;
|
636 |
|
|
begin
|
637 |
|
|
if (~got_target_stop)
|
638 |
|
|
begin
|
639 |
|
|
$display ("*** test master %h - Target Stop not received when expected, at %t",
|
640 |
|
|
test_device_id[2:0], $time);
|
641 |
|
|
error_detected <= ~error_detected;
|
642 |
|
|
end
|
643 |
|
|
else if (words_transferred[9:0] != words_expected[9:0])
|
644 |
|
|
begin
|
645 |
|
|
$display ("*** test master %h - Target Stop received, but Word Count %d not %d, at %t",
|
646 |
|
|
test_device_id[2:0], words_transferred, words_expected, $time);
|
647 |
|
|
error_detected <= ~error_detected;
|
648 |
|
|
end
|
649 |
|
|
`NO_ELSE;
|
650 |
|
|
end
|
651 |
|
|
endtask
|
652 |
|
|
|
653 |
|
|
// The initiator asked for a certain termination scheme. Did it do that?
|
654 |
|
|
task Check_Master_Burst_Termination_Cause;
|
655 |
|
|
input got_master_abort, got_master_terminate;
|
656 |
|
|
input got_target_retry, got_target_stop, got_target_abort;
|
657 |
|
|
input [9:0] words_transferred;
|
658 |
|
|
begin
|
659 |
|
|
if (~pci_reset_comb)
|
660 |
|
|
begin
|
661 |
|
|
// Check for Master Abort status
|
662 |
|
|
if (~hold_master_expect_master_abort & got_master_abort)
|
663 |
|
|
begin
|
664 |
|
|
$display ("*** test master %h - Master Abort received when none was expected, at %t",
|
665 |
|
|
test_device_id[2:0], $time);
|
666 |
|
|
error_detected <= ~error_detected;
|
667 |
|
|
end
|
668 |
|
|
`NO_ELSE;
|
669 |
|
|
if (hold_master_expect_master_abort & ~got_master_abort)
|
670 |
|
|
begin
|
671 |
|
|
$display ("*** test master %h - Master Abort not received when expected, at %t",
|
672 |
|
|
test_device_id[2:0], $time);
|
673 |
|
|
error_detected <= ~error_detected;
|
674 |
|
|
end
|
675 |
|
|
`NO_ELSE;
|
676 |
|
|
// Check for Target Abort status
|
677 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Abort_On)
|
678 |
|
|
Check_Target_Abort (got_target_abort, words_transferred[9:0], hold_master_size - 1);
|
679 |
|
|
|
680 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Abort_Before)
|
681 |
|
|
begin
|
682 |
|
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
683 |
|
|
begin
|
684 |
|
|
Check_Target_Abort (got_target_abort, words_transferred[9:0], hold_master_size - 2);
|
685 |
|
|
end
|
686 |
|
|
else
|
687 |
|
|
begin
|
688 |
|
|
Check_Target_Stop (got_master_terminate,
|
689 |
|
|
words_transferred[9:0], hold_master_size[9:0]);
|
690 |
|
|
end
|
691 |
|
|
end
|
692 |
|
|
`NO_ELSE;
|
693 |
|
|
// Check for Target Retry status
|
694 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Retry_On)
|
695 |
|
|
begin
|
696 |
107 |
tadejm |
// Check_Target_Retry (got_target_retry, words_transferred[9:0], hold_master_size - 1);
|
697 |
|
|
// tadejm, tadejm@flextronics.si, 7.8.2003; target disconnect is target_retry and target_stop
|
698 |
|
|
Check_Target_Retry ((got_target_retry || got_target_stop), words_transferred[9:0], hold_master_size - 1);
|
699 |
19 |
mihad |
end
|
700 |
|
|
`NO_ELSE;
|
701 |
|
|
|
702 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Retry_Before)
|
703 |
|
|
begin
|
704 |
|
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
705 |
|
|
begin
|
706 |
107 |
tadejm |
// Check_Target_Retry (got_target_retry, words_transferred[9:0], hold_master_size - 2);
|
707 |
|
|
// tadejm, tadejm@flextronics.si, 7.8.2003; target disconnect is target_retry and target_stop
|
708 |
|
|
Check_Target_Retry ((got_target_retry || got_target_stop), words_transferred[9:0], hold_master_size - 2);
|
709 |
19 |
mihad |
end
|
710 |
|
|
else
|
711 |
|
|
begin
|
712 |
|
|
Check_Target_Stop (got_master_terminate,
|
713 |
|
|
words_transferred[9:0], hold_master_size[9:0]);
|
714 |
|
|
end
|
715 |
|
|
end
|
716 |
|
|
`NO_ELSE;
|
717 |
|
|
// Check for Target Disconnect status
|
718 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Disc_On)
|
719 |
|
|
begin
|
720 |
|
|
Check_Target_Stop (got_target_stop, words_transferred[9:0], hold_master_size);
|
721 |
|
|
end
|
722 |
|
|
`NO_ELSE;
|
723 |
|
|
|
724 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Disc_Before)
|
725 |
|
|
begin
|
726 |
|
|
if (hold_master_size[9:0] >= 10'h2) // too small, don't get a chance to do 2
|
727 |
|
|
begin
|
728 |
|
|
Check_Target_Stop (got_target_stop, words_transferred[9:0], hold_master_size - 1);
|
729 |
|
|
end
|
730 |
|
|
else
|
731 |
|
|
begin
|
732 |
|
|
Check_Target_Stop (got_master_terminate,
|
733 |
|
|
words_transferred[9:0], hold_master_size[9:0]);
|
734 |
|
|
end
|
735 |
|
|
end
|
736 |
|
|
`NO_ELSE;
|
737 |
|
|
// Check for retry due to starting a delayed read
|
738 |
|
|
if (hold_master_target_termination[2:0] == `Test_Target_Start_Delayed_Read)
|
739 |
|
|
begin
|
740 |
107 |
tadejm |
// Check_Target_Retry (got_target_retry, words_transferred[9:0], 10'h0);
|
741 |
|
|
// tadejm, tadejm@flextronics.si, 7.8.2003; target disconnect is target_retry and target_stop
|
742 |
|
|
Check_Target_Retry ((got_target_retry || got_target_stop), words_transferred[9:0], 10'h0);
|
743 |
19 |
mihad |
end
|
744 |
|
|
`NO_ELSE;
|
745 |
|
|
|
746 |
|
|
// Check for normal completion caused by the Master
|
747 |
|
|
if ( (hold_master_target_termination[2:0] == `Test_Target_Normal_Completion)
|
748 |
|
|
& ~hold_master_expect_master_abort )
|
749 |
|
|
begin
|
750 |
|
|
if (got_target_abort)
|
751 |
|
|
begin
|
752 |
|
|
$display ("*** test master %h - Target Abort received when doing normal transfer, at %t",
|
753 |
|
|
test_device_id[2:0], $time);
|
754 |
|
|
error_detected <= ~error_detected;
|
755 |
|
|
end
|
756 |
|
|
`NO_ELSE;
|
757 |
|
|
if (got_target_retry)
|
758 |
|
|
begin
|
759 |
|
|
$display ("*** test master %h - Target Retry received when doing normal transfer, at %t",
|
760 |
|
|
test_device_id[2:0], $time);
|
761 |
|
|
error_detected <= ~error_detected;
|
762 |
|
|
end
|
763 |
|
|
`NO_ELSE;
|
764 |
|
|
if (words_transferred[9:0] != hold_master_size[9:0])
|
765 |
|
|
begin
|
766 |
|
|
$display ("*** test master %h - Normal Transfer, but Word Count %d not %d, at %t",
|
767 |
|
|
test_device_id[2:0], words_transferred, hold_master_size, $time);
|
768 |
|
|
error_detected <= ~error_detected;
|
769 |
|
|
end
|
770 |
|
|
`NO_ELSE;
|
771 |
|
|
end
|
772 |
|
|
`NO_ELSE;
|
773 |
|
|
end
|
774 |
|
|
end
|
775 |
|
|
endtask
|
776 |
|
|
|
777 |
|
|
// Linger until DEVSEL.
|
778 |
|
|
// Tasks can't have local storage! have to be module global
|
779 |
|
|
integer iii;
|
780 |
|
|
task Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort;
|
781 |
|
|
input drive_ad_bus;
|
782 |
|
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
783 |
|
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
784 |
|
|
input do_master_terminate;
|
785 |
|
|
output got_master_abort;
|
786 |
|
|
begin
|
787 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
788 |
|
|
$display (" test %h - Lingering waiting for DEVSEL, at %t",
|
789 |
|
|
test_device_id[2:0], $time);
|
790 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
791 |
|
|
for (iii = 0; iii < TEST_MASTER_SPINLOOP_MAX; iii = iii + 1)
|
792 |
|
|
begin
|
793 |
|
|
if (~devsel_now) // no master yet
|
794 |
|
|
begin
|
795 |
|
|
if (stop_now) // target abort!
|
796 |
|
|
begin
|
797 |
|
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
798 |
|
|
got_master_abort = 1'b0; // target abort handled before master abort
|
799 |
|
|
end
|
800 |
|
|
else
|
801 |
|
|
begin
|
802 |
|
|
Check_Master_Abort_Counter (got_master_abort);
|
803 |
|
|
if (got_master_abort) // immediate exit on master abort
|
804 |
|
|
begin
|
805 |
|
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
806 |
|
|
end
|
807 |
|
|
else
|
808 |
|
|
begin
|
809 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
810 |
|
|
master_ad_oe <= drive_ad_bus;
|
811 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
812 |
|
|
master_cbe_oe <= 1'b1;
|
813 |
|
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
814 |
|
|
master_got_master_abort <= 1'b0;
|
815 |
|
|
master_got_target_abort <= 1'b0;
|
816 |
|
|
master_got_target_retry <= 1'b0;
|
817 |
|
|
master_perr_check_next <= ~drive_ad_bus;
|
818 |
|
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
819 |
|
|
Inc_Master_Abort_Counter;
|
820 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
821 |
|
|
end
|
822 |
|
|
end
|
823 |
|
|
end
|
824 |
|
|
else
|
825 |
|
|
begin
|
826 |
|
|
iii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
827 |
|
|
got_master_abort = 1'b0; // success
|
828 |
|
|
end
|
829 |
|
|
end
|
830 |
|
|
if (iii == TEST_MASTER_SPINLOOP_MAX)
|
831 |
|
|
begin
|
832 |
|
|
got_master_abort = 1'b1; // fail if fall off end
|
833 |
|
|
end
|
834 |
|
|
`NO_ELSE;
|
835 |
|
|
`ifdef NORMAL_PCI_CHECKS
|
836 |
|
|
if (~pci_reset_comb & (iii == TEST_MASTER_SPINLOOP_MAX))
|
837 |
|
|
begin
|
838 |
|
|
$display ("*** test master %h - Bus didn't get DEVSEL during Master ref, at %t",
|
839 |
|
|
test_device_id[2:0], $time);
|
840 |
|
|
error_detected <= ~error_detected;
|
841 |
|
|
end
|
842 |
|
|
`NO_ELSE;
|
843 |
|
|
`endif // NORMAL_PCI_CHECKS
|
844 |
|
|
end
|
845 |
|
|
endtask
|
846 |
|
|
|
847 |
|
|
// Linger until TRDY or STOP are asserted.
|
848 |
|
|
// Tasks can't have local storage! have to be module global
|
849 |
|
|
integer iiii;
|
850 |
|
|
task Linger_Until_Target_Waitstates_Done;
|
851 |
|
|
input drive_ad_bus;
|
852 |
|
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
853 |
|
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
854 |
|
|
input do_master_terminate;
|
855 |
|
|
begin
|
856 |
|
|
for (iiii = 0; iiii < TEST_MASTER_SPINLOOP_MAX; iiii = iiii + 1)
|
857 |
|
|
begin
|
858 |
|
|
if (~trdy_now & ~stop_now) // stick in master wait states
|
859 |
|
|
begin
|
860 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
861 |
|
|
master_ad_oe <= drive_ad_bus;
|
862 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
863 |
|
|
master_cbe_oe <= 1'b1;
|
864 |
|
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
865 |
|
|
master_got_master_abort <= 1'b0;
|
866 |
|
|
master_got_target_abort <= 1'b0;
|
867 |
|
|
master_got_target_retry <= 1'b0;
|
868 |
|
|
master_perr_check_next <= ~drive_ad_bus;
|
869 |
|
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
870 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
871 |
|
|
end
|
872 |
|
|
else
|
873 |
|
|
begin
|
874 |
|
|
iiii = TEST_MASTER_SPINLOOP_MAX + 1; // break
|
875 |
|
|
end
|
876 |
|
|
end
|
877 |
|
|
`ifdef NORMAL_PCI_CHECKS
|
878 |
|
|
if (~pci_reset_comb & (iiii == TEST_MASTER_SPINLOOP_MAX))
|
879 |
|
|
begin
|
880 |
|
|
$display ("*** test master %h - Bus didn't get DEVSEL during Master ref, at %t",
|
881 |
|
|
test_device_id[2:0], $time);
|
882 |
|
|
error_detected <= ~error_detected;
|
883 |
|
|
end
|
884 |
|
|
`NO_ELSE;
|
885 |
|
|
`endif // NORMAL_PCI_CHECKS
|
886 |
|
|
end
|
887 |
|
|
endtask
|
888 |
|
|
|
889 |
|
|
// Transfer a word with or without target termination, and act on Master Termination
|
890 |
|
|
// This task MIGHT be entered when DEVSEL is Deasserted and STOP is Asserted!
|
891 |
|
|
// Handle this Target Abort if it occurs.
|
892 |
|
|
task Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B;
|
893 |
|
|
input drive_ad_bus;
|
894 |
|
|
input watching_for_master_abort;
|
895 |
|
|
input do_master_terminate;
|
896 |
|
|
input enable_fast_back_to_back;
|
897 |
|
|
input [PCI_BUS_DATA_RANGE:0] master_write_data;
|
898 |
|
|
input [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
899 |
|
|
output [PCI_BUS_DATA_RANGE:0] target_read_data;
|
900 |
|
|
output got_master_abort, got_target_retry, got_target_stop, got_target_abort;
|
901 |
|
|
output want_fast_back_to_back;
|
902 |
|
|
begin
|
903 |
|
|
if (~devsel_now & stop_now)
|
904 |
|
|
begin // Target Abort.
|
905 |
|
|
got_master_abort = 1'b0;
|
906 |
|
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
907 |
|
|
do_master_terminate = 1'b0; // force clean termination activity as if master abort
|
908 |
|
|
end
|
909 |
|
|
else
|
910 |
|
|
begin
|
911 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
912 |
|
|
master_ad_oe <= drive_ad_bus;
|
913 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
914 |
|
|
master_cbe_oe <= 1'b1;
|
915 |
|
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
916 |
|
|
master_got_master_abort <= 1'b0;
|
917 |
|
|
master_got_target_abort <= 1'b0;
|
918 |
|
|
master_got_target_retry <= 1'b0;
|
919 |
|
|
master_perr_check_next <= ~drive_ad_bus;
|
920 |
|
|
Assert_Master_Continue_Or_Terminate (do_master_terminate);
|
921 |
|
|
Inc_Master_Abort_Counter;
|
922 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
923 |
|
|
if (watching_for_master_abort)
|
924 |
|
|
begin
|
925 |
|
|
Linger_Until_DEVSEL_Or_Master_Abort_Or_Target_Abort (drive_ad_bus,
|
926 |
|
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
927 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
928 |
|
|
do_master_terminate, got_master_abort);
|
929 |
|
|
end
|
930 |
|
|
else
|
931 |
|
|
begin
|
932 |
|
|
got_master_abort = 1'b0;
|
933 |
|
|
end
|
934 |
|
|
if (got_master_abort)
|
935 |
|
|
begin
|
936 |
|
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
937 |
|
|
end
|
938 |
|
|
else
|
939 |
|
|
begin
|
940 |
|
|
Linger_Until_Target_Waitstates_Done (drive_ad_bus,
|
941 |
|
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
942 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
943 |
|
|
do_master_terminate);
|
944 |
|
|
target_read_data[PCI_BUS_DATA_RANGE:0] = ad_now[PCI_BUS_DATA_RANGE:0]; // unconditionally grab.
|
945 |
|
|
if (~devsel_now & stop_now)
|
946 |
|
|
begin
|
947 |
|
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
948 |
|
|
end
|
949 |
|
|
else if (devsel_now & trdy_now & stop_now)
|
950 |
|
|
begin
|
951 |
|
|
got_target_retry = 1'b0; got_target_stop = 1'b1; got_target_abort = 1'b0;
|
952 |
|
|
end
|
953 |
|
|
else if (devsel_now & ~trdy_now & stop_now)
|
954 |
|
|
begin
|
955 |
|
|
got_target_retry = 1'b1; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
956 |
|
|
end
|
957 |
|
|
else if (devsel_now & trdy_now & ~stop_now)
|
958 |
|
|
begin
|
959 |
|
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b0;
|
960 |
|
|
end
|
961 |
|
|
else
|
962 |
|
|
begin
|
963 |
|
|
if (~pci_reset_comb)
|
964 |
|
|
begin
|
965 |
|
|
$display ("*** test %h - Master got unexpected Target Handshake Signals, at %t",
|
966 |
|
|
test_device_id[2:0], $time);
|
967 |
|
|
error_detected <= ~error_detected;
|
968 |
|
|
end
|
969 |
|
|
`NO_ELSE;
|
970 |
|
|
got_target_retry = 1'b0; got_target_stop = 1'b0; got_target_abort = 1'b1;
|
971 |
|
|
end
|
972 |
|
|
end
|
973 |
|
|
end
|
974 |
|
|
if ((got_master_abort | got_target_retry | got_target_stop | got_target_abort)
|
975 |
|
|
& ~do_master_terminate) // If not do_master_terminate, FRAME still asserted
|
976 |
|
|
begin // turn-around cycle on FRAME
|
977 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= master_write_data[PCI_BUS_DATA_RANGE:0];
|
978 |
|
|
master_ad_oe <= drive_ad_bus;
|
979 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= master_mask_l[PCI_BUS_CBE_RANGE:0];
|
980 |
|
|
master_cbe_oe <= 1'b1;
|
981 |
|
|
master_debug_force_bad_par <= hold_master_data_par_err;
|
982 |
|
|
master_got_master_abort <= 1'b0;
|
983 |
|
|
master_got_target_abort <= 1'b0;
|
984 |
|
|
master_got_target_retry <= 1'b0;
|
985 |
|
|
master_perr_check_next <= ~drive_ad_bus;
|
986 |
|
|
Deassert_FRAME; // do the work that master_terminate would have already done
|
987 |
|
|
Assert_IRDY;
|
988 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
989 |
|
|
end
|
990 |
|
|
if (got_master_abort | got_target_retry | got_target_stop | got_target_abort
|
991 |
|
|
| do_master_terminate) // If do_master_terminate, FRAME already deasserted
|
992 |
|
|
begin
|
993 |
|
|
// If doing immediate Address phase due to fast back-to-back, don't drive bus here
|
994 |
|
|
// Extremely subtle point.
|
995 |
|
|
// Cannot do a fast back-to-back transfer if Address Lines are being stepped!
|
996 |
|
|
// Fast-Back-To-Back only works if the device is able to grab the bus the next cycle.
|
997 |
|
|
// It must do this because the PCI Arbiter thinks the bus is busy, and might grant
|
998 |
|
|
// mastership to another party without a wait state assuming that an idle state
|
999 |
|
|
// must be inserted by the present device before it re-drives the bus.
|
1000 |
|
|
// The other party will drive the bus the next clock if it does NOT see FRAME
|
1001 |
|
|
// asserted now. Frame will always be delayed by address-stepping devices.
|
1002 |
|
|
// See the PCI Local Bus Spec Revision 2.2 section 3.4.1 and 3.4.2.
|
1003 |
|
|
// no fast B2B if master or target abort, to give time to report error to Config Reg
|
1004 |
|
|
if (~got_master_abort & ~got_target_abort
|
1005 |
|
|
& master_gnt_now & enable_fast_back_to_back & master_fast_b2b_en
|
1006 |
|
|
& This_Master_Drove_The_AD_Bus_The_Last_Clock
|
1007 |
|
|
& test_start & (test_master_number[2:0] == test_device_id[2:0])
|
1008 |
|
|
& ( (test_command[3:0] != PCI_COMMAND_CONFIG_READ)
|
1009 |
|
|
& (test_command[3:0] != PCI_COMMAND_CONFIG_WRITE) ) )
|
1010 |
|
|
begin
|
1011 |
|
|
want_fast_back_to_back = 1'b1;
|
1012 |
|
|
// No clock here to let the next command dispatch quickly. The dispatcher has a wait
|
1013 |
|
|
end
|
1014 |
|
|
else
|
1015 |
|
|
begin
|
1016 |
|
|
// Otherwise enforce an idle state
|
1017 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
1018 |
|
|
master_ad_oe <= 1'b0;
|
1019 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
1020 |
|
|
master_cbe_oe <= 1'b0;
|
1021 |
|
|
master_debug_force_bad_par <= 1'b0;
|
1022 |
|
|
master_got_master_abort <= got_master_abort;
|
1023 |
|
|
master_got_target_abort <= got_target_abort;
|
1024 |
|
|
master_got_target_retry <= got_target_retry;
|
1025 |
|
|
master_perr_check_next <= 1'b0;
|
1026 |
|
|
Deassert_FRAME;
|
1027 |
|
|
Deassert_IRDY;
|
1028 |
|
|
want_fast_back_to_back = 1'b0;
|
1029 |
|
|
end
|
1030 |
|
|
end
|
1031 |
|
|
else
|
1032 |
|
|
begin
|
1033 |
|
|
want_fast_back_to_back = 1'b0;
|
1034 |
|
|
end
|
1035 |
|
|
end
|
1036 |
|
|
endtask
|
1037 |
|
|
|
1038 |
|
|
parameter TEST_MASTER_DOING_CONFIG_READ = 3'b000;
|
1039 |
|
|
parameter TEST_MASTER_DOING_CONFIG_WRITE = 3'b001;
|
1040 |
|
|
parameter TEST_MASTER_DOING_MEM_READ = 3'b010;
|
1041 |
|
|
parameter TEST_MASTER_DOING_MEM_WRITE = 3'b011;
|
1042 |
|
|
parameter TEST_MASTER_DOING_MEM_READ_LN = 3'b100; // Added by Tadej M., 06.12.2001
|
1043 |
|
|
parameter TEST_MASTER_DOING_MEM_READ_MUL = 3'b110; // Added by Tadej M., 06.12.2001
|
1044 |
|
|
|
1045 |
|
|
task Report_On_Master_PCI_Ref_Start;
|
1046 |
|
|
input [2:0] reference_type;
|
1047 |
|
|
begin
|
1048 |
|
|
case (reference_type[2:0])
|
1049 |
|
|
TEST_MASTER_DOING_CONFIG_READ:
|
1050 |
|
|
$display (" test master %h - Starting Config Read, at %t",
|
1051 |
|
|
test_device_id[2:0], $time);
|
1052 |
|
|
TEST_MASTER_DOING_CONFIG_WRITE:
|
1053 |
|
|
$display (" test master %h - Starting Config Write, at %t",
|
1054 |
|
|
test_device_id[2:0], $time);
|
1055 |
|
|
TEST_MASTER_DOING_MEM_READ:
|
1056 |
|
|
$display (" test master %h - Starting Memory Read, at %t",
|
1057 |
|
|
test_device_id[2:0], $time);
|
1058 |
|
|
TEST_MASTER_DOING_MEM_WRITE:
|
1059 |
|
|
$display (" test master %h - Starting Memory Write, at %t",
|
1060 |
|
|
test_device_id[2:0], $time);
|
1061 |
|
|
TEST_MASTER_DOING_MEM_READ_LN:
|
1062 |
|
|
$display (" test master %h - Starting Memory Read Line, at %t",
|
1063 |
|
|
test_device_id[2:0], $time);
|
1064 |
|
|
TEST_MASTER_DOING_MEM_READ_MUL:
|
1065 |
|
|
$display (" test master %h - Starting Memory Read Line Multiple, at %t",
|
1066 |
|
|
test_device_id[2:0], $time);
|
1067 |
|
|
default:
|
1068 |
|
|
$display (" test master %h - Doing Unknown Reference, at %t",
|
1069 |
|
|
test_device_id[2:0], $time);
|
1070 |
|
|
endcase
|
1071 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
1072 |
|
|
Report_Master_Reference_Paramaters;
|
1073 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
1074 |
|
|
end
|
1075 |
|
|
endtask
|
1076 |
|
|
|
1077 |
|
|
task Report_On_Master_PCI_Ref_Finish;
|
1078 |
|
|
input got_master_abort;
|
1079 |
|
|
input got_target_abort;
|
1080 |
|
|
input got_target_retry;
|
1081 |
|
|
input got_target_stop;
|
1082 |
|
|
input [9:0] words_transferred;
|
1083 |
|
|
begin
|
1084 |
|
|
if (got_master_abort)
|
1085 |
|
|
begin
|
1086 |
|
|
$display (" test master %h - Got Master Abort, at %t",
|
1087 |
|
|
test_device_id[2:0], $time);
|
1088 |
|
|
end
|
1089 |
|
|
`NO_ELSE;
|
1090 |
|
|
if (got_target_abort)
|
1091 |
|
|
begin
|
1092 |
|
|
$display (" test master %h - Got Target Abort, at %t",
|
1093 |
|
|
test_device_id[2:0], $time);
|
1094 |
|
|
end
|
1095 |
|
|
`NO_ELSE;
|
1096 |
|
|
if (got_target_retry)
|
1097 |
|
|
begin
|
1098 |
|
|
$display (" test master %h - Got Target Retry, at %t",
|
1099 |
|
|
test_device_id[2:0], $time);
|
1100 |
|
|
end
|
1101 |
|
|
`NO_ELSE;
|
1102 |
|
|
if (got_target_stop)
|
1103 |
|
|
begin
|
1104 |
|
|
$display (" test master %h - Got Target Stop, at %t",
|
1105 |
|
|
test_device_id[2:0], $time);
|
1106 |
|
|
end
|
1107 |
|
|
`NO_ELSE;
|
1108 |
|
|
if (~got_master_abort & ~got_target_abort & ~got_target_retry & ~got_target_stop)
|
1109 |
|
|
begin
|
1110 |
|
|
$display (" test master %h - Normal Success, at %t",
|
1111 |
|
|
test_device_id[2:0], $time);
|
1112 |
|
|
end
|
1113 |
|
|
`NO_ELSE;
|
1114 |
|
|
if (words_transferred != 10'h0)
|
1115 |
|
|
begin
|
1116 |
|
|
$display (" test master %h - Transferred %h words, at %t",
|
1117 |
|
|
test_device_id[2:0], words_transferred[9:0], $time);
|
1118 |
|
|
end
|
1119 |
|
|
`NO_ELSE;
|
1120 |
|
|
end
|
1121 |
|
|
endtask
|
1122 |
|
|
|
1123 |
|
|
// Tasks can't have local storage! have to be module global
|
1124 |
|
|
reg step_address;
|
1125 |
|
|
reg [3:0] wait_states_this_time;
|
1126 |
|
|
reg [9:0] words_transferred;
|
1127 |
|
|
reg drive_ad_bus, watching_for_master_abort, do_master_terminate_this_time;
|
1128 |
|
|
reg [PCI_BUS_DATA_RANGE:0] target_read_data;
|
1129 |
|
|
reg [PCI_BUS_DATA_RANGE:0] master_write_data;
|
1130 |
|
|
reg [PCI_BUS_CBE_RANGE:0] master_mask_l;
|
1131 |
|
|
reg [PCI_BUS_DATA_RANGE:0] master_write_data_next;
|
1132 |
|
|
reg [PCI_BUS_CBE_RANGE:0] master_mask_l_next;
|
1133 |
|
|
reg got_master_abort, got_target_retry, got_target_stop, got_target_abort;
|
1134 |
|
|
reg got_master_terminate;
|
1135 |
|
|
task Execute_Master_PCI_Ref;
|
1136 |
|
|
input [2:0] reference_type;
|
1137 |
|
|
output want_fast_back_to_back;
|
1138 |
|
|
begin
|
1139 |
|
|
Master_Req_Bus;
|
1140 |
|
|
if ( (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_READ)
|
1141 |
|
|
| (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_WRITE) )
|
1142 |
|
|
begin
|
1143 |
|
|
step_address = TEST_MASTER_STEP_ADDRESS;
|
1144 |
|
|
end
|
1145 |
|
|
else
|
1146 |
|
|
begin
|
1147 |
|
|
step_address = TEST_MASTER_IMMEDIATE_ADDRESS;
|
1148 |
|
|
end
|
1149 |
|
|
Master_Assert_Address (modified_master_address[PCI_BUS_DATA_RANGE:0],
|
1150 |
|
|
hold_master_command[PCI_BUS_CBE_RANGE:0],
|
1151 |
|
|
step_address, hold_master_fast_b2b, hold_master_addr_par_err);
|
1152 |
|
|
Master_Unreq_Bus; // After FRAME is asserted!
|
1153 |
|
|
`ifdef REPORT_TEST_DEVICE
|
1154 |
|
|
// Do Report after Address to let the time of the report line up with the bus event.
|
1155 |
|
|
Report_On_Master_PCI_Ref_Start (reference_type[2:0]);
|
1156 |
|
|
`endif // REPORT_TEST_DEVICE
|
1157 |
|
|
drive_ad_bus = (reference_type[2:0] == TEST_MASTER_DOING_CONFIG_WRITE)
|
1158 |
|
|
| (reference_type[2:0] == TEST_MASTER_DOING_MEM_WRITE);
|
1159 |
|
|
words_transferred = 9'h0;
|
1160 |
|
|
wait_states_this_time = hold_master_initial_waitstates[3:0];
|
1161 |
|
|
do_master_terminate_this_time =
|
1162 |
|
|
((words_transferred[9:0] + 4'h1) == hold_master_size[9:0]);
|
1163 |
|
|
watching_for_master_abort = 1'b1;
|
1164 |
|
|
master_write_data[PCI_BUS_DATA_RANGE:0] = hold_master_data[PCI_BUS_DATA_RANGE:0];
|
1165 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0] = hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0];
|
1166 |
|
|
got_master_abort = 1'b0;
|
1167 |
|
|
got_target_retry = 1'b0;
|
1168 |
|
|
got_target_stop = 1'b0;
|
1169 |
|
|
got_target_abort = 1'b0;
|
1170 |
|
|
got_master_terminate = 1'b0;
|
1171 |
|
|
while ( ~got_master_abort & ~got_target_retry & ~got_target_stop
|
1172 |
|
|
& ~got_target_abort & ~got_master_terminate)
|
1173 |
|
|
begin
|
1174 |
|
|
Execute_Master_Waitstates_But_Quit_On_Target_Abort (drive_ad_bus,
|
1175 |
|
|
master_mask_l[3:0], wait_states_this_time[3:0]);
|
1176 |
|
|
Execute_Master_Ref_Undrive_All_In_Any_Termination_Unless_Fast_B2B (drive_ad_bus,
|
1177 |
|
|
watching_for_master_abort, do_master_terminate_this_time,
|
1178 |
|
|
hold_master_fast_b2b, master_write_data[PCI_BUS_DATA_RANGE:0],
|
1179 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
1180 |
|
|
target_read_data[PCI_BUS_DATA_RANGE:0],
|
1181 |
|
|
got_master_abort, got_target_retry,
|
1182 |
|
|
got_target_stop, got_target_abort,
|
1183 |
|
|
want_fast_back_to_back);
|
1184 |
|
|
got_master_terminate = do_master_terminate_this_time;
|
1185 |
|
|
if (~got_master_abort & ~got_target_retry & ~got_target_abort)
|
1186 |
|
|
begin
|
1187 |
|
|
if (~drive_ad_bus)
|
1188 |
|
|
begin
|
1189 |
|
|
if ( master_check_received_data )
|
1190 |
|
|
Compare_Read_Data_With_Expected_Data (target_read_data[PCI_BUS_DATA_RANGE:0],
|
1191 |
|
|
master_write_data[PCI_BUS_DATA_RANGE:0],
|
1192 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0]);
|
1193 |
|
|
|
1194 |
|
|
master_received_data = target_read_data ;
|
1195 |
|
|
master_received_data_valid <= ~master_received_data_valid ;
|
1196 |
|
|
end
|
1197 |
|
|
`NO_ELSE;
|
1198 |
|
|
wait_states_this_time = hold_master_subsequent_waitstates[3:0];
|
1199 |
|
|
words_transferred = words_transferred + 10'b1;
|
1200 |
|
|
do_master_terminate_this_time =
|
1201 |
|
|
((words_transferred[9:0] + 4'h1) == hold_master_size[9:0]);
|
1202 |
|
|
watching_for_master_abort = 1'b0;
|
1203 |
|
|
Update_Write_Data (master_write_data[PCI_BUS_DATA_RANGE:0],
|
1204 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0],
|
1205 |
|
|
master_write_data_next[PCI_BUS_DATA_RANGE:0],
|
1206 |
|
|
master_mask_l_next[PCI_BUS_CBE_RANGE:0]);
|
1207 |
|
|
master_write_data[PCI_BUS_DATA_RANGE:0] = master_write_data_next[PCI_BUS_DATA_RANGE:0];
|
1208 |
|
|
master_mask_l[PCI_BUS_CBE_RANGE:0] = master_mask_l_next[PCI_BUS_CBE_RANGE:0];
|
1209 |
|
|
end
|
1210 |
|
|
`NO_ELSE;
|
1211 |
|
|
end
|
1212 |
|
|
`ifdef NORMAL_PCI_CHECKS
|
1213 |
|
|
Check_Master_Burst_Termination_Cause (got_master_abort, got_master_terminate,
|
1214 |
|
|
got_target_retry, got_target_stop, got_target_abort,
|
1215 |
|
|
words_transferred[9:0]);
|
1216 |
|
|
`endif // NORMAL_PCI_CHECKS
|
1217 |
|
|
`ifdef VERBOSE_TEST_DEVICE
|
1218 |
|
|
Report_On_Master_PCI_Ref_Finish (got_master_abort, got_target_abort,
|
1219 |
|
|
got_target_retry, got_target_stop,
|
1220 |
|
|
words_transferred[9:0]);
|
1221 |
|
|
`endif // VERBOSE_TEST_DEVICE
|
1222 |
|
|
end
|
1223 |
|
|
endtask
|
1224 |
|
|
|
1225 |
|
|
// Task to print debug info
|
1226 |
|
|
// NOTE This must change if bit allocation changes
|
1227 |
|
|
task Report_Master_Reference_Paramaters;
|
1228 |
|
|
begin
|
1229 |
|
|
if (hold_master_address[23:9] != 15'h0000)
|
1230 |
|
|
begin
|
1231 |
|
|
// hold_master_address, hold_master_command, hold_master_data,
|
1232 |
|
|
// hold_master_byte_enables_l, hold_master_size
|
1233 |
|
|
$display (" First Master Data Wait States %h, Subsequent Master Data Wait States %h",
|
1234 |
|
|
hold_master_initial_waitstates[3:0],
|
1235 |
|
|
hold_master_subsequent_waitstates[3:0]);
|
1236 |
|
|
$display (" Master Fast B-to_B En %h, Expect Master Abort %h",
|
1237 |
|
|
hold_master_fast_b2b, hold_master_expect_master_abort);
|
1238 |
|
|
$display (" Target Devsel Speed %h, Target Termination %h,",
|
1239 |
|
|
hold_master_target_devsel_speed[1:0],
|
1240 |
|
|
hold_master_target_termination[2:0]);
|
1241 |
|
|
$display (" First Target Data Wait States %h, Subsequent Target Data Wait States %h",
|
1242 |
|
|
hold_master_target_initial_waitstates[3:0],
|
1243 |
|
|
hold_master_target_subsequent_waitstates[3:0]);
|
1244 |
|
|
$display (" Addr Par Error %h, Data Par Error %h",
|
1245 |
|
|
hold_master_addr_par_err, hold_master_data_par_err);
|
1246 |
|
|
end
|
1247 |
|
|
`NO_ELSE;
|
1248 |
|
|
end
|
1249 |
|
|
endtask
|
1250 |
|
|
|
1251 |
|
|
task Complain_That_Test_Not_Written;
|
1252 |
|
|
output want_fast_back_to_back;
|
1253 |
|
|
begin
|
1254 |
|
|
$display ("*** test master %h - Diag not written yet: 'h%x, at %t",
|
1255 |
|
|
test_device_id[2:0], hold_master_command[3:0], $time);
|
1256 |
|
|
error_detected <= ~error_detected;
|
1257 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
1258 |
|
|
master_ad_oe <= 1'b0;
|
1259 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4; // easy to see
|
1260 |
|
|
master_cbe_oe <= 1'b0;
|
1261 |
|
|
master_debug_force_bad_par <= 1'b0;
|
1262 |
|
|
master_got_master_abort <= 1'b0;
|
1263 |
|
|
master_got_target_abort <= 1'b0;
|
1264 |
|
|
master_got_target_retry <= 1'b0;
|
1265 |
|
|
master_perr_check_next <= 1'b0;
|
1266 |
|
|
Deassert_FRAME;
|
1267 |
|
|
Deassert_IRDY;
|
1268 |
|
|
Clock_Wait_Unless_Reset; // wait for outputs to settle
|
1269 |
|
|
Indicate_Done; // indicate done as early as possible, while still after start
|
1270 |
|
|
want_fast_back_to_back = 1'b0;
|
1271 |
|
|
end
|
1272 |
|
|
endtask
|
1273 |
|
|
|
1274 |
|
|
task Reset_Master_To_Idle;
|
1275 |
|
|
begin
|
1276 |
|
|
master_req_out <= 1'b0;
|
1277 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_ZERO;
|
1278 |
|
|
master_ad_oe <= 1'b0;
|
1279 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_ZERO;
|
1280 |
|
|
master_cbe_oe <= 1'b0;
|
1281 |
|
|
master_frame_out <= 1'b0; master_irdy_out <= 1'b0;
|
1282 |
|
|
master_got_master_abort <= 1'b0;
|
1283 |
|
|
master_got_target_abort <= 1'b0;
|
1284 |
|
|
master_got_target_retry <= 1'b0;
|
1285 |
|
|
master_perr_check_next <= 1'b0;
|
1286 |
|
|
test_accepted_next <= 1'b0;
|
1287 |
|
|
end
|
1288 |
|
|
endtask
|
1289 |
|
|
|
1290 |
|
|
// We want the Target to do certain behavior to let us test the interface.
|
1291 |
|
|
// We will use Address Bits to encode Target Wait State, Target Completion,
|
1292 |
|
|
// and Target Error info.
|
1293 |
|
|
//
|
1294 |
|
|
// Our Test Chips will use an 8-Bit Base Address Register, which
|
1295 |
|
|
// will result in a 16 MByte memory map for each BAR.
|
1296 |
|
|
// Our Targets only have 256 bytes of SRAM. That leaves 16 Address
|
1297 |
|
|
// Bits to play with.
|
1298 |
|
|
// Allocate Address Bits to mean the following:
|
1299 |
|
|
// Bit [23] When 1, the Target acts upon the fancy encoded info below
|
1300 |
|
|
// Bits [22:19] Target Wait States for First Data Item
|
1301 |
|
|
// Bits [18:15] Target Wait States for Subsequent Data Items
|
1302 |
|
|
// Bits [14:12] What sort of Target Termination to make
|
1303 |
|
|
// Bits [11:10] Devsel Speed
|
1304 |
|
|
// Bit [9] Whether to make or expect a Data Parity Error
|
1305 |
|
|
// Bit [8] Whether to expect an Address Parity Error
|
1306 |
|
|
|
1307 |
|
|
// fire off Master tasks in response to top-level testbench
|
1308 |
|
|
reg want_fast_back_to_back;
|
1309 |
|
|
always @(posedge pci_ext_clk or posedge pci_reset_comb)
|
1310 |
|
|
begin
|
1311 |
|
|
if ( ~pci_reset_comb & test_start
|
1312 |
|
|
& (test_master_number[2:0] == test_device_id[2:0]))
|
1313 |
|
|
begin
|
1314 |
|
|
want_fast_back_to_back = 1'b1;
|
1315 |
|
|
while (want_fast_back_to_back)
|
1316 |
|
|
begin
|
1317 |
|
|
Indicate_Start;
|
1318 |
|
|
// Grab address and data in case it takes a while to get bus mastership
|
1319 |
|
|
// Intentionally use "=" assignment so these variables are available to tasks
|
1320 |
|
|
hold_master_address[23:9] = test_address[23:9];
|
1321 |
|
|
hold_master_command[3:0] = test_command[3:0];
|
1322 |
|
|
hold_master_data[PCI_BUS_DATA_RANGE:0] = test_data[PCI_BUS_DATA_RANGE:0];
|
1323 |
|
|
hold_master_byte_enables_l[PCI_BUS_CBE_RANGE:0] =
|
1324 |
|
|
test_byte_enables_l[PCI_BUS_CBE_RANGE:0];
|
1325 |
|
|
hold_master_size[9:0] = test_size[9:0];
|
1326 |
|
|
hold_master_addr_par_err = test_make_addr_par_error;
|
1327 |
|
|
hold_master_data_par_err = test_make_data_par_error;
|
1328 |
|
|
hold_master_initial_waitstates[3:0] = test_master_initial_wait_states[3:0];
|
1329 |
|
|
hold_master_subsequent_waitstates[3:0] = test_master_subsequent_wait_states[3:0];
|
1330 |
|
|
hold_master_target_initial_waitstates[3:0] = test_target_initial_wait_states[3:0];
|
1331 |
|
|
hold_master_target_subsequent_waitstates[3:0] = test_target_subsequent_wait_states[3:0];
|
1332 |
|
|
hold_master_target_devsel_speed[1:0] = test_target_devsel_speed[1:0];
|
1333 |
|
|
hold_master_fast_b2b = test_fast_back_to_back;
|
1334 |
|
|
hold_master_target_termination[2:0] = test_target_termination[2:0];
|
1335 |
|
|
hold_master_expect_master_abort = test_expect_master_abort;
|
1336 |
|
|
if (hold_master_size[9:0] == 0) // This means read causing delayed read
|
1337 |
|
|
begin
|
1338 |
|
|
hold_master_size = 1;
|
1339 |
|
|
hold_master_target_termination = `Test_Target_Retry_Before_First;
|
1340 |
|
|
end
|
1341 |
|
|
`NO_ELSE;
|
1342 |
|
|
// changed by Miha D. - no need for encoded addresses
|
1343 |
|
|
modified_master_address = test_address ;
|
1344 |
|
|
/*
|
1345 |
|
|
modified_master_address[31:24] = test_address[31:24];
|
1346 |
|
|
modified_master_address[`TARGET_ENCODED_PARAMATERS_ENABLE] = 1'b1;
|
1347 |
|
|
modified_master_address[`TARGET_ENCODED_INIT_WAITSTATES] =
|
1348 |
|
|
test_target_initial_wait_states[3:0];
|
1349 |
|
|
modified_master_address[`TARGET_ENCODED_SUBS_WAITSTATES] =
|
1350 |
|
|
test_target_subsequent_wait_states[3:0];
|
1351 |
|
|
modified_master_address[`TARGET_ENCODED_TERMINATION] =
|
1352 |
|
|
test_target_termination[2:0];
|
1353 |
|
|
modified_master_address[`TARGET_ENCODED_DEVSEL_SPEED] =
|
1354 |
|
|
test_target_devsel_speed[1:0];
|
1355 |
|
|
modified_master_address[`TARGET_ENCODED_DATA_PAR_ERR] =
|
1356 |
|
|
test_make_data_par_error;
|
1357 |
|
|
modified_master_address[`TARGET_ENCODED_ADDR_PAR_ERR] =
|
1358 |
|
|
test_make_addr_par_error;
|
1359 |
|
|
modified_master_address[7:0] = test_address[7:0];
|
1360 |
|
|
*/
|
1361 |
|
|
case (test_command[3:0])
|
1362 |
|
|
PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
|
1363 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1364 |
|
|
PCI_COMMAND_SPECIAL_CYCLE:
|
1365 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1366 |
|
|
PCI_COMMAND_IO_READ:
|
1367 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
|
1368 |
|
|
want_fast_back_to_back);
|
1369 |
|
|
PCI_COMMAND_IO_WRITE:
|
1370 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
|
1371 |
|
|
want_fast_back_to_back);
|
1372 |
|
|
PCI_COMMAND_RESERVED_READ_4:
|
1373 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1374 |
|
|
PCI_COMMAND_RESERVED_WRITE_5:
|
1375 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1376 |
|
|
PCI_COMMAND_MEMORY_READ:
|
1377 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ,
|
1378 |
|
|
want_fast_back_to_back);
|
1379 |
|
|
PCI_COMMAND_MEMORY_WRITE:
|
1380 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_WRITE,
|
1381 |
|
|
want_fast_back_to_back);
|
1382 |
|
|
PCI_COMMAND_RESERVED_READ_8:
|
1383 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1384 |
|
|
PCI_COMMAND_RESERVED_WRITE_9:
|
1385 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1386 |
|
|
PCI_COMMAND_CONFIG_READ:
|
1387 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_READ,
|
1388 |
|
|
want_fast_back_to_back);
|
1389 |
|
|
PCI_COMMAND_CONFIG_WRITE:
|
1390 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_CONFIG_WRITE,
|
1391 |
|
|
want_fast_back_to_back);
|
1392 |
|
|
PCI_COMMAND_MEMORY_READ_MULTIPLE: // Added by Tadej M., 06.12.2001
|
1393 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ_MUL,
|
1394 |
|
|
want_fast_back_to_back);
|
1395 |
|
|
// Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1396 |
|
|
PCI_COMMAND_DUAL_ADDRESS_CYCLE:
|
1397 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1398 |
|
|
PCI_COMMAND_MEMORY_READ_LINE: // Added by Tadej M., 06.12.2001
|
1399 |
|
|
Execute_Master_PCI_Ref (TEST_MASTER_DOING_MEM_READ_LN,
|
1400 |
|
|
want_fast_back_to_back);
|
1401 |
|
|
// Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1402 |
|
|
PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
|
1403 |
|
|
Complain_That_Test_Not_Written (want_fast_back_to_back);
|
1404 |
|
|
default:
|
1405 |
|
|
begin
|
1406 |
|
|
$display ("*** test master %h - Unknown External Device Activity 'h%x, at %t",
|
1407 |
|
|
test_device_id[2:0], test_command, $time);
|
1408 |
|
|
error_detected <= ~error_detected;
|
1409 |
|
|
end
|
1410 |
|
|
endcase
|
1411 |
|
|
if (pci_reset_comb)
|
1412 |
|
|
begin
|
1413 |
|
|
want_fast_back_to_back = 1'b0;
|
1414 |
|
|
end
|
1415 |
|
|
`NO_ELSE;
|
1416 |
|
|
end
|
1417 |
|
|
end // while want_fast_back_to_back
|
1418 |
|
|
else if (~frame_now & ~irdy_now & master_gnt_now)
|
1419 |
|
|
begin // park bus
|
1420 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_PARK_VALUE;
|
1421 |
|
|
master_ad_oe <= 1'b1;
|
1422 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
|
1423 |
|
|
master_cbe_oe <= 1'b1;
|
1424 |
|
|
end
|
1425 |
|
|
else
|
1426 |
|
|
begin // unpark if grant is removed
|
1427 |
|
|
master_ad_out[PCI_BUS_DATA_RANGE:0] <= `BUS_IMPOSSIBLE_VALUE;
|
1428 |
|
|
master_ad_oe <= 1'b0;
|
1429 |
|
|
master_cbe_l_out[PCI_BUS_CBE_RANGE:0] <= PCI_COMMAND_RESERVED_READ_4;
|
1430 |
|
|
master_cbe_oe <= 1'b0;
|
1431 |
|
|
end
|
1432 |
|
|
// NOTE WORKING need to handle master_got_target_retry here
|
1433 |
|
|
|
1434 |
|
|
// Because this is sequential code, have to reset all regs if the above falls
|
1435 |
|
|
// through due to a reset. This would not be needed in synthesizable code.
|
1436 |
|
|
if (pci_reset_comb)
|
1437 |
|
|
begin
|
1438 |
|
|
Reset_Master_To_Idle;
|
1439 |
|
|
end
|
1440 |
|
|
`NO_ELSE;
|
1441 |
|
|
end
|
1442 |
|
|
endmodule
|
1443 |
|
|
|