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mihad |
ncvlog: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
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ncvlog: v03.30.(p001): Started on Jul 08, 2001 at 11:28:41
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ncvlog
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-f ./ncvlog.args
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-cdslib ../bin/cds.lib
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-hdlvar ../bin/hdl.var
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-logfile ../log/ncvlog.log
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-update
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-messages
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-INCDIR ../../../bench/verilog
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-INCDIR ../../../rtl/verilog
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../../../rtl/verilog/pci_parity_check.v
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../../../rtl/verilog/pci_target_unit.v
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../../../rtl/verilog/wb_addr_mux.v
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../../../rtl/verilog/cbe_en_crit.v
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../../../rtl/verilog/fifo_control.v
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../../../rtl/verilog/out_reg.v
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../../../rtl/verilog/pci_tpram.v
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../../../rtl/verilog/wb_master.v
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../../../rtl/verilog/conf_cyc_addr_dec.v
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../../../rtl/verilog/frame_crit.v
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../../../rtl/verilog/pci_target32_clk_en.v
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../../../rtl/verilog/pciw_fifo_control.v
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../../../rtl/verilog/wb_slave.v
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../../../rtl/verilog/conf_space.v
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../../../rtl/verilog/frame_en_crit.v
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../../../rtl/verilog/par_crit.v
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../../../rtl/verilog/pciw_pcir_fifos.v
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../../../rtl/verilog/wb_slave_unit.v
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../../../rtl/verilog/frame_load_crit.v
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../../../rtl/verilog/pci_bridge32.v
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../../../rtl/verilog/pci_target32_devs_crit.v
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../../../rtl/verilog/perr_crit.v
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../../../rtl/verilog/wbr_fifo_control.v
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../../../rtl/verilog/cur_out_reg.v
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../../../rtl/verilog/pci_decoder.v
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../../../rtl/verilog/pci_target32_interface.v
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../../../rtl/verilog/perr_en_crit.v
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../../../rtl/verilog/wbw_fifo_control.v
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../../../rtl/verilog/decoder.v
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../../../rtl/verilog/pci_in_reg.v
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../../../rtl/verilog/serr_crit.v
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../../../rtl/verilog/wbw_wbr_fifos.v
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../../../rtl/verilog/delayed_sync.v
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../../../rtl/verilog/irdy_out_crit.v
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../../../rtl/verilog/pci_io_mux.v
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../../../rtl/verilog/pci_io_mux_ad_en_crit.v
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../../../rtl/verilog/pci_io_mux_ad_load_crit.v
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../../../rtl/verilog/pci_target32_sm.v
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../../../rtl/verilog/serr_en_crit.v
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../../../rtl/verilog/delayed_write_reg.v
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../../../rtl/verilog/mas_ad_en_crit.v
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../../../rtl/verilog/mas_ad_load_crit.v
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../../../rtl/verilog/pci_master32_sm.v
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../../../rtl/verilog/pci_target32_stop_crit.v
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../../../rtl/verilog/synchronizer_flop.v
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../../../rtl/verilog/async_reset_flop.v
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../../../rtl/verilog/mas_ch_state_crit.v
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../../../rtl/verilog/pci_master32_sm_if.v
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../../../rtl/verilog/pci_target32_trdy_crit.v
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../../../rtl/verilog/top.v
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../../../rtl/verilog/pci_rst_int.v
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../../../rtl/verilog/sync_module.v
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../../../rtl/verilog/wb_tpram.v
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../../../bench/verilog/wb_master32.v
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../../../bench/verilog/wb_master_behavioral.v
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../../../bench/verilog/system.v
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../../../bench/verilog/pci_blue_arbiter.v
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../../../bench/verilog/pci_bus_monitor.v
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../../../bench/verilog/pci_behaviorial_device.v
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../../../bench/verilog/pci_behaviorial_master.v
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../../../bench/verilog/pci_behaviorial_target.v
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../../../bench/verilog/wb_slave_behavioral.v
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../../../bench/verilog/wb_bus_mon.v
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../../../bench/verilog/pci_behavioral_iack_target.v
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../../../bench/verilog/pci_unsupported_commands_master.v
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../../../../../../lib/xilinx/lib/glbl/glbl.v
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../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
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../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
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file: ../../../rtl/verilog/pci_parity_check.v
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module worklib.PCI_PARITY_CHECK:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_target_unit.v
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module worklib.PCI_TARGET_UNIT:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wb_addr_mux.v
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module worklib.WB_ADDR_MUX:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/cbe_en_crit.v
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module worklib.CBE_EN_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/fifo_control.v
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module worklib.FIFO_CONTROL:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/out_reg.v
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module worklib.OUT_REG:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_tpram.v
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module worklib.PCI_TPRAM:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wb_master.v
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module worklib.WB_MASTER:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/conf_cyc_addr_dec.v
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module worklib.CONF_CYC_ADDR_DEC:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/frame_crit.v
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module worklib.FRAME_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_target32_clk_en.v
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module worklib.PCI_TARGET32_CLK_EN:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pciw_fifo_control.v
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module worklib.PCIW_FIFO_CONTROL:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wb_slave.v
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module worklib.WB_SLAVE:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/conf_space.v
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module worklib.CONF_SPACE:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/frame_en_crit.v
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module worklib.FRAME_EN_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/par_crit.v
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module worklib.PAR_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pciw_pcir_fifos.v
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module worklib.PCIW_PCIR_FIFOS:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wb_slave_unit.v
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module worklib.WB_SLAVE_UNIT:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/frame_load_crit.v
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module worklib.FRAME_LOAD_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_bridge32.v
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module worklib.PCI_BRIDGE32:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_target32_devs_crit.v
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module worklib.PCI_TARGET32_DEVS_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/perr_crit.v
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module worklib.PERR_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wbr_fifo_control.v
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module worklib.WBR_FIFO_CONTROL:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/cur_out_reg.v
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module worklib.CUR_OUT_REG:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_decoder.v
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module worklib.PCI_DECODER:v
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errors: 0, warnings: 0
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156 |
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file: ../../../rtl/verilog/pci_target32_interface.v
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module worklib.PCI_TARGET32_INTERFACE:v
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errors: 0, warnings: 0
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159 |
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file: ../../../rtl/verilog/perr_en_crit.v
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module worklib.PERR_EN_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wbw_fifo_control.v
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module worklib.WBW_FIFO_CONTROL:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/decoder.v
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module worklib.DECODER:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_in_reg.v
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module worklib.PCI_IN_REG:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/serr_crit.v
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module worklib.SERR_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/wbw_wbr_fifos.v
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module worklib.WBW_WBR_FIFOS:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/delayed_sync.v
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module worklib.DELAYED_SYNC:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/irdy_out_crit.v
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module worklib.IRDY_OUT_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_io_mux.v
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module worklib.PCI_IO_MUX:v (up-to-date)
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errors: 0, warnings: 0
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186 |
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file: ../../../rtl/verilog/pci_io_mux_ad_en_crit.v
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module worklib.PCI_IO_MUX_AD_EN_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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189 |
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file: ../../../rtl/verilog/pci_io_mux_ad_load_crit.v
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module worklib.PCI_IO_MUX_AD_LOAD_CRIT:v (up-to-date)
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191 |
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errors: 0, warnings: 0
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192 |
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file: ../../../rtl/verilog/pci_target32_sm.v
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193 |
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module worklib.PCI_TARGET32_SM:v
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/serr_en_crit.v
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module worklib.SERR_EN_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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198 |
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file: ../../../rtl/verilog/delayed_write_reg.v
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module worklib.DELAYED_WRITE_REG:v
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errors: 0, warnings: 0
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201 |
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file: ../../../rtl/verilog/mas_ad_en_crit.v
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module worklib.MAS_AD_EN_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/mas_ad_load_crit.v
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module worklib.MAS_AD_LOAD_CRIT:v (up-to-date)
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errors: 0, warnings: 0
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file: ../../../rtl/verilog/pci_master32_sm.v
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module worklib.PCI_MASTER32_SM:v
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errors: 0, warnings: 0
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210 |
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file: ../../../rtl/verilog/pci_target32_stop_crit.v
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211 |
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module worklib.PCI_TARGET32_STOP_CRIT:v (up-to-date)
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212 |
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errors: 0, warnings: 0
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213 |
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file: ../../../rtl/verilog/synchronizer_flop.v
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module worklib.synchronizer_flop:v (up-to-date)
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215 |
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errors: 0, warnings: 0
|
216 |
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file: ../../../rtl/verilog/async_reset_flop.v
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217 |
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module worklib.async_reset_flop:v
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218 |
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errors: 0, warnings: 0
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219 |
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file: ../../../rtl/verilog/mas_ch_state_crit.v
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module worklib.MAS_CH_STATE_CRIT:v (up-to-date)
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221 |
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errors: 0, warnings: 0
|
222 |
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file: ../../../rtl/verilog/pci_master32_sm_if.v
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module worklib.PCI_MASTER32_SM_IF:v
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errors: 0, warnings: 0
|
225 |
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file: ../../../rtl/verilog/pci_target32_trdy_crit.v
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226 |
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module worklib.PCI_TARGET32_TRDY_CRIT:v (up-to-date)
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227 |
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errors: 0, warnings: 0
|
228 |
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file: ../../../rtl/verilog/top.v
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229 |
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module worklib.TOP:v
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230 |
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errors: 0, warnings: 0
|
231 |
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file: ../../../rtl/verilog/pci_rst_int.v
|
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module worklib.PCI_RST_INT:v
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233 |
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errors: 0, warnings: 0
|
234 |
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file: ../../../rtl/verilog/sync_module.v
|
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module worklib.SYNC_MODULE:v (up-to-date)
|
236 |
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errors: 0, warnings: 0
|
237 |
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file: ../../../rtl/verilog/wb_tpram.v
|
238 |
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module worklib.WB_TPRAM:v
|
239 |
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errors: 0, warnings: 0
|
240 |
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file: ../../../bench/verilog/wb_master32.v
|
241 |
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module worklib.WB_MASTER32:v
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242 |
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errors: 0, warnings: 0
|
243 |
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file: ../../../bench/verilog/wb_master_behavioral.v
|
244 |
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module worklib.WB_MASTER_BEHAVIORAL:v
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245 |
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errors: 0, warnings: 0
|
246 |
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file: ../../../bench/verilog/system.v
|
247 |
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module worklib.SYSTEM:v
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248 |
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errors: 0, warnings: 0
|
249 |
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file: ../../../bench/verilog/pci_blue_arbiter.v
|
250 |
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module worklib.pci_blue_arbiter:v (up-to-date)
|
251 |
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errors: 0, warnings: 0
|
252 |
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file: ../../../bench/verilog/pci_bus_monitor.v
|
253 |
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module worklib.pci_bus_monitor:v (up-to-date)
|
254 |
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errors: 0, warnings: 0
|
255 |
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file: ../../../bench/verilog/pci_behaviorial_device.v
|
256 |
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module worklib.pci_behaviorial_device:v (up-to-date)
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257 |
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errors: 0, warnings: 0
|
258 |
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module worklib.delayed_test_pad:v (up-to-date)
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259 |
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errors: 0, warnings: 0
|
260 |
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file: ../../../bench/verilog/pci_behaviorial_master.v
|
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module worklib.pci_behaviorial_master:v (up-to-date)
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262 |
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errors: 0, warnings: 0
|
263 |
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file: ../../../bench/verilog/pci_behaviorial_target.v
|
264 |
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module worklib.pci_behaviorial_target:v (up-to-date)
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265 |
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errors: 0, warnings: 0
|
266 |
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file: ../../../bench/verilog/wb_slave_behavioral.v
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267 |
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module worklib.WB_SLAVE_BEHAVIORAL:v
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268 |
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errors: 0, warnings: 0
|
269 |
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file: ../../../bench/verilog/wb_bus_mon.v
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270 |
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module worklib.WB_BUS_MON:v
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271 |
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errors: 0, warnings: 0
|
272 |
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file: ../../../bench/verilog/pci_behavioral_iack_target.v
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273 |
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module worklib.PCI_BEHAVIORAL_IACK_TARGET:v
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274 |
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errors: 0, warnings: 0
|
275 |
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file: ../../../bench/verilog/pci_unsupported_commands_master.v
|
276 |
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module worklib.pci_unsupported_commands_master:v
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277 |
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errors: 0, warnings: 0
|
278 |
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file: ../../../../../../lib/xilinx/lib/glbl/glbl.v
|
279 |
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module worklib.glbl:v (up-to-date)
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280 |
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errors: 0, warnings: 0
|
281 |
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file: ../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
|
282 |
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module worklib.RAMB4_S16_S16:v (up-to-date)
|
283 |
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errors: 0, warnings: 0
|
284 |
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file: ../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
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module worklib.RAM16X1D:v (up-to-date)
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errors: 0, warnings: 0
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ncvlog: v03.30.(p001): Exiting on Jul 08, 2001 at 11:28:46 (total: 00:00:05)
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