1 |
17 |
mihad |
-cdslib ../bin/cds.lib
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2 |
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-hdlvar ../bin/hdl.var
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3 |
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-logfile ../log/ncvlog.log
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4 |
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-update
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5 |
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-messages
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6 |
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-INCDIR ../../../bench/verilog
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7 |
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-INCDIR ../../../rtl/verilog
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8 |
106 |
mihad |
-DEFINE REGRESSION
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9 |
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-DEFINE REGR_FIFO_SMALL_GENERIC
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10 |
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-DEFINE GUEST
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11 |
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-DEFINE WB_DECODE_FAST
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12 |
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-DEFINE PCI_DECODE_MAX
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13 |
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-DEFINE WB_DECODE_MED
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14 |
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-DEFINE PCI66
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15 |
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-DEFINE WB_CLK66
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16 |
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-DEFINE ACTIVE_HIGH_OE
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17 |
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-DEFINE WB_CNF_BASE_ZERO
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18 |
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-DEFINE NO_CNF_IMAGE
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19 |
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-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2
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20 |
17 |
mihad |
../../../rtl/verilog/pci_parity_check.v
|
21 |
|
|
../../../rtl/verilog/pci_target_unit.v
|
22 |
92 |
mihad |
../../../rtl/verilog/pci_wb_addr_mux.v
|
23 |
|
|
../../../rtl/verilog/pci_cbe_en_crit.v
|
24 |
|
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../../../rtl/verilog/pci_pcir_fifo_control.v
|
25 |
|
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../../../rtl/verilog/pci_out_reg.v
|
26 |
|
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../../../rtl/verilog/pci_pci_tpram.v
|
27 |
|
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../../../rtl/verilog/pci_wb_master.v
|
28 |
|
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../../../rtl/verilog/pci_conf_cyc_addr_dec.v
|
29 |
|
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../../../rtl/verilog/pci_frame_crit.v
|
30 |
17 |
mihad |
../../../rtl/verilog/pci_target32_clk_en.v
|
31 |
92 |
mihad |
../../../rtl/verilog/pci_pciw_fifo_control.v
|
32 |
|
|
../../../rtl/verilog/pci_wb_slave.v
|
33 |
|
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../../../rtl/verilog/pci_conf_space.v
|
34 |
|
|
../../../rtl/verilog/pci_frame_en_crit.v
|
35 |
|
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../../../rtl/verilog/pci_par_crit.v
|
36 |
|
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../../../rtl/verilog/pci_pciw_pcir_fifos.v
|
37 |
|
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../../../rtl/verilog/pci_wb_slave_unit.v
|
38 |
|
|
../../../rtl/verilog/pci_frame_load_crit.v
|
39 |
17 |
mihad |
../../../rtl/verilog/pci_bridge32.v
|
40 |
|
|
../../../rtl/verilog/pci_target32_devs_crit.v
|
41 |
92 |
mihad |
../../../rtl/verilog/pci_perr_crit.v
|
42 |
|
|
../../../rtl/verilog/pci_wbr_fifo_control.v
|
43 |
|
|
../../../rtl/verilog/pci_cur_out_reg.v
|
44 |
|
|
../../../rtl/verilog/pci_pci_decoder.v
|
45 |
17 |
mihad |
../../../rtl/verilog/pci_target32_interface.v
|
46 |
92 |
mihad |
../../../rtl/verilog/pci_perr_en_crit.v
|
47 |
|
|
../../../rtl/verilog/pci_wbw_fifo_control.v
|
48 |
|
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../../../rtl/verilog/pci_wb_decoder.v
|
49 |
17 |
mihad |
../../../rtl/verilog/pci_in_reg.v
|
50 |
92 |
mihad |
../../../rtl/verilog/pci_serr_crit.v
|
51 |
|
|
../../../rtl/verilog/pci_wbw_wbr_fifos.v
|
52 |
|
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../../../rtl/verilog/pci_delayed_sync.v
|
53 |
|
|
../../../rtl/verilog/pci_irdy_out_crit.v
|
54 |
17 |
mihad |
../../../rtl/verilog/pci_io_mux.v
|
55 |
|
|
../../../rtl/verilog/pci_io_mux_ad_en_crit.v
|
56 |
|
|
../../../rtl/verilog/pci_io_mux_ad_load_crit.v
|
57 |
|
|
../../../rtl/verilog/pci_target32_sm.v
|
58 |
92 |
mihad |
../../../rtl/verilog/pci_serr_en_crit.v
|
59 |
|
|
../../../rtl/verilog/pci_delayed_write_reg.v
|
60 |
|
|
../../../rtl/verilog/pci_mas_ad_en_crit.v
|
61 |
|
|
../../../rtl/verilog/pci_mas_ad_load_crit.v
|
62 |
17 |
mihad |
../../../rtl/verilog/pci_master32_sm.v
|
63 |
|
|
../../../rtl/verilog/pci_target32_stop_crit.v
|
64 |
124 |
tadejm |
../../../rtl/verilog/pci_synchronizer_flop.v
|
65 |
92 |
mihad |
../../../rtl/verilog/pci_async_reset_flop.v
|
66 |
|
|
../../../rtl/verilog/pci_mas_ch_state_crit.v
|
67 |
17 |
mihad |
../../../rtl/verilog/pci_master32_sm_if.v
|
68 |
|
|
../../../rtl/verilog/pci_target32_trdy_crit.v
|
69 |
|
|
../../../rtl/verilog/top.v
|
70 |
|
|
../../../rtl/verilog/pci_rst_int.v
|
71 |
92 |
mihad |
../../../rtl/verilog/pci_sync_module.v
|
72 |
|
|
../../../rtl/verilog/pci_wb_tpram.v
|
73 |
106 |
mihad |
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v
|
74 |
17 |
mihad |
../../../bench/verilog/wb_master32.v
|
75 |
|
|
../../../bench/verilog/wb_master_behavioral.v
|
76 |
|
|
../../../bench/verilog/system.v
|
77 |
|
|
../../../bench/verilog/pci_blue_arbiter.v
|
78 |
|
|
../../../bench/verilog/pci_bus_monitor.v
|
79 |
|
|
../../../bench/verilog/pci_behaviorial_device.v
|
80 |
|
|
../../../bench/verilog/pci_behaviorial_master.v
|
81 |
|
|
../../../bench/verilog/pci_behaviorial_target.v
|
82 |
|
|
../../../bench/verilog/wb_slave_behavioral.v
|
83 |
|
|
../../../bench/verilog/wb_bus_mon.v
|
84 |
|
|
../../../bench/verilog/pci_unsupported_commands_master.v
|
85 |
92 |
mihad |
../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
|