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17 |
mihad |
-cdslib ../bin/cds.lib
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-hdlvar ../bin/hdl.var
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-logfile ../log/ncvlog.log
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-update
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-messages
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-INCDIR ../../../bench/verilog
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-INCDIR ../../../rtl/verilog
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-DEFINE REGRESSION -DEFINE HOST -DEFINE REGR_FIFO_SMALL_GENERIC -DEFINE WB_DECODE_FAST -DEFINE PCI_DECODE_MAX -DEFINE WB_DECODE_MIN -DEFINE PCI33 -DEFINE WB_CLK10 -DEFINE ACTIVE_LOW_OE -DEFINE REGISTER_WBM_OUTPUTS -DEFINE REGISTER_WBS_OUTPUTS -DEFINE ADDR_TRAN_IMPL -DEFINE WB_RETRY_MAX -DEFINE PCI_IMAGE0 -DEFINE PCI_IMAGE2
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| 9 |
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../../../rtl/verilog/pci_parity_check.v
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| 10 |
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../../../rtl/verilog/pci_target_unit.v
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| 11 |
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../../../rtl/verilog/wb_addr_mux.v
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| 12 |
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../../../rtl/verilog/cbe_en_crit.v
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| 13 |
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../../../rtl/verilog/fifo_control.v
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| 14 |
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../../../rtl/verilog/out_reg.v
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| 15 |
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../../../rtl/verilog/pci_tpram.v
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| 16 |
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../../../rtl/verilog/wb_master.v
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| 17 |
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../../../rtl/verilog/conf_cyc_addr_dec.v
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| 18 |
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../../../rtl/verilog/frame_crit.v
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| 19 |
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../../../rtl/verilog/pci_target32_clk_en.v
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| 20 |
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../../../rtl/verilog/pciw_fifo_control.v
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| 21 |
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../../../rtl/verilog/wb_slave.v
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| 22 |
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../../../rtl/verilog/conf_space.v
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| 23 |
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../../../rtl/verilog/frame_en_crit.v
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| 24 |
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../../../rtl/verilog/par_crit.v
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| 25 |
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../../../rtl/verilog/pciw_pcir_fifos.v
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| 26 |
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../../../rtl/verilog/wb_slave_unit.v
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| 27 |
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../../../rtl/verilog/frame_load_crit.v
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| 28 |
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../../../rtl/verilog/pci_bridge32.v
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| 29 |
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../../../rtl/verilog/pci_target32_devs_crit.v
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| 30 |
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../../../rtl/verilog/perr_crit.v
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| 31 |
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../../../rtl/verilog/wbr_fifo_control.v
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| 32 |
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../../../rtl/verilog/cur_out_reg.v
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| 33 |
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../../../rtl/verilog/pci_decoder.v
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| 34 |
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../../../rtl/verilog/pci_target32_interface.v
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| 35 |
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../../../rtl/verilog/perr_en_crit.v
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| 36 |
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../../../rtl/verilog/wbw_fifo_control.v
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| 37 |
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../../../rtl/verilog/decoder.v
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| 38 |
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../../../rtl/verilog/pci_in_reg.v
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| 39 |
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../../../rtl/verilog/serr_crit.v
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| 40 |
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../../../rtl/verilog/wbw_wbr_fifos.v
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| 41 |
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../../../rtl/verilog/delayed_sync.v
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| 42 |
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../../../rtl/verilog/irdy_out_crit.v
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| 43 |
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../../../rtl/verilog/pci_io_mux.v
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| 44 |
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../../../rtl/verilog/pci_io_mux_ad_en_crit.v
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| 45 |
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../../../rtl/verilog/pci_io_mux_ad_load_crit.v
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| 46 |
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../../../rtl/verilog/pci_target32_sm.v
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| 47 |
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../../../rtl/verilog/serr_en_crit.v
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| 48 |
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../../../rtl/verilog/delayed_write_reg.v
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| 49 |
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../../../rtl/verilog/mas_ad_en_crit.v
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| 50 |
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../../../rtl/verilog/mas_ad_load_crit.v
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| 51 |
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../../../rtl/verilog/pci_master32_sm.v
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| 52 |
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../../../rtl/verilog/pci_target32_stop_crit.v
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| 53 |
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../../../rtl/verilog/synchronizer_flop.v
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| 54 |
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../../../rtl/verilog/async_reset_flop.v
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| 55 |
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../../../rtl/verilog/mas_ch_state_crit.v
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| 56 |
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../../../rtl/verilog/pci_master32_sm_if.v
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| 57 |
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../../../rtl/verilog/pci_target32_trdy_crit.v
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| 58 |
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../../../rtl/verilog/top.v
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| 59 |
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../../../rtl/verilog/pci_rst_int.v
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| 60 |
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../../../rtl/verilog/sync_module.v
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| 61 |
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../../../rtl/verilog/wb_tpram.v
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| 62 |
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../../../bench/verilog/wb_master32.v
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| 63 |
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../../../bench/verilog/wb_master_behavioral.v
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| 64 |
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../../../bench/verilog/system.v
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| 65 |
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../../../bench/verilog/pci_blue_arbiter.v
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| 66 |
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../../../bench/verilog/pci_bus_monitor.v
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| 67 |
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../../../bench/verilog/pci_behaviorial_device.v
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| 68 |
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../../../bench/verilog/pci_behaviorial_master.v
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| 69 |
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../../../bench/verilog/pci_behaviorial_target.v
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| 70 |
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../../../bench/verilog/wb_slave_behavioral.v
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| 71 |
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../../../bench/verilog/wb_bus_mon.v
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| 72 |
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../../../bench/verilog/pci_behavioral_iack_target.v
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| 73 |
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../../../bench/verilog/pci_unsupported_commands_master.v
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