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Subversion Repositories pci

[/] [pci/] [tags/] [rel_12/] [syn/] [scr/] [cons_wb_ports.inc] - Blame information for rev 154

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Line No. Rev Author Line
1 18 mihad 
set_input_delay -max 2 -clock WB_CLK {SDAT_I}
2 
set_input_delay -max 2 -clock WB_CLK {ADR_I}
3 
set_input_delay -max 2 -clock WB_CLK {SDAT_I}
4 
set_input_delay -max 2 -clock WB_CLK {SEL_I}
5 
set_input_delay -max 2 -clock WB_CLK {CYC_I}
6 
set_input_delay -max 2 -clock WB_CLK {STB_I}
7 
set_input_delay -max 2 -clock WB_CLK {CAB_I}
8 
set_input_delay -max 2 -clock WB_CLK {WE_I}
9 
 
10 
set_input_delay -max 2 -clock WB_CLK {MDAT_I}
11 
set_input_delay -max 2 -clock WB_CLK {ACK_I}
12 
set_input_delay -max 2 -clock WB_CLK {ERR_I}
13 
set_input_delay -max 2 -clock WB_CLK {RTY_I}
14 
 
15 
set_output_delay -max 2 -clock WB_CLK {SDAT_O}
16 
set_output_delay -max 2 -clock WB_CLK {MDAT_O}
17 
set_output_delay -max 2 -clock WB_CLK {ADR_O}
18 
set_output_delay -max 2 -clock WB_CLK {ACK_O}
19 
set_output_delay -max 2 -clock WB_CLK {ERR_O}
20 
set_output_delay -max 2 -clock WB_CLK {RTY_O}
21 
set_output_delay -max 2 -clock WB_CLK {CYC_O}
22 
set_output_delay -max 2 -clock WB_CLK {CAB_O}
23 
set_output_delay -max 2 -clock WB_CLK {WE_O}
24 
set_output_delay -max 2 -clock WB_CLK {STB_O}

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