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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "delayed_sync.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.4 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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//
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mihad |
// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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mihad |
// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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mihad |
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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mihad |
//
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mihad |
//
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mihad |
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// module provides synchronization mechanism between requesting and completing side of the bridge
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mihad |
`include "pci_constants.v"
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mihad |
`include "bus_commands.v"
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mihad |
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// synopsys translate_off
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mihad |
`include "timescale.v"
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mihad |
// synopsys translate_on
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mihad |
module DELAYED_SYNC
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(
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reset_in,
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req_clk_in,
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comp_clk_in,
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req_in,
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comp_in,
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done_in,
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in_progress_in,
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comp_req_pending_out,
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req_req_pending_out,
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req_comp_pending_out,
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comp_comp_pending_out,
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addr_in,
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mihad |
be_in,
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mihad |
addr_out,
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mihad |
be_out,
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mihad |
we_in,
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we_out,
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bc_in,
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bc_out,
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status_in,
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status_out,
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comp_flush_out,
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burst_in,
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burst_out,
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retry_expired_in
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);
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// system inputs
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input reset_in, // reset input
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req_clk_in, // requesting clock input
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comp_clk_in ; // completing clock input
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// request, completion, done and in progress indication inputs
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input req_in, // request qualifier - when 1 it indicates that valid request data is provided on inputs
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comp_in, // completion qualifier - when 1, completing side indicates that request has completed
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done_in, // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus
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in_progress_in ; // in progress indicator - indicates that current completion is in progress on requesting side of the bridge
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// pending indication outputs
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output comp_req_pending_out, // completion side request output - resynchronized from requesting clock to completing clock
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req_req_pending_out, // request pending output for requesting side
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req_comp_pending_out, // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus
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comp_comp_pending_out ; // completion pending output for completing side of the bridge
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// additional signals and wires for clock domain passage of signals
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mihad |
reg comp_req_pending,
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req_req_pending,
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req_comp_pending,
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req_comp_pending_sample,
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mihad |
comp_comp_pending,
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req_done_reg,
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comp_done_reg_main,
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comp_done_reg_clr,
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req_rty_exp_reg,
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req_rty_exp_clr,
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comp_rty_exp_reg,
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comp_rty_exp_clr ;
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mihad |
wire sync_comp_req_pending,
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mihad |
sync_req_comp_pending,
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sync_comp_done,
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sync_req_rty_exp,
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mihad |
sync_comp_rty_exp_clr ;
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mihad |
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// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides
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// all signals that identify requests are stored in this module
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input [31:0] addr_in ; // address bus input
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input [3:0] be_in ; // byte enable input
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input we_in ; // write enable input - read/write request indication 1 = write request / 0 = read request
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input [3:0] bc_in ; // bus command input
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input burst_in ; // burst indicator - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer
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// common request outputs used both by completing and requesting sides
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// this outputs are not resynchronized, since flags determine the request status
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output [31:0] addr_out ;
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output [3:0] be_out ;
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output we_out ;
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output [3:0] bc_out ;
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output burst_out ;
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// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
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mihad |
input status_in ;
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mihad |
output status_out ;
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// input signals that delayed transaction has been retried for max number of times
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// on this signal request is ditched, otherwise it would cause a deadlock
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mihad |
// requestor can issue another request and procedure will be repeated
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mihad |
input retry_expired_in ;
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// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data
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output comp_flush_out ;
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// output registers for common signals
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reg [31:0] addr_out ;
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reg [3:0] be_out ;
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reg we_out ;
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reg [3:0] bc_out ;
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reg burst_out ;
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// delayed transaction information is stored only when request is issued and request nor completion are pending
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wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;
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always@(posedge req_clk_in or posedge reset_in)
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begin
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if (reset_in)
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begin
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addr_out <= #`FF_DELAY 32'h0000_0000 ;
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be_out <= #`FF_DELAY 4'h0 ;
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we_out <= #`FF_DELAY 1'b0 ;
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bc_out <= #`FF_DELAY `BC_RESERVED0 ;
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burst_out <= #`FF_DELAY 1'b0 ;
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end
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else
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if (new_request)
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begin
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addr_out <= #`FF_DELAY addr_in ;
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be_out <= #`FF_DELAY be_in ;
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we_out <= #`FF_DELAY we_in ;
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bc_out <= #`FF_DELAY bc_in ;
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burst_out <= #`FF_DELAY burst_in ;
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end
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end
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// completion pending cycle counter
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reg [16:0] comp_cycle_count ;
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/*=================================================================================================================================
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Passing of requests between clock domains:
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request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain
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=================================================================================================================================*/
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// main request flip-flop triggered on requesting side's clock
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// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge
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wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ;
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always@(posedge req_clk_in or posedge reset_in)
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begin
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if ( reset_in )
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req_req_pending <= #`FF_DELAY 1'b0 ;
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mihad |
else
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2 |
mihad |
if ( req_req_clear )
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req_req_pending <= #`FF_DELAY 1'b0 ;
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mihad |
else
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mihad |
if ( req_in )
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req_req_pending <= #`FF_DELAY 1'b1 ;
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end
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// interemediate stage request synchronization flip - flop - this one is prone to metastability
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// and should have setup and hold times disabled during simulation
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synchronizer_flop req_sync
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(
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mihad |
.data_in (req_req_pending),
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.clk_out (comp_clk_in),
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.sync_data_out (sync_comp_req_pending),
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2 |
mihad |
.async_reset (reset_in)
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) ;
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// wire for clearing completion side request flag - whenever completion or retry expired are signalled
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wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ;
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// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active
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wire comp_req_pending_ena = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;
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// completion side request flip flop - gets a value from intermediate stage sync flip flop
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always@(posedge comp_clk_in or posedge reset_in)
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begin
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if ( reset_in )
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comp_req_pending <= #`FF_DELAY 1'b0 ;
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else
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if ( comp_req_pending_clear )
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comp_req_pending <= #`FF_DELAY 1'b0 ;
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else
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if ( comp_req_pending_ena )
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comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
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end
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// completion side request output assignment - when request ff is set and completion ff is not set
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assign comp_req_pending_out = comp_req_pending ;
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// requesting side request pending output
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assign req_req_pending_out = req_req_pending ;
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/*=================================================================================================================================
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Passing of completions between clock domains:
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completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
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=================================================================================================================================*/
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// main completion Flip - Flop - triggered by completing side's clock
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// completion side completion pending flag is cleared when done flag propagates through clock domains
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wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;
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always@(posedge comp_clk_in or posedge reset_in)
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begin
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257 |
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if ( reset_in )
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258 |
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comp_comp_pending <= #`FF_DELAY 1'b0 ;
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else
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if ( comp_comp_clear )
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comp_comp_pending <= #`FF_DELAY 1'b0 ;
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else
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263 |
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if ( comp_in && comp_req_pending )
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comp_comp_pending <= #`FF_DELAY 1'b1 ;
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end
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266 |
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267 |
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assign comp_comp_pending_out = comp_comp_pending ;
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268 |
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269 |
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// interemediate stage completion synchronization flip - flop - this one is prone to metastability
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270 |
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synchronizer_flop comp_sync
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271 |
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(
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272 |
21 |
mihad |
.data_in (comp_comp_pending),
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273 |
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.clk_out (req_clk_in),
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274 |
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.sync_data_out (sync_req_comp_pending),
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275 |
2 |
mihad |
.async_reset (reset_in)
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276 |
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) ;
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277 |
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278 |
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// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles
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279 |
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wire req_comp_pending_clear = done_in || comp_cycle_count[16];
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280 |
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281 |
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// request side completion pending flip flop is disabled while done flag is set
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282 |
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wire req_comp_pending_ena = ~req_done_reg ;
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283 |
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284 |
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// request side completion flip flop - gets a value from intermediate stage sync flip flop
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285 |
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always@(posedge req_clk_in or posedge reset_in)
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286 |
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begin
|
287 |
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if ( reset_in )
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288 |
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req_comp_pending <= #`FF_DELAY 1'b0 ;
|
289 |
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else
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290 |
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if ( req_comp_pending_clear )
|
291 |
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req_comp_pending <= #`FF_DELAY 1'b0 ;
|
292 |
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else
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293 |
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if ( req_comp_pending_ena )
|
294 |
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req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
|
295 |
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end
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296 |
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297 |
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// sampling FF - used for sampling incoming completion flag from completing side
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298 |
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always@(posedge req_clk_in or posedge reset_in)
|
299 |
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begin
|
300 |
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if ( reset_in )
|
301 |
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req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
|
302 |
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else
|
303 |
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req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
|
304 |
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end
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305 |
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306 |
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// requesting side completion pending output assignment
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307 |
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assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;
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308 |
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309 |
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/*==================================================================================================================================
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310 |
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Passing of delayed transaction done signal between clock domains.
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311 |
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Done is signalled by requesting side of the bridge and is passed to completing side of the bridge
|
312 |
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==================================================================================================================================*/
|
313 |
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// main done flip-flop triggered on requesting side's clock
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314 |
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// when completing side removes completion flag, done flag is also removed, so requests can proceede
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315 |
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wire req_done_clear = ~req_comp_pending_sample ;
|
316 |
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always@(posedge req_clk_in or posedge reset_in)
|
317 |
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begin
|
318 |
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if ( reset_in )
|
319 |
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req_done_reg <= #`FF_DELAY 1'b0 ;
|
320 |
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else
|
321 |
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if ( req_done_clear )
|
322 |
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req_done_reg <= #`FF_DELAY 1'b0 ;
|
323 |
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else
|
324 |
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if ( done_in || comp_cycle_count[16] )
|
325 |
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req_done_reg <= #`FF_DELAY 1'b1 ;
|
326 |
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end
|
327 |
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|
328 |
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synchronizer_flop done_sync
|
329 |
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(
|
330 |
21 |
mihad |
.data_in (req_done_reg),
|
331 |
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.clk_out (comp_clk_in),
|
332 |
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.sync_data_out (sync_comp_done),
|
333 |
2 |
mihad |
.async_reset (reset_in)
|
334 |
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) ;
|
335 |
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|
336 |
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always@(posedge comp_clk_in or posedge reset_in)
|
337 |
|
|
begin
|
338 |
|
|
if ( reset_in )
|
339 |
|
|
comp_done_reg_main <= #`FF_DELAY 1'b0 ;
|
340 |
|
|
else
|
341 |
|
|
comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
|
342 |
|
|
end
|
343 |
|
|
|
344 |
|
|
always@(posedge comp_clk_in or posedge reset_in)
|
345 |
|
|
begin
|
346 |
|
|
if ( reset_in )
|
347 |
|
|
comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
|
348 |
|
|
else
|
349 |
|
|
comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
|
350 |
|
|
end
|
351 |
|
|
|
352 |
|
|
/*=================================================================================================================================
|
353 |
|
|
Passing of retry expired signal between clock domains
|
354 |
|
|
Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
|
355 |
|
|
=================================================================================================================================*/
|
356 |
|
|
// main retry expired Flip - Flop - triggered by completing side's clock
|
357 |
|
|
wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;
|
358 |
|
|
|
359 |
|
|
// retry expired is a special case of transaction removal - retry expired propagates from completing
|
360 |
|
|
// clock domain to requesting clock domain to remove all pending requests and than propagates back
|
361 |
|
|
// to completing side to qualify valid new requests
|
362 |
|
|
|
363 |
|
|
always@(posedge comp_clk_in or posedge reset_in)
|
364 |
|
|
begin
|
365 |
|
|
if ( reset_in )
|
366 |
|
|
comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
|
367 |
|
|
else
|
368 |
|
|
if ( comp_rty_exp_clear )
|
369 |
|
|
comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
|
370 |
|
|
else
|
371 |
|
|
if ( retry_expired_in && comp_req_pending)
|
372 |
|
|
comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
|
373 |
|
|
end
|
374 |
|
|
|
375 |
|
|
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability
|
376 |
|
|
synchronizer_flop rty_exp_sync
|
377 |
|
|
(
|
378 |
21 |
mihad |
.data_in (comp_rty_exp_reg),
|
379 |
|
|
.clk_out (req_clk_in),
|
380 |
|
|
.sync_data_out (sync_req_rty_exp),
|
381 |
2 |
mihad |
.async_reset (reset_in)
|
382 |
|
|
) ;
|
383 |
|
|
|
384 |
|
|
// request retry expired flip flop - gets a value from intermediate stage sync flip flop
|
385 |
|
|
always@(posedge req_clk_in or posedge reset_in)
|
386 |
|
|
begin
|
387 |
|
|
if ( reset_in )
|
388 |
|
|
req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
|
389 |
|
|
else
|
390 |
|
|
req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
|
391 |
|
|
end
|
392 |
|
|
|
393 |
|
|
always@(posedge req_clk_in or posedge reset_in)
|
394 |
|
|
begin
|
395 |
|
|
if ( reset_in )
|
396 |
|
|
req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
|
397 |
|
|
else
|
398 |
|
|
req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
|
399 |
|
|
end
|
400 |
|
|
|
401 |
|
|
synchronizer_flop rty_exp_back_prop_sync
|
402 |
|
|
(
|
403 |
33 |
mihad |
.data_in (req_rty_exp_reg && req_rty_exp_clr),
|
404 |
21 |
mihad |
.clk_out (comp_clk_in),
|
405 |
|
|
.sync_data_out (sync_comp_rty_exp_clr),
|
406 |
2 |
mihad |
.async_reset (reset_in)
|
407 |
|
|
) ;
|
408 |
|
|
|
409 |
|
|
always@(posedge comp_clk_in or posedge reset_in)
|
410 |
|
|
begin
|
411 |
|
|
if ( reset_in )
|
412 |
|
|
comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
|
413 |
|
|
else
|
414 |
|
|
comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
|
415 |
|
|
end
|
416 |
|
|
|
417 |
|
|
// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error
|
418 |
|
|
reg status_out ;
|
419 |
21 |
mihad |
always@(posedge comp_clk_in or posedge reset_in)
|
420 |
2 |
mihad |
begin
|
421 |
|
|
if (reset_in)
|
422 |
|
|
status_out <= #`FF_DELAY 1'b0 ;
|
423 |
|
|
else
|
424 |
|
|
if (comp_in && comp_req_pending)
|
425 |
|
|
status_out <= #`FF_DELAY status_in ;
|
426 |
|
|
end
|
427 |
|
|
|
428 |
|
|
// clocks counter - it counts how many clock cycles completion is present without beeing repeated
|
429 |
|
|
// if it counts to 2^^16 cycles the completion must be ditched
|
430 |
|
|
|
431 |
|
|
// wire for clearing this counter
|
432 |
57 |
mihad |
wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ;
|
433 |
2 |
mihad |
always@(posedge req_clk_in or posedge reset_in)
|
434 |
|
|
begin
|
435 |
|
|
if (reset_in)
|
436 |
|
|
comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
|
437 |
|
|
else
|
438 |
|
|
if (clear_count)
|
439 |
|
|
comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
|
440 |
|
|
else
|
441 |
|
|
comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
|
442 |
|
|
end
|
443 |
|
|
|
444 |
|
|
// completion flush output - used for flushing fifos when counter expires
|
445 |
|
|
// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines
|
446 |
|
|
reg comp_flush_out ;
|
447 |
|
|
always@(posedge req_clk_in or posedge reset_in)
|
448 |
|
|
begin
|
449 |
|
|
if (reset_in)
|
450 |
|
|
comp_flush_out <= #`FF_DELAY 1'b0 ;
|
451 |
|
|
else
|
452 |
|
|
comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
|
453 |
|
|
end
|
454 |
|
|
|
455 |
|
|
endmodule //delayed_sync
|