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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "fifo_control.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.6 2002/09/30 16:03:04 mihad
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// Added meta flop module for easier meta stable FF identification during synthesis
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//
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mihad |
// Revision 1.5 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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//
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mihad |
// Revision 1.4 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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//
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mihad |
// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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mihad |
// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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mihad |
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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mihad |
//
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mihad |
//
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mihad |
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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mihad |
`include "pci_constants.v"
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mihad |
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mihad |
// synopsys translate_off
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mihad |
`include "timescale.v"
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mihad |
// synopsys translate_on
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mihad |
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mihad |
module FIFO_CONTROL
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(
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mihad |
rclock_in,
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wclock_in,
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renable_in,
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wenable_in,
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reset_in,
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flush_in,
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full_out,
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almost_empty_out,
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empty_out,
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waddr_out,
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raddr_out,
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rallow_out,
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mihad |
wallow_out
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);
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// address length parameter - depends on fifo depth
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parameter ADDR_LENGTH = 7 ;
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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input rclock_in, wclock_in;
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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input renable_in, wenable_in;
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// reset input
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input reset_in;
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// flush input
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input flush_in ;
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mihad |
// almost empy status output
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output almost_empty_out;
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2 |
mihad |
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// full and empty status outputs
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output full_out, empty_out;
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// read and write addresses outputs
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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// read and write allow outputs
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output rallow_out, wallow_out ;
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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// grey code registers
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // one before current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next grey coded write address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FFs for registered empty and full flags
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mihad |
wire empty ;
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wire full ;
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2 |
mihad |
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mihad |
// almost_empty tag
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mihad |
wire almost_empty ;
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2 |
mihad |
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// write allow wire - writes are allowed when fifo is not full
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mihad |
wire wallow = wenable_in && !full ;
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2 |
mihad |
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// write allow output assignment
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assign wallow_out = wallow ;
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// read allow wire
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wire rallow ;
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// full output assignment
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assign full_out = full ;
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// clear generation for FFs and registers
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mihad |
wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
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2 |
mihad |
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mihad |
reg wclock_nempty_detect ;
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mihad |
always@(posedge clear or posedge wclock_in)
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mihad |
begin
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mihad |
if (clear)
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mihad |
wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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else
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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end
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2 |
mihad |
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mihad |
wire stretched_empty ;
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2 |
mihad |
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mihad |
wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
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meta_flop #(1) i_meta_flop_stretched_empty
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(
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.rst_i (clear),
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.clk_i (rclock_in),
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.ld_i (1'b0),
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.ld_val_i (1'b0),
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.en_i (1'b1),
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.d_i (stretched_empty_flop_i),
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.meta_q_o (stretched_empty)
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) ;
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21 |
mihad |
// empty output is actual empty + 1 read clock cycle ( stretched empty )
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assign empty_out = empty || stretched_empty ;
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2 |
mihad |
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21 |
mihad |
//rallow generation
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mihad |
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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2 |
mihad |
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21 |
mihad |
// rallow output assignment
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assign rallow_out = rallow ;
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2 |
mihad |
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21 |
mihad |
// almost empty output assignment
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59 |
mihad |
assign almost_empty_out = almost_empty && !empty && !stretched_empty ;
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2 |
mihad |
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21 |
mihad |
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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2 |
mihad |
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21 |
mihad |
// address output mux - when FIFO is not read, current actual address is driven out, when it is read, next address is driven out to provide
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// next data immediately
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// done for zero wait state burst operation
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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2 |
mihad |
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21 |
mihad |
always@(posedge rclock_in or posedge clear)
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begin
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if (clear)
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71 |
mihad |
begin
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// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
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33 |
mihad |
raddr_plus_one <= #`FF_DELAY 4 ;
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71 |
mihad |
raddr <= #`FF_DELAY 3 ;
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end
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58 |
mihad |
else if (flush_in)
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mihad |
begin
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mihad |
raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ;
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mihad |
raddr <= #`FF_DELAY waddr ;
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end
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21 |
mihad |
else if (rallow)
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mihad |
begin
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mihad |
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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71 |
mihad |
raddr <= #`FF_DELAY raddr_plus_one ;
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end
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21 |
mihad |
end
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2 |
mihad |
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/*-----------------------------------------------------------------------------------------------
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Read address control consists of Read address counter and Grey Address pipeline
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21 |
mihad |
There are 4 Grey addresses:
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2 |
mihad |
- rgrey_minus1 is Grey Code of address one before current address
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- rgrey_addr is Grey Code of current read address
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- rgrey_next is Grey Code of next read address
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--------------------------------------------------------------------------------------------------*/
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71 |
mihad |
// grey coded address pipeline for status generation in read clock domain
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2 |
mihad |
always@(posedge rclock_in or posedge clear)
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begin
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21 |
mihad |
if (clear)
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71 |
mihad |
begin
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33 |
mihad |
rgrey_minus1 <= #`FF_DELAY 0 ;
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71 |
mihad |
rgrey_addr <= #`FF_DELAY 1 ;
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rgrey_next <= #`FF_DELAY 3 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo
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end
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58 |
mihad |
else if (flush_in)
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71 |
mihad |
begin
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// when fifo is flushed, load the register values from the write clock domain.
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// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur.
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58 |
mihad |
rgrey_minus1 <= #`FF_DELAY wgrey_minus1 ;
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71 |
mihad |
rgrey_addr <= #`FF_DELAY wgrey_addr ;
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rgrey_next <= #`FF_DELAY wgrey_next ;
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end
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254 |
58 |
mihad |
else if (rallow)
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71 |
mihad |
begin
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256 |
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// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address
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21 |
mihad |
rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
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71 |
mihad |
rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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261 |
2 |
mihad |
end
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262 |
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263 |
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/*--------------------------------------------------------------------------------------------
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264 |
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Write address control consists of write address counter and three Grey Code Registers:
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265 |
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- wgrey_minus1 represents Grey Coded address of location one before current write address
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266 |
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- wgrey_addr represents current Grey Coded write address
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267 |
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- wgrey_next represents Grey Coded next write address
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268 |
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----------------------------------------------------------------------------------------------*/
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269 |
71 |
mihad |
// grey coded address pipeline for status generation in write clock domain
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270 |
2 |
mihad |
always@(posedge wclock_in or posedge clear)
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271 |
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begin
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272 |
21 |
mihad |
if (clear)
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273 |
2 |
mihad |
begin
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274 |
33 |
mihad |
// initial value is 0
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275 |
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wgrey_minus1 <= #`FF_DELAY 0 ;
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276 |
71 |
mihad |
wgrey_addr <= #`FF_DELAY 1 ;
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277 |
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wgrey_next <= #`FF_DELAY 3 ;
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278 |
2 |
mihad |
end
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279 |
21 |
mihad |
else
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280 |
2 |
mihad |
if (wallow)
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281 |
71 |
mihad |
begin
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282 |
21 |
mihad |
wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
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283 |
71 |
mihad |
wgrey_addr <= #`FF_DELAY wgrey_next ;
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284 |
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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285 |
2 |
mihad |
end
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286 |
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end
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287 |
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288 |
71 |
mihad |
// write address binary counter - nothing special except initial value
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289 |
2 |
mihad |
always@(posedge wclock_in or posedge clear)
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290 |
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begin
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291 |
21 |
mihad |
if (clear)
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292 |
33 |
mihad |
// initial value 3
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293 |
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waddr <= #`FF_DELAY 3 ;
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294 |
21 |
mihad |
else
|
295 |
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if (wallow)
|
296 |
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waddr <= #`FF_DELAY waddr + 1'b1 ;
|
297 |
2 |
mihad |
end
|
298 |
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|
299 |
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/*------------------------------------------------------------------------------------------------------------------------------
|
300 |
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Registered full control:
|
301 |
21 |
mihad |
registered full is set on rising edge of wclock_in, when fifo is almost full and something gets written to it.
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302 |
2 |
mihad |
It's kept high until something is read from FIFO, which is registered on next rising write clock edge.
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303 |
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|
304 |
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Registered almost full control:
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305 |
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Almost full flag is set on rising write clock edge whenever two free locations are left in fifo and another entry is written to it.
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306 |
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It remains set if nothing is read/written from/to fifo. All operations are synchronized on write clock.
|
307 |
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--------------------------------------------------------------------------------------------------------------------------------*/
|
308 |
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wire comb_full = wgrey_next == rgrey_addr ;
|
309 |
33 |
mihad |
wire comb_almost_full = wgrey_next == rgrey_minus1 ;
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310 |
2 |
mihad |
|
311 |
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//combinatorial input to Registered full FlipFlop
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312 |
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wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
|
313 |
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|
314 |
59 |
mihad |
meta_flop #(0) i_meta_flop_full
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315 |
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(
|
316 |
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.rst_i (clear),
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317 |
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.clk_i (wclock_in),
|
318 |
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.ld_i (1'b0),
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319 |
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.ld_val_i (1'b0),
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320 |
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.en_i (1'b1),
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321 |
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.d_i (reg_full),
|
322 |
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.meta_q_o (full)
|
323 |
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) ;
|
324 |
2 |
mihad |
|
325 |
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
326 |
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Registered empty control:
|
327 |
|
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registered empty is set on rising edge of rclock_in when one location is occupied and read from it. It remains set until
|
328 |
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something is written to fifo which is detected on next read clock edge.
|
329 |
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|
|
330 |
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Registered almost empty control:
|
331 |
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Almost empty is set on rising clock edge of read clock when two locations are used in fifo and one of them is read from it.
|
332 |
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It remains set until something is read/written from/to fifo. All operations are detected on rising edge of read clock.
|
333 |
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--------------------------------------------------------------------------------------------------------------------------------*/
|
334 |
|
|
wire comb_almost_empty = rgrey_next == wgrey_addr ;
|
335 |
|
|
wire comb_empty = rgrey_addr == wgrey_addr ;
|
336 |
|
|
wire comb_two_used = rgrey_next == wgrey_minus1 ;
|
337 |
|
|
|
338 |
|
|
// combinatorial input for registered emty FlipFlop
|
339 |
|
|
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
|
340 |
|
|
|
341 |
59 |
mihad |
// meta flop for empty signal instantiation - reset value 1, load value (flush) 1 etc..
|
342 |
|
|
meta_flop #(1) i_meta_flop_empty
|
343 |
|
|
(
|
344 |
|
|
.rst_i (clear),
|
345 |
|
|
.clk_i (rclock_in),
|
346 |
|
|
.ld_i (flush_in),
|
347 |
|
|
.ld_val_i (1'b1),
|
348 |
|
|
.en_i (1'b1),
|
349 |
|
|
.d_i (reg_empty),
|
350 |
|
|
.meta_q_o (empty)
|
351 |
|
|
) ;
|
352 |
2 |
mihad |
|
353 |
|
|
// input for almost empty flip flop
|
354 |
|
|
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
|
355 |
|
|
|
356 |
59 |
mihad |
meta_flop #(0) i_meta_flop_almost_empty
|
357 |
|
|
(
|
358 |
|
|
.rst_i (clear),
|
359 |
|
|
.clk_i (rclock_in),
|
360 |
|
|
.ld_i (flush_in),
|
361 |
|
|
.ld_val_i (1'b0),
|
362 |
|
|
.en_i (1'b1),
|
363 |
|
|
.d_i (reg_almost_empty),
|
364 |
|
|
.meta_q_o (almost_empty)
|
365 |
|
|
) ;
|
366 |
|
|
|
367 |
2 |
mihad |
endmodule
|