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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "meta_flop.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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// this module is just an ordinary flip-flop - used for identifying meta stable critical flip flops - similar to synchronizer flop
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module meta_flop
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(
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rst_i,
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clk_i,
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ld_i,
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ld_val_i,
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en_i,
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d_i,
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meta_q_o
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) ;
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parameter p_reset_value = 0 ;
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input rst_i,
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clk_i,
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ld_i,
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ld_val_i,
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en_i,
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d_i ;
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output meta_q_o ;
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reg meta_q_o ;
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always@(posedge rst_i or posedge clk_i)
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begin
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if (rst_i)
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meta_q_o <= #1 p_reset_value ;
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else if (ld_i)
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meta_q_o <= #1 ld_val_i ;
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else if (en_i)
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meta_q_o <= #1 d_i ;
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end
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endmodule
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