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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  File name "pci_bridge32.v"                                  ////

////                                                              ////

////  This file is part of the "PCI bridge" project               ////

////  http://www.opencores.org/cores/pci/                         ////

////                                                              ////

////  Author(s):                                                  ////

////      - Miha Dolenc (mihad@opencores.org)                     ////

////      - Tadej Markovic (tadej@opencores.org)                  ////

////                                                              ////

////  All additional information is avaliable in the README       ////

////  file.                                                       ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.4  2002/10/08 17:17:05  mihad

// Added BIST signals for RAMs.

//

// Revision 1.3  2002/02/01 15:25:12  mihad

// Repaired a few bugs, updated specification, added test bench files and design document

//

// Revision 1.2  2001/10/05 08:14:28  mihad

// Updated all files with inclusion of timescale file for simulation purposes.

//

// Revision 1.1.1.1  2001/10/02 15:33:46  mihad

// New project directory structure

//

//

`include "pci_constants.v"

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

// this is top level module of pci bridge core

// it instantiates and connects other lower level modules

// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification

module PCI_BRIDGE32

(

    // WISHBONE system signals

    CLK_I,

    RST_I,

    RST_O,

    INT_I,

    INT_O,

    // WISHBONE slave interface

    ADR_I,

    SDAT_I,

    SDAT_O,

    SEL_I,

    CYC_I,

    STB_I,

    WE_I,

    CAB_I,

    ACK_O,

    RTY_O,

    ERR_O,

    // WISHBONE master interface

    ADR_O,

    MDAT_I,

    MDAT_O,

    SEL_O,

    CYC_O,

    STB_O,

    WE_O,

    CAB_O,

    ACK_I,

    RTY_I,

    ERR_I,

    // pci interface - system pins

    PCI_CLK_IN,

    PCI_RSTn_IN,

    PCI_RSTn_OUT,

    PCI_INTAn_IN,

    PCI_INTAn_OUT,

    PCI_RSTn_EN_OUT,

    PCI_INTAn_EN_OUT,

    // arbitration pins

    PCI_REQn_OUT,

    PCI_REQn_EN_OUT,

    PCI_GNTn_IN,

    // protocol pins

    PCI_FRAMEn_IN,

    PCI_FRAMEn_OUT,

    PCI_FRAMEn_EN_OUT,

    PCI_IRDYn_EN_OUT,

    PCI_DEVSELn_EN_OUT,

    PCI_TRDYn_EN_OUT,

    PCI_STOPn_EN_OUT,

    PCI_AD_EN_OUT,

    PCI_CBEn_EN_OUT,

    PCI_IRDYn_IN,

    PCI_IRDYn_OUT,

    PCI_IDSEL_IN,

    PCI_DEVSELn_IN,

    PCI_DEVSELn_OUT,

    PCI_TRDYn_IN,

    PCI_TRDYn_OUT,

    PCI_STOPn_IN,

    PCI_STOPn_OUT,

    // data transfer pins

    PCI_AD_IN,

    PCI_AD_OUT,

    PCI_CBEn_IN,

    PCI_CBEn_OUT,

    // parity generation and checking pins

    PCI_PAR_IN,

    PCI_PAR_OUT,

    PCI_PAR_EN_OUT,

    PCI_PERRn_IN,

    PCI_PERRn_OUT,

    PCI_PERRn_EN_OUT,

    // system error pin

    PCI_SERRn_OUT,

    PCI_SERRn_EN_OUT

`ifdef PCI_BIST

    ,

    // debug chain signals

    trst       ,

    SO         ,

    SI         ,

    shift_DR   ,

    capture_DR ,

    extest     ,

    tck

`endif

);

// WISHBONE system signals

input   CLK_I ;

input   RST_I ;

output  RST_O ;

input   INT_I ;

output  INT_O ;

// WISHBONE slave interface

input   [31:0]  ADR_I ;

input   [31:0]  SDAT_I ;

output  [31:0]  SDAT_O ;

input   [3:0]   SEL_I ;

input           CYC_I ;

input           STB_I ;

input           WE_I  ;

input           CAB_I ;

output          ACK_O ;

output          RTY_O ;

output          ERR_O ;

// WISHBONE master interface

output  [31:0]  ADR_O ;

input   [31:0]  MDAT_I ;

output  [31:0]  MDAT_O ;

output  [3:0]   SEL_O ;

output          CYC_O ;

output          STB_O ;

output          WE_O  ;

output          CAB_O ;

input           ACK_I ;

input           RTY_I ;

input           ERR_I ;

// pci interface - system pins

input   PCI_CLK_IN ;

input   PCI_RSTn_IN ;

output  PCI_RSTn_OUT ;

output  PCI_RSTn_EN_OUT ;

input   PCI_INTAn_IN ;

output  PCI_INTAn_OUT ;

output  PCI_INTAn_EN_OUT ;

// arbitration pins

output  PCI_REQn_OUT ;

output  PCI_REQn_EN_OUT ;

input   PCI_GNTn_IN ;

// protocol pins

input   PCI_FRAMEn_IN ;

output  PCI_FRAMEn_OUT ;

output  PCI_FRAMEn_EN_OUT ;

output  PCI_IRDYn_EN_OUT ;

output  PCI_DEVSELn_EN_OUT ;

output  PCI_TRDYn_EN_OUT ;

output  PCI_STOPn_EN_OUT ;

output  [31:0]  PCI_AD_EN_OUT ;

output  [3:0]   PCI_CBEn_EN_OUT ;

input   PCI_IRDYn_IN ;

output  PCI_IRDYn_OUT ;

input   PCI_IDSEL_IN ;

input   PCI_DEVSELn_IN ;

output  PCI_DEVSELn_OUT ;

input   PCI_TRDYn_IN ;

output  PCI_TRDYn_OUT ;

input   PCI_STOPn_IN ;

output  PCI_STOPn_OUT ;

// data transfer pins

input   [31:0]  PCI_AD_IN ;

output  [31:0]  PCI_AD_OUT ;

input   [3:0]   PCI_CBEn_IN ;

output  [3:0]   PCI_CBEn_OUT ;

// parity generation and checking pins

input   PCI_PAR_IN ;

output  PCI_PAR_OUT ;

output  PCI_PAR_EN_OUT ;

input   PCI_PERRn_IN ;

output  PCI_PERRn_OUT ;

output  PCI_PERRn_EN_OUT ;

// system error pin

output  PCI_SERRn_OUT ;

output  PCI_SERRn_EN_OUT ;

`ifdef PCI_BIST

/*-----------------------------------------------------

BIST debug chain port signals

-----------------------------------------------------*/

input   trst ;

output  SO ;

input   SI ;

input   shift_DR ;

input   capture_DR ;

input   extest ;

input   tck ;

// internal wires for serial chain connection

wire SO_internal ;

wire SI_internal = SO_internal ;

`endif

// declare clock and reset wires

wire pci_clk = PCI_CLK_IN ;

wire wb_clk  = CLK_I ;

wire reset ; // assigned at pci bridge reset and interrupt logic

/*=========================================================================================================

First comes definition of all modules' outputs, so they can be assigned to any other module's input later

  in the file, when module is instantiated

=========================================================================================================*/

// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS

wire    pci_reso_reset ;

wire    pci_reso_pci_rstn_out ;

wire    pci_reso_pci_rstn_en_out ;

wire    pci_reso_rst_o ;

wire    pci_into_pci_intan_out ;

wire    pci_into_pci_intan_en_out ;

wire    pci_into_int_o ;

wire    pci_into_conf_isr_int_prop_out ;

// assign pci bridge reset interrupt logic outputs to top outputs where possible

assign reset            = pci_reso_reset ;

assign PCI_RSTn_OUT     = pci_reso_pci_rstn_out ;

assign PCI_RSTn_EN_OUT  = pci_reso_pci_rstn_en_out ;

assign RST_O            = pci_reso_rst_o ;

assign PCI_INTAn_OUT    = pci_into_pci_intan_out ;

assign PCI_INTAn_EN_OUT = pci_into_pci_intan_en_out ;

assign INT_O            = pci_into_int_o ;

// WISHBONE SLAVE UNIT OUTPUTS

wire    [31:0]  wbu_sdata_out ;

wire            wbu_ack_out ;

wire            wbu_rty_out ;

wire            wbu_err_out ;

wire            wbu_pciif_req_out ;

wire            wbu_pciif_frame_out ;

wire            wbu_pciif_frame_en_out ;

wire            wbu_pciif_irdy_out ;

wire            wbu_pciif_irdy_en_out ;

wire    [31:0]  wbu_pciif_ad_out ;

wire            wbu_pciif_ad_en_out ;

wire    [3:0]   wbu_pciif_cbe_out ;

wire            wbu_pciif_cbe_en_out ;

wire    [31:0]  wbu_err_addr_out ;

wire    [3:0]   wbu_err_bc_out ;

wire            wbu_err_signal_out ;

wire            wbu_err_source_out ;

wire            wbu_err_rty_exp_out ;

wire            wbu_tabort_rec_out ;

wire            wbu_mabort_rec_out ;

wire    [11:0]  wbu_conf_offset_out ;

wire            wbu_conf_renable_out ;

wire            wbu_conf_wenable_out ;

wire    [3:0]   wbu_conf_be_out ;

wire    [31:0]  wbu_conf_data_out ;

wire            wbu_del_read_comp_pending_out ;

wire            wbu_wbw_fifo_empty_out ;

wire            wbu_ad_load_out ;

wire            wbu_ad_load_on_transfer_out ;

wire            wbu_pciif_frame_load_out ;

// assign wishbone slave unit's outputs to top outputs where possible

assign SDAT_O   =   wbu_sdata_out ;

assign ACK_O    =   wbu_ack_out ;

assign RTY_O    =   wbu_rty_out ;

assign ERR_O    =   wbu_err_out ;

// PCI TARGET UNIT OUTPUTS

wire    [31:0]  pciu_adr_out ;

wire    [31:0]  pciu_mdata_out ;

wire            pciu_cyc_out ;

wire            pciu_stb_out ;

wire            pciu_we_out ;

wire    [3:0]   pciu_sel_out ;

wire            pciu_cab_out ;

wire            pciu_pciif_trdy_out ;

wire            pciu_pciif_stop_out ;

wire            pciu_pciif_devsel_out ;

wire            pciu_pciif_trdy_en_out ;

wire            pciu_pciif_stop_en_out ;

wire            pciu_pciif_devsel_en_out ;

wire            pciu_ad_load_out ;

wire            pciu_ad_load_on_transfer_out ;

wire   [31:0]   pciu_pciif_ad_out ;

wire            pciu_pciif_ad_en_out ;

wire            pciu_pciif_tabort_set_out ;

wire    [31:0]  pciu_err_addr_out ;

wire    [3:0]   pciu_err_bc_out ;

wire    [31:0]  pciu_err_data_out ;

wire    [3:0]   pciu_err_be_out ;

wire            pciu_err_signal_out ;

wire            pciu_err_source_out ;

wire            pciu_err_rty_exp_out ;

wire            pciu_conf_select_out ;

wire    [11:0]  pciu_conf_offset_out ;

wire            pciu_conf_renable_out ;

wire            pciu_conf_wenable_out ;

wire    [3:0]   pciu_conf_be_out ;

wire    [31:0]  pciu_conf_data_out ;

wire            pciu_pci_drcomp_pending_out ;

wire            pciu_pciw_fifo_empty_out ;

// assign pci target unit's outputs to top outputs where possible

assign ADR_O    =   pciu_adr_out ;

assign MDAT_O   =   pciu_mdata_out ;

assign CYC_O    =   pciu_cyc_out ;

assign STB_O    =   pciu_stb_out ;

assign WE_O     =   pciu_we_out ;

assign SEL_O    =   pciu_sel_out ;

assign CAB_O    =   pciu_cab_out ;

// CONFIGURATION SPACE OUTPUTS

wire    [31:0]  conf_w_data_out ;

wire    [31:0]  conf_r_data_out ;

wire            conf_serr_enable_out ;

wire            conf_perr_response_out ;

wire            conf_pci_master_enable_out ;

wire            conf_mem_space_enable_out ;

wire            conf_io_space_enable_out ;

wire    [7:0]   conf_cache_line_size_to_pci_out ;

wire    [7:0]   conf_cache_line_size_to_wb_out ;

wire            conf_cache_lsize_not_zero_to_wb_out ;

wire    [7:0]   conf_latency_tim_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba0_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba1_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba2_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba3_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba4_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba5_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta0_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta1_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta2_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta3_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta4_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta5_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am0_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am1_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am2_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am3_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am4_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am5_out ;

wire            conf_pci_mem_io0_out ;

wire            conf_pci_mem_io1_out ;

wire            conf_pci_mem_io2_out ;

wire            conf_pci_mem_io3_out ;

wire            conf_pci_mem_io4_out ;

wire            conf_pci_mem_io5_out ;

wire    [1:0]   conf_pci_img_ctrl0_out ;

wire    [1:0]   conf_pci_img_ctrl1_out ;

wire    [1:0]   conf_pci_img_ctrl2_out ;

wire    [1:0]   conf_pci_img_ctrl3_out ;

wire    [1:0]   conf_pci_img_ctrl4_out ;

wire    [1:0]   conf_pci_img_ctrl5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba0_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba1_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba2_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba3_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba4_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba5_out ;

wire            conf_wb_mem_io0_out ;

wire            conf_wb_mem_io1_out ;

wire            conf_wb_mem_io2_out ;

wire            conf_wb_mem_io3_out ;

wire            conf_wb_mem_io4_out ;

wire            conf_wb_mem_io5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am0_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am1_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am2_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am3_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am4_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta0_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta1_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta2_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta3_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta4_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta5_out ;

wire    [2:0]   conf_wb_img_ctrl0_out ;

wire    [2:0]   conf_wb_img_ctrl1_out ;

wire    [2:0]   conf_wb_img_ctrl2_out ;

wire    [2:0]   conf_wb_img_ctrl3_out ;

wire    [2:0]   conf_wb_img_ctrl4_out ;

wire    [2:0]   conf_wb_img_ctrl5_out ;

wire    [23:0]  conf_ccyc_addr_out ;

wire            conf_soft_res_out ;

wire            conf_int_out ;

// PCI IO MUX OUTPUTS

wire        pci_mux_frame_out ;

wire        pci_mux_irdy_out ;

wire        pci_mux_devsel_out ;

wire        pci_mux_trdy_out ;

wire        pci_mux_stop_out ;

wire [3:0]  pci_mux_cbe_out ;

wire [31:0] pci_mux_ad_out ;

wire        pci_mux_ad_load_out ;

wire [31:0] pci_mux_ad_en_out ;

wire        pci_mux_ad_en_unregistered_out ;

wire        pci_mux_frame_en_out ;

wire        pci_mux_irdy_en_out ;

wire        pci_mux_devsel_en_out ;

wire        pci_mux_trdy_en_out ;

wire        pci_mux_stop_en_out ;

wire [3:0]  pci_mux_cbe_en_out ;

wire        pci_mux_par_out ;

wire        pci_mux_par_en_out ;

wire        pci_mux_perr_out ;

wire        pci_mux_perr_en_out ;

wire        pci_mux_serr_out ;

wire        pci_mux_serr_en_out ;

wire        pci_mux_req_out ;

wire        pci_mux_req_en_out ;

// assign outputs to top level outputs

assign PCI_AD_EN_OUT       = pci_mux_ad_en_out ;

assign PCI_FRAMEn_EN_OUT   = pci_mux_frame_en_out ;

assign PCI_IRDYn_EN_OUT    = pci_mux_irdy_en_out ;

assign PCI_CBEn_EN_OUT     = pci_mux_cbe_en_out ;

assign PCI_PAR_OUT         =   pci_mux_par_out ;

assign PCI_PAR_EN_OUT      =   pci_mux_par_en_out ;

assign PCI_PERRn_OUT       =   pci_mux_perr_out ;

assign PCI_PERRn_EN_OUT    =   pci_mux_perr_en_out ;

assign PCI_SERRn_OUT       =   pci_mux_serr_out ;

assign PCI_SERRn_EN_OUT    =   pci_mux_serr_en_out ;

assign PCI_REQn_OUT        =   pci_mux_req_out ;

assign PCI_REQn_EN_OUT     =   pci_mux_req_en_out ;

assign PCI_TRDYn_EN_OUT    = pci_mux_trdy_en_out ;

assign PCI_DEVSELn_EN_OUT  = pci_mux_devsel_en_out ;

assign PCI_STOPn_EN_OUT    = pci_mux_stop_en_out ;

assign PCI_TRDYn_OUT       =  pci_mux_trdy_out ;

assign PCI_DEVSELn_OUT     = pci_mux_devsel_out ;

assign PCI_STOPn_OUT       = pci_mux_stop_out ;

assign PCI_AD_OUT          = pci_mux_ad_out ;

assign PCI_FRAMEn_OUT      = pci_mux_frame_out ;

assign PCI_IRDYn_OUT       = pci_mux_irdy_out ;

assign PCI_CBEn_OUT        = pci_mux_cbe_out ;

// duplicate output register's outputs

wire            out_bckp_frame_out ;

wire            out_bckp_irdy_out ;

wire            out_bckp_devsel_out ;

wire            out_bckp_trdy_out ;

wire            out_bckp_stop_out ;

wire    [3:0]   out_bckp_cbe_out ;

wire            out_bckp_cbe_en_out ;

wire    [31:0]  out_bckp_ad_out ;

wire            out_bckp_ad_en_out ;

wire            out_bckp_irdy_en_out ;

wire            out_bckp_frame_en_out ;

wire            out_bckp_tar_ad_en_out ;

wire            out_bckp_mas_ad_en_out ;

wire            out_bckp_trdy_en_out ;

wire            out_bckp_par_out ;

wire            out_bckp_par_en_out ;

wire            out_bckp_perr_out ;

wire            out_bckp_perr_en_out ;

wire            out_bckp_serr_out ;

wire            out_bckp_serr_en_out ;

// PARITY CHECKER OUTPUTS

wire    parchk_pci_par_out ;

wire    parchk_pci_par_en_out ;

wire    parchk_pci_perr_out ;

wire    parchk_pci_perr_en_out ;

wire    parchk_pci_serr_out ;

wire    parchk_pci_serr_en_out ;

wire    parchk_par_err_detect_out ;

wire    parchk_perr_mas_detect_out ;

wire    parchk_sig_serr_out ;

// input register outputs

wire            in_reg_gnt_out ;

wire            in_reg_frame_out ;

wire            in_reg_irdy_out ;

wire            in_reg_trdy_out ;

wire            in_reg_stop_out ;

wire            in_reg_devsel_out ;

wire            in_reg_idsel_out ;

wire    [31:0]  in_reg_ad_out ;

wire    [3:0]   in_reg_cbe_out ;

/*=========================================================================================================

Now comes definition of all modules' and their appropriate inputs

=========================================================================================================*/

// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS

wire    pci_resi_rst_i                  = RST_I ;

wire    pci_resi_pci_rstn_in            = PCI_RSTn_IN ;

wire    pci_resi_conf_soft_res_in       = conf_soft_res_out ;

wire    pci_inti_pci_intan_in           = PCI_INTAn_IN ;

wire    pci_inti_conf_int_in            = conf_int_out ;

wire    pci_inti_int_i                  = INT_I ;

wire    pci_inti_out_bckp_perr_en_in    = out_bckp_perr_en_out ;

wire    pci_inti_out_bckp_serr_en_in    = out_bckp_serr_en_out ;

PCI_RST_INT     pci_resets_and_interrupts

(

    .clk_in                 (pci_clk),

    .rst_i                  (pci_resi_rst_i),

    .pci_rstn_in            (pci_resi_pci_rstn_in),

    .conf_soft_res_in       (pci_resi_conf_soft_res_in),

    .reset                  (pci_reso_reset),

    .pci_rstn_out           (pci_reso_pci_rstn_out),

    .pci_rstn_en_out        (pci_reso_pci_rstn_en_out),

    .rst_o                  (pci_reso_rst_o),

    .pci_intan_in           (pci_inti_pci_intan_in),

    .conf_int_in            (pci_inti_conf_int_in),

    .int_i                  (pci_inti_int_i),

    .out_bckp_perr_en_in    (pci_inti_out_bckp_perr_en_in),

    .out_bckp_serr_en_in    (pci_inti_out_bckp_serr_en_in),

    .pci_intan_out          (pci_into_pci_intan_out),

    .pci_intan_en_out       (pci_into_pci_intan_en_out),

    .int_o                  (pci_into_int_o),

    .conf_isr_int_prop_out  (pci_into_conf_isr_int_prop_out)

);

// WISHBONE SLAVE UNIT INPUTS

wire    [31:0]  wbu_addr_in                     =   ADR_I ;

wire    [31:0]  wbu_sdata_in                    =   SDAT_I ;

wire            wbu_cyc_in                      =   CYC_I ;

wire            wbu_stb_in                      =   STB_I ;

wire            wbu_we_in                       =   WE_I ;

wire    [3:0]   wbu_sel_in                      =   SEL_I ;

wire            wbu_cab_in                      =   CAB_I ;

wire    [5:0]   wbu_map_in                      =   {

                                                     conf_wb_mem_io5_out,

                                                     conf_wb_mem_io4_out,

                                                     conf_wb_mem_io3_out,

                                                     conf_wb_mem_io2_out,

                                                     conf_wb_mem_io1_out,

                                                     conf_wb_mem_io0_out

                                                    } ;

wire    [5:0]   wbu_pref_en_in                  =   {

                                                     conf_wb_img_ctrl5_out[1],

                                                     conf_wb_img_ctrl4_out[1],

                                                     conf_wb_img_ctrl3_out[1],

                                                     conf_wb_img_ctrl2_out[1],

                                                     conf_wb_img_ctrl1_out[1],

                                                     conf_wb_img_ctrl0_out[1]

                                                    };

wire    [5:0]   wbu_mrl_en_in                   =   {

                                                     conf_wb_img_ctrl5_out[0],

                                                     conf_wb_img_ctrl4_out[0],

                                                     conf_wb_img_ctrl3_out[0],

                                                     conf_wb_img_ctrl2_out[0],

                                                     conf_wb_img_ctrl1_out[0],

                                                     conf_wb_img_ctrl0_out[0]

                                                    };

wire    [5:0]   wbu_at_en_in                    =   {

                                                     conf_wb_img_ctrl5_out[2],

                                                     conf_wb_img_ctrl4_out[2],

                                                     conf_wb_img_ctrl3_out[2],

                                                     conf_wb_img_ctrl2_out[2],

                                                     conf_wb_img_ctrl1_out[2],

                                                     conf_wb_img_ctrl0_out[2]

                                                    } ;

wire            wbu_pci_drcomp_pending_in       =   pciu_pci_drcomp_pending_out ;

wire            wbu_pciw_empty_in               =   pciu_pciw_fifo_empty_out ;

`ifdef HOST

    wire    [31:0]  wbu_conf_data_in            =   conf_w_data_out ;

`else

`ifdef GUEST

    wire    [31:0]  wbu_conf_data_in            =   conf_r_data_out ;

`endif

`endif

wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in  =   conf_wb_ba0_out ;

wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in  =   conf_wb_ba1_out ;

wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in  =   conf_wb_ba2_out ;

wire   [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in  =   conf_wb_ba3_out ;