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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_io_mux.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/10/05 08:14:29  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
// this module instantiates output flip flops for PCI interface and
// some fanout downsizing logic because of heavily constrained PCI signals
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module PCI_IO_MUX
(
    reset_in,
    clk_in,
    frame_in,
    frame_en_in,
    frame_load_in,
    irdy_in,
    irdy_en_in,
    devsel_in,
    devsel_en_in,
    trdy_in,
    trdy_en_in,
    stop_in,
    stop_en_in,
    master_load_in,
    master_load_on_transfer_in,
    target_load_in,
    target_load_on_transfer_in,
    cbe_in,
    cbe_en_in,
    mas_ad_in,
    tar_ad_in,
 
    par_in,
    par_en_in,
    perr_in,
    perr_en_in,
    serr_in,
    serr_en_in,
 
    req_in,
 
    mas_ad_en_in,
    tar_ad_en_in,
    tar_ad_en_reg_in,
 
    ad_en_out,
    frame_en_out,
    irdy_en_out,
    devsel_en_out,
    trdy_en_out,
    stop_en_out,
    cbe_en_out,
 
    frame_out,
    irdy_out,
    devsel_out,
    trdy_out,
    stop_out,
    cbe_out,
    ad_out,
    ad_load_out,
    ad_en_unregistered_out,
 
    par_out,
    par_en_out,
    perr_out,
    perr_en_out,
    serr_out,
    serr_en_out,
 
    req_out,
    req_en_out,
    pci_trdy_in,
    pci_irdy_in,
    pci_frame_in,
    pci_stop_in
);
 
input reset_in, clk_in ;
 
input           frame_in ;
input           frame_en_in ;
input           frame_load_in ;
input           irdy_in ;
input           irdy_en_in ;
input           devsel_in ;
input           devsel_en_in ;
input           trdy_in ;
input           trdy_en_in ;
input           stop_in ;
input           stop_en_in ;
input           master_load_in ;
input           target_load_in ;
 
input [3:0]     cbe_in ;
input           cbe_en_in ;
input [31:0]    mas_ad_in ;
input [31:0]    tar_ad_in ;
 
input           mas_ad_en_in ;
input           tar_ad_en_in ;
input           tar_ad_en_reg_in ;
 
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
 
output          frame_en_out ;
output          irdy_en_out ;
output          devsel_en_out ;
output          trdy_en_out ;
output          stop_en_out ;
output [31:0]   ad_en_out ;
output [3:0]    cbe_en_out ;
 
output          frame_out ;
output          irdy_out ;
output          devsel_out ;
output          trdy_out ;
output          stop_out ;
output [3:0]    cbe_out ;
output [31:0]   ad_out ;
output          ad_load_out ;
output          ad_en_unregistered_out ;
 
output          par_out ;
output          par_en_out ;
output          perr_out ;
output          perr_en_out ;
output          serr_out ;
output          serr_en_out ;
 
input           req_in ;
 
output          req_out ;
output          req_en_out ;
 
input           pci_trdy_in,
                pci_irdy_in,
                pci_frame_in,
                pci_stop_in ;
 
input           master_load_on_transfer_in ;
input           target_load_on_transfer_in ;
 
wire   [31:0]   temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
 
wire ad_en_ctrl_low ;
 
wire ad_en_ctrl_mlow ;
 
wire ad_en_ctrl_mhigh ;
 
wire ad_en_ctrl_high ;
 
wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
 
PCI_IO_MUX_AD_EN_CRIT ad_en_low_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_low)
);
 
PCI_IO_MUX_AD_EN_CRIT ad_en_mlow_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_mlow)
);
 
PCI_IO_MUX_AD_EN_CRIT ad_en_mhigh_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_mhigh)
);
 
PCI_IO_MUX_AD_EN_CRIT ad_en_high_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_high)
);
 
assign ad_en_unregistered_out = ad_en_ctrl_high ;
 
wire load = master_load_in || target_load_in ;
wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
 
wire   ad_load_ctrl_low ;
wire   ad_load_ctrl_mlow ;
wire   ad_load_ctrl_mhigh ;
wire   ad_load_ctrl_high ;
 
assign ad_load_out = ad_load_ctrl_high ;
 
PCI_IO_MUX_AD_LOAD_CRIT ad_load_low_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_low)
);
 
PCI_IO_MUX_AD_LOAD_CRIT ad_load_mlow_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_mlow)
);
 
PCI_IO_MUX_AD_LOAD_CRIT ad_load_mhigh_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_mhigh)
);
 
PCI_IO_MUX_AD_LOAD_CRIT ad_load_high_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_high)
);
 
OUT_REG ad_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[0] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[0] ),
    .dat_out      ( ad_out[0] )
);
 
OUT_REG ad_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[1] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[1] ),
    .dat_out      ( ad_out[1] )
);
 
OUT_REG ad_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[2] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[2] ),
    .dat_out      ( ad_out[2] )
);
 
OUT_REG ad_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[3] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[3] ),
    .dat_out      ( ad_out[3] )
);
 
OUT_REG ad_iob4
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[4] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[4] ),
    .dat_out      ( ad_out[4] )
);
 
OUT_REG ad_iob5
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[5] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[5] ),
    .dat_out      ( ad_out[5] )
);
 
OUT_REG ad_iob6
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[6] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[6] ),
    .dat_out      ( ad_out[6] )
);
 
OUT_REG ad_iob7
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[7] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[7] ),
    .dat_out      ( ad_out[7] )
);
 
OUT_REG ad_iob8
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[8] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[8] ),
    .dat_out      ( ad_out[8] )
);
 
OUT_REG ad_iob9
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[9] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[9] ),
    .dat_out      ( ad_out[9] )
);
 
OUT_REG ad_iob10
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[10] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[10] ),
    .dat_out      ( ad_out[10] )
);
 
OUT_REG ad_iob11
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[11] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[11] ),
    .dat_out      ( ad_out[11] )
);
 
OUT_REG ad_iob12
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[12] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[12] ),
    .dat_out      ( ad_out[12] )
);
 
OUT_REG ad_iob13
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[13] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[13] ),
    .dat_out      ( ad_out[13] )
);
 
OUT_REG ad_iob14
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[14] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[14] ),
    .dat_out      ( ad_out[14] )
);
 
OUT_REG ad_iob15
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[15] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[15] ),
    .dat_out      ( ad_out[15] )
);
 
OUT_REG ad_iob16
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[16] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[16] ),
    .dat_out      ( ad_out[16] )
);
 
OUT_REG ad_iob17
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[17] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[17] ),
    .dat_out      ( ad_out[17] )
);
 
OUT_REG ad_iob18
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[18] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[18] ),
    .dat_out      ( ad_out[18] )
);
 
OUT_REG ad_iob19
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[19] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[19] ),
    .dat_out      ( ad_out[19] )
);
 
OUT_REG ad_iob20
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[20] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[20] ),
    .dat_out      ( ad_out[20] )
);
 
OUT_REG ad_iob21
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[21] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[21] ),
    .dat_out      ( ad_out[21] )
);
 
OUT_REG ad_iob22
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[22] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[22] ),
    .dat_out      ( ad_out[22] )
);
 
OUT_REG ad_iob23
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[23] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[23] ),
    .dat_out      ( ad_out[23] )
);
 
OUT_REG ad_iob24
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[24] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[24] ),
    .dat_out      ( ad_out[24] )
);
 
OUT_REG ad_iob25
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[25] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[25] ),
    .dat_out      ( ad_out[25] )
);
 
OUT_REG ad_iob26
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[26] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[26] ),
    .dat_out      ( ad_out[26] )
);
 
OUT_REG ad_iob27
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[27] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[27] ),
    .dat_out      ( ad_out[27] )
);
 
OUT_REG ad_iob28
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[28] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[28] ),
    .dat_out      ( ad_out[28] )
);
 
OUT_REG ad_iob29
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[29] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[29] ),
    .dat_out      ( ad_out[29] )
);
 
OUT_REG ad_iob30
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[30] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[30] ),
    .dat_out      ( ad_out[30] )
);
 
OUT_REG ad_iob31
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[31] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[31] ),
    .dat_out      ( ad_out[31] )
);
 
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
wire [3:0] cbe_en_ctrl   = {4{ cbe_en_in }} ;
 
OUT_REG cbe_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[0] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[0] ) ,
    .en_in        ( cbe_en_ctrl[0] ) ,
    .en_out       ( cbe_en_out[0] ),
    .dat_out      ( cbe_out[0] )
);
 
OUT_REG cbe_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[1] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[1] ) ,
    .en_in        ( cbe_en_ctrl[1] ) ,
    .en_out       ( cbe_en_out[1] ),
    .dat_out      ( cbe_out[1] )
);
 
OUT_REG cbe_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[2] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[2] ) ,
    .en_in        ( cbe_en_ctrl[2] ) ,
    .en_out       ( cbe_en_out[2] ),
    .dat_out      ( cbe_out[2] )
);
 
OUT_REG cbe_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[3] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[3] ) ,
    .en_in        ( cbe_en_ctrl[3] ) ,
    .en_out       ( cbe_en_out[3] ),
    .dat_out      ( cbe_out[3] )
);
 
OUT_REG frame_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( frame_load_in ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( frame_in ) ,
    .en_in        ( frame_en_in ) ,
    .en_out       ( frame_en_out ),
    .dat_out      ( frame_out )
);
 
OUT_REG irdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( irdy_in ) ,
    .en_in        ( irdy_en_in ) ,
    .en_out       ( irdy_en_out ),
    .dat_out      ( irdy_out )
);
 
OUT_REG trdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( trdy_in ) ,
    .en_in        ( trdy_en_in ) ,
    .en_out       ( trdy_en_out ),
    .dat_out      ( trdy_out )
);
 
OUT_REG stop_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( stop_in ) ,
    .en_in        ( stop_en_in ) ,
    .en_out       ( stop_en_out ),
    .dat_out      ( stop_out )
);
 
OUT_REG devsel_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( devsel_in ) ,
    .en_in        ( devsel_en_in ) ,
    .en_out       ( devsel_en_out ),
    .dat_out      ( devsel_out )
);
 
OUT_REG par_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( par_in ) ,
    .en_in        ( par_en_in ) ,
    .en_out       ( par_en_out ),
    .dat_out      ( par_out )
);
 
OUT_REG perr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( perr_in ) ,
    .en_in        ( perr_en_in ) ,
    .en_out       ( perr_en_out ),
    .dat_out      ( perr_out )
);
 
OUT_REG serr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( serr_in ) ,
    .en_in        ( serr_en_in ) ,
    .en_out       ( serr_en_out ),
    .dat_out      ( serr_out )
);
 
OUT_REG req_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( req_in ) ,
    .en_in        ( 1'b1 ) ,
    .en_out       ( req_en_out ),
    .dat_out      ( req_out )
);
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_io_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	21	mihad	`// Revision 1.2 2001/10/05 08:14:29 mihad`
46			`// Updated all files with inclusion of timescale file for simulation purposes.`
47			`//`
48	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
49			`// New project directory structure`
50	2	mihad	`//`
51	6	mihad	`//`
52	2	mihad
53			`// this module instantiates output flip flops for PCI interface and`
54			`// some fanout downsizing logic because of heavily constrained PCI signals`
55	21	mihad
56			`// synopsys translate_off`
57	6	mihad	`include "timescale.v"
58	21	mihad	`// synopsys translate_on`
59	6	mihad
60	2	mihad	`module PCI_IO_MUX`
61			`(`
62			`reset_in,`
63			`clk_in,`
64			`frame_in,`
65			`frame_en_in,`
66			`frame_load_in,`
67			`irdy_in,`
68			`irdy_en_in,`
69			`devsel_in,`
70			`devsel_en_in,`
71			`trdy_in,`
72			`trdy_en_in,`
73			`stop_in,`
74			`stop_en_in,`
75			`master_load_in,`
76	21	mihad	`master_load_on_transfer_in,`
77	2	mihad	`target_load_in,`
78	21	mihad	`target_load_on_transfer_in,`
79	2	mihad	`cbe_in,`
80			`cbe_en_in,`
81			`mas_ad_in,`
82			`tar_ad_in,`
83
84			`par_in,`
85			`par_en_in,`
86			`perr_in,`
87			`perr_en_in,`
88			`serr_in,`
89			`serr_en_in,`
90
91			`req_in,`
92	21	mihad
93	2	mihad	`mas_ad_en_in,`
94			`tar_ad_en_in,`
95			`tar_ad_en_reg_in,`
96	21	mihad
97	2	mihad	`ad_en_out,`
98			`frame_en_out,`
99			`irdy_en_out,`
100			`devsel_en_out,`
101			`trdy_en_out,`
102			`stop_en_out,`
103			`cbe_en_out,`
104
105			`frame_out,`
106			`irdy_out,`
107			`devsel_out,`
108			`trdy_out,`
109			`stop_out,`
110			`cbe_out,`
111			`ad_out,`
112	21	mihad	`ad_load_out,`
113			`ad_en_unregistered_out,`
114
115	2	mihad	`par_out,`
116			`par_en_out,`
117			`perr_out,`
118			`perr_en_out,`
119			`serr_out,`
120			`serr_en_out,`
121
122			`req_out,`
123	21	mihad	`req_en_out,`
124			`pci_trdy_in,`
125			`pci_irdy_in,`
126			`pci_frame_in,`
127			`pci_stop_in`
128	2	mihad	`);`
129
130			`input reset_in, clk_in ;`
131
132			`input frame_in ;`
133			`input frame_en_in ;`
134			`input frame_load_in ;`
135			`input irdy_in ;`
136			`input irdy_en_in ;`
137			`input devsel_in ;`
138			`input devsel_en_in ;`
139			`input trdy_in ;`
140			`input trdy_en_in ;`
141			`input stop_in ;`
142			`input stop_en_in ;`
143			`input master_load_in ;`
144			`input target_load_in ;`
145
146			`input [3:0] cbe_in ;`
147			`input cbe_en_in ;`
148			`input [31:0] mas_ad_in ;`
149			`input [31:0] tar_ad_in ;`
150
151			`input mas_ad_en_in ;`
152			`input tar_ad_en_in ;`
153			`input tar_ad_en_reg_in ;`
154
155			`input par_in ;`
156			`input par_en_in ;`
157	21	mihad	`input perr_in ;`
158	2	mihad	`input perr_en_in ;`
159	21	mihad	`input serr_in ;`
160	2	mihad	`input serr_en_in ;`
161
162			`output frame_en_out ;`
163			`output irdy_en_out ;`
164			`output devsel_en_out ;`
165			`output trdy_en_out ;`
166			`output stop_en_out ;`
167			`output [31:0] ad_en_out ;`
168			`output [3:0] cbe_en_out ;`
169
170			`output frame_out ;`
171			`output irdy_out ;`
172			`output devsel_out ;`
173			`output trdy_out ;`
174			`output stop_out ;`
175			`output [3:0] cbe_out ;`
176			`output [31:0] ad_out ;`
177	21	mihad	`output ad_load_out ;`
178			`output ad_en_unregistered_out ;`
179	2	mihad
180			`output par_out ;`
181			`output par_en_out ;`
182	21	mihad	`output perr_out ;`
183	2	mihad	`output perr_en_out ;`
184	21	mihad	`output serr_out ;`
185	2	mihad	`output serr_en_out ;`
186
187			`input req_in ;`
188
189			`output req_out ;`
190			`output req_en_out ;`
191
192	21	mihad	`input pci_trdy_in,`
193			`pci_irdy_in,`
194			`pci_frame_in,`
195			`pci_stop_in ;`
196	2	mihad
197	21	mihad	`input master_load_on_transfer_in ;`
198			`input target_load_on_transfer_in ;`
199
200	2	mihad	`wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;`
201
202			`wire ad_en_ctrl_low ;`
203
204			`wire ad_en_ctrl_mlow ;`
205
206			`wire ad_en_ctrl_mhigh ;`
207
208			`wire ad_en_ctrl_high ;`
209
210	21	mihad	`wire ad_enable_internal = mas_ad_en_in \|\| tar_ad_en_in ;`
211	2	mihad
212	21	mihad	`PCI_IO_MUX_AD_EN_CRIT ad_en_low_gen`
213			`(`
214			`.ad_en_in (ad_enable_internal),`
215			`.pci_frame_in (pci_frame_in),`
216			`.pci_trdy_in (pci_trdy_in),`
217			`.pci_stop_in (pci_stop_in),`
218			`.ad_en_out (ad_en_ctrl_low)`
219			`);`
220	2	mihad
221	21	mihad	`PCI_IO_MUX_AD_EN_CRIT ad_en_mlow_gen`
222			`(`
223			`.ad_en_in (ad_enable_internal),`
224			`.pci_frame_in (pci_frame_in),`
225			`.pci_trdy_in (pci_trdy_in),`
226			`.pci_stop_in (pci_stop_in),`
227			`.ad_en_out (ad_en_ctrl_mlow)`
228			`);`
229	2	mihad
230	21	mihad	`PCI_IO_MUX_AD_EN_CRIT ad_en_mhigh_gen`
231			`(`
232			`.ad_en_in (ad_enable_internal),`
233			`.pci_frame_in (pci_frame_in),`
234			`.pci_trdy_in (pci_trdy_in),`
235			`.pci_stop_in (pci_stop_in),`
236			`.ad_en_out (ad_en_ctrl_mhigh)`
237			`);`
238	2	mihad
239	21	mihad	`PCI_IO_MUX_AD_EN_CRIT ad_en_high_gen`
240			`(`
241			`.ad_en_in (ad_enable_internal),`
242			`.pci_frame_in (pci_frame_in),`
243			`.pci_trdy_in (pci_trdy_in),`
244			`.pci_stop_in (pci_stop_in),`
245			`.ad_en_out (ad_en_ctrl_high)`
246			`);`
247
248			`assign ad_en_unregistered_out = ad_en_ctrl_high ;`
249
250			`wire load = master_load_in \|\| target_load_in ;`
251			`wire load_on_transfer = master_load_on_transfer_in \|\| target_load_on_transfer_in ;`
252
253			`wire ad_load_ctrl_low ;`
254			`wire ad_load_ctrl_mlow ;`
255			`wire ad_load_ctrl_mhigh ;`
256			`wire ad_load_ctrl_high ;`
257
258			`assign ad_load_out = ad_load_ctrl_high ;`
259
260			`PCI_IO_MUX_AD_LOAD_CRIT ad_load_low_gen`
261			`(`
262			`.load_in(load),`
263			`.load_on_transfer_in(load_on_transfer),`
264			`.pci_irdy_in(pci_irdy_in),`
265			`.pci_trdy_in(pci_trdy_in),`
266			`.load_out(ad_load_ctrl_low)`
267			`);`
268
269			`PCI_IO_MUX_AD_LOAD_CRIT ad_load_mlow_gen`
270			`(`
271			`.load_in(load),`
272			`.load_on_transfer_in(load_on_transfer),`
273			`.pci_irdy_in(pci_irdy_in),`
274			`.pci_trdy_in(pci_trdy_in),`
275			`.load_out(ad_load_ctrl_mlow)`
276			`);`
277
278			`PCI_IO_MUX_AD_LOAD_CRIT ad_load_mhigh_gen`
279			`(`
280			`.load_in(load),`
281			`.load_on_transfer_in(load_on_transfer),`
282			`.pci_irdy_in(pci_irdy_in),`
283			`.pci_trdy_in(pci_trdy_in),`
284			`.load_out(ad_load_ctrl_mhigh)`
285			`);`
286
287			`PCI_IO_MUX_AD_LOAD_CRIT ad_load_high_gen`
288			`(`
289			`.load_in(load),`
290			`.load_on_transfer_in(load_on_transfer),`
291			`.pci_irdy_in(pci_irdy_in),`
292			`.pci_trdy_in(pci_trdy_in),`
293			`.load_out(ad_load_ctrl_high)`
294			`);`
295
296	2	mihad	`OUT_REG ad_iob0`
297	21	mihad	`(`
298	2	mihad	`.reset_in ( reset_in ),`
299			`.clk_in ( clk_in) ,`
300			`.dat_en_in ( ad_load_ctrl_low ),`
301			`.en_en_in ( 1'b1 ),`
302			`.dat_in ( temp_ad[0] ) ,`
303			`.en_in ( ad_en_ctrl_low ) ,`
304			`.en_out ( ad_en_out[0] ),`
305			`.dat_out ( ad_out[0] )`
306			`);`
307
308			`OUT_REG ad_iob1`
309	21	mihad	`(`
310	2	mihad	`.reset_in ( reset_in ),`
311			`.clk_in ( clk_in) ,`
312			`.dat_en_in ( ad_load_ctrl_low ),`
313			`.en_en_in ( 1'b1 ),`
314			`.dat_in ( temp_ad[1] ) ,`
315			`.en_in ( ad_en_ctrl_low ) ,`
316			`.en_out ( ad_en_out[1] ),`
317			`.dat_out ( ad_out[1] )`
318			`);`
319
320			`OUT_REG ad_iob2`
321	21	mihad	`(`
322	2	mihad	`.reset_in ( reset_in ),`
323			`.clk_in ( clk_in) ,`
324			`.dat_en_in ( ad_load_ctrl_low ),`
325			`.en_en_in ( 1'b1 ),`
326			`.dat_in ( temp_ad[2] ) ,`
327			`.en_in ( ad_en_ctrl_low ) ,`
328			`.en_out ( ad_en_out[2] ),`
329			`.dat_out ( ad_out[2] )`
330			`);`
331
332			`OUT_REG ad_iob3`
333	21	mihad	`(`
334	2	mihad	`.reset_in ( reset_in ),`
335			`.clk_in ( clk_in) ,`
336			`.dat_en_in ( ad_load_ctrl_low ),`
337			`.en_en_in ( 1'b1 ),`
338			`.dat_in ( temp_ad[3] ) ,`
339			`.en_in ( ad_en_ctrl_low ) ,`
340			`.en_out ( ad_en_out[3] ),`
341			`.dat_out ( ad_out[3] )`
342			`);`
343
344			`OUT_REG ad_iob4`
345	21	mihad	`(`
346	2	mihad	`.reset_in ( reset_in ),`
347			`.clk_in ( clk_in) ,`
348			`.dat_en_in ( ad_load_ctrl_low ),`
349			`.en_en_in ( 1'b1 ),`
350			`.dat_in ( temp_ad[4] ) ,`
351			`.en_in ( ad_en_ctrl_low ) ,`
352			`.en_out ( ad_en_out[4] ),`
353			`.dat_out ( ad_out[4] )`
354			`);`
355
356			`OUT_REG ad_iob5`
357	21	mihad	`(`
358	2	mihad	`.reset_in ( reset_in ),`
359			`.clk_in ( clk_in) ,`
360			`.dat_en_in ( ad_load_ctrl_low ),`
361			`.en_en_in ( 1'b1 ),`
362			`.dat_in ( temp_ad[5] ) ,`
363			`.en_in ( ad_en_ctrl_low ) ,`
364			`.en_out ( ad_en_out[5] ),`
365			`.dat_out ( ad_out[5] )`
366			`);`
367
368			`OUT_REG ad_iob6`
369	21	mihad	`(`
370	2	mihad	`.reset_in ( reset_in ),`
371			`.clk_in ( clk_in) ,`
372			`.dat_en_in ( ad_load_ctrl_low ),`
373			`.en_en_in ( 1'b1 ),`
374			`.dat_in ( temp_ad[6] ) ,`
375			`.en_in ( ad_en_ctrl_low ) ,`
376			`.en_out ( ad_en_out[6] ),`
377			`.dat_out ( ad_out[6] )`
378			`);`
379
380			`OUT_REG ad_iob7`
381	21	mihad	`(`
382	2	mihad	`.reset_in ( reset_in ),`
383			`.clk_in ( clk_in) ,`
384			`.dat_en_in ( ad_load_ctrl_low ),`
385			`.en_en_in ( 1'b1 ),`
386			`.dat_in ( temp_ad[7] ) ,`
387			`.en_in ( ad_en_ctrl_low ) ,`
388			`.en_out ( ad_en_out[7] ),`
389			`.dat_out ( ad_out[7] )`
390			`);`
391
392			`OUT_REG ad_iob8`
393	21	mihad	`(`
394	2	mihad	`.reset_in ( reset_in ),`
395			`.clk_in ( clk_in) ,`
396			`.dat_en_in ( ad_load_ctrl_mlow ),`
397			`.en_en_in ( 1'b1 ),`
398			`.dat_in ( temp_ad[8] ) ,`
399			`.en_in ( ad_en_ctrl_mlow ) ,`
400			`.en_out ( ad_en_out[8] ),`
401			`.dat_out ( ad_out[8] )`
402			`);`
403
404			`OUT_REG ad_iob9`
405	21	mihad	`(`
406	2	mihad	`.reset_in ( reset_in ),`
407			`.clk_in ( clk_in) ,`
408			`.dat_en_in ( ad_load_ctrl_mlow ),`
409			`.en_en_in ( 1'b1 ),`
410			`.dat_in ( temp_ad[9] ) ,`
411			`.en_in ( ad_en_ctrl_mlow ) ,`
412			`.en_out ( ad_en_out[9] ),`
413			`.dat_out ( ad_out[9] )`
414			`);`
415
416			`OUT_REG ad_iob10`
417	21	mihad	`(`
418	2	mihad	`.reset_in ( reset_in ),`
419			`.clk_in ( clk_in) ,`
420			`.dat_en_in ( ad_load_ctrl_mlow ),`
421			`.en_en_in ( 1'b1 ),`
422			`.dat_in ( temp_ad[10] ) ,`
423			`.en_in ( ad_en_ctrl_mlow ) ,`
424			`.en_out ( ad_en_out[10] ),`
425			`.dat_out ( ad_out[10] )`
426			`);`
427
428			`OUT_REG ad_iob11`
429	21	mihad	`(`
430	2	mihad	`.reset_in ( reset_in ),`
431			`.clk_in ( clk_in) ,`
432			`.dat_en_in ( ad_load_ctrl_mlow ),`
433			`.en_en_in ( 1'b1 ),`
434			`.dat_in ( temp_ad[11] ) ,`
435			`.en_in ( ad_en_ctrl_mlow ) ,`
436			`.en_out ( ad_en_out[11] ),`
437			`.dat_out ( ad_out[11] )`
438			`);`
439
440			`OUT_REG ad_iob12`
441	21	mihad	`(`
442	2	mihad	`.reset_in ( reset_in ),`
443			`.clk_in ( clk_in) ,`
444			`.dat_en_in ( ad_load_ctrl_mlow ),`
445			`.en_en_in ( 1'b1 ),`
446			`.dat_in ( temp_ad[12] ) ,`
447			`.en_in ( ad_en_ctrl_mlow ) ,`
448			`.en_out ( ad_en_out[12] ),`
449			`.dat_out ( ad_out[12] )`
450			`);`
451
452			`OUT_REG ad_iob13`
453	21	mihad	`(`
454	2	mihad	`.reset_in ( reset_in ),`
455			`.clk_in ( clk_in) ,`
456			`.dat_en_in ( ad_load_ctrl_mlow ),`
457			`.en_en_in ( 1'b1 ),`
458			`.dat_in ( temp_ad[13] ) ,`
459			`.en_in ( ad_en_ctrl_mlow ) ,`
460			`.en_out ( ad_en_out[13] ),`
461			`.dat_out ( ad_out[13] )`
462			`);`
463
464			`OUT_REG ad_iob14`
465	21	mihad	`(`
466	2	mihad	`.reset_in ( reset_in ),`
467			`.clk_in ( clk_in) ,`
468			`.dat_en_in ( ad_load_ctrl_mlow ),`
469			`.en_en_in ( 1'b1 ),`
470			`.dat_in ( temp_ad[14] ) ,`
471			`.en_in ( ad_en_ctrl_mlow ) ,`
472			`.en_out ( ad_en_out[14] ),`
473			`.dat_out ( ad_out[14] )`
474			`);`
475
476			`OUT_REG ad_iob15`
477	21	mihad	`(`
478	2	mihad	`.reset_in ( reset_in ),`
479			`.clk_in ( clk_in) ,`
480			`.dat_en_in ( ad_load_ctrl_mlow ),`
481			`.en_en_in ( 1'b1 ),`
482			`.dat_in ( temp_ad[15] ) ,`
483			`.en_in ( ad_en_ctrl_mlow ) ,`
484			`.en_out ( ad_en_out[15] ),`
485			`.dat_out ( ad_out[15] )`
486			`);`
487
488			`OUT_REG ad_iob16`
489	21	mihad	`(`
490	2	mihad	`.reset_in ( reset_in ),`
491			`.clk_in ( clk_in) ,`
492			`.dat_en_in ( ad_load_ctrl_mhigh ),`
493			`.en_en_in ( 1'b1 ),`
494			`.dat_in ( temp_ad[16] ) ,`
495			`.en_in ( ad_en_ctrl_mhigh ) ,`
496			`.en_out ( ad_en_out[16] ),`
497			`.dat_out ( ad_out[16] )`
498			`);`
499
500			`OUT_REG ad_iob17`

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_io_mux.v] - Blame information for rev 21