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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_io_mux.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
// this module instantiates output flip flops for PCI interface and
// some fanout downsizing logic because of heavily constrained PCI signals
`include "constants.v"
`include "timescale.v"
 
module PCI_IO_MUX
(
    reset_in,
    clk_in,
    frame_in,
    frame_en_in,
    frame_load_in,
    irdy_in,
    irdy_en_in,
    devsel_in,
    devsel_en_in,
    trdy_in,
    trdy_en_in,
    stop_in,
    stop_en_in,
    master_load_in,
    target_load_in,
    cbe_in,
    cbe_en_in,
    mas_ad_in,
    tar_ad_in,
 
    par_in,
    par_en_in,
    perr_in,
    perr_en_in,
    serr_in,
    serr_en_in,
 
    req_in,
 
    mas_ad_en_in,
    tar_ad_en_in,
    tar_ad_en_reg_in,
 
    ad_en_out,
    frame_en_out,
    irdy_en_out,
    devsel_en_out,
    trdy_en_out,
    stop_en_out,
    cbe_en_out,
 
    frame_out,
    irdy_out,
    devsel_out,
    trdy_out,
    stop_out,
    cbe_out,
    ad_out,
 
    par_out,
    par_en_out,
    perr_out,
    perr_en_out,
    serr_out,
    serr_en_out,
 
    req_out,
    req_en_out
 
);
 
input reset_in, clk_in ;
 
input           frame_in ;
input           frame_en_in ;
input           frame_load_in ;
input           irdy_in ;
input           irdy_en_in ;
input           devsel_in ;
input           devsel_en_in ;
input           trdy_in ;
input           trdy_en_in ;
input           stop_in ;
input           stop_en_in ;
input           master_load_in ;
input           target_load_in ;
 
input [3:0]     cbe_in ;
input           cbe_en_in ;
input [31:0]    mas_ad_in ;
input [31:0]    tar_ad_in ;
 
input           mas_ad_en_in ;
input           tar_ad_en_in ;
input           tar_ad_en_reg_in ;
 
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
 
output          frame_en_out ;
output          irdy_en_out ;
output          devsel_en_out ;
output          trdy_en_out ;
output          stop_en_out ;
output [31:0]   ad_en_out ;
output [3:0]    cbe_en_out ;
 
output          frame_out ;
output          irdy_out ;
output          devsel_out ;
output          trdy_out ;
output          stop_out ;
output [3:0]    cbe_out ;
output [31:0]   ad_out ;
 
output          par_out ;
output          par_en_out ;
output          perr_out ;
output          perr_en_out ;
output          serr_out ;
output          serr_en_out ;
 
input           req_in ;
 
output          req_out ;
output          req_en_out ;
 
 
wire   [31:0]   temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
 
wire ad_en_ctrl_low ;
IO_MUX_EN_MULT ad_en_low_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_low)) ;
 
wire ad_en_ctrl_mlow ;
IO_MUX_EN_MULT ad_en_mlow_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mlow)) ;
 
wire ad_en_ctrl_mhigh ;
IO_MUX_EN_MULT ad_en_mhigh_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mhigh)) ;
 
wire ad_en_ctrl_high ;
IO_MUX_EN_MULT ad_en_high_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_high)) ;
 
wire ad_load_ctrl_low ;
IO_MUX_LOAD_MUX ad_load_low_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_low));
 
wire ad_load_ctrl_mlow ;
IO_MUX_LOAD_MUX ad_load_mlow_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mlow));
 
wire ad_load_ctrl_mhigh ;
IO_MUX_LOAD_MUX ad_load_mhigh_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mhigh));
 
wire ad_load_ctrl_high ;
IO_MUX_LOAD_MUX ad_load_high_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_high)) ;
 
OUT_REG ad_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[0] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[0] ),
    .dat_out      ( ad_out[0] )
);
 
OUT_REG ad_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[1] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[1] ),
    .dat_out      ( ad_out[1] )
);
 
OUT_REG ad_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[2] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[2] ),
    .dat_out      ( ad_out[2] )
);
 
OUT_REG ad_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[3] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[3] ),
    .dat_out      ( ad_out[3] )
);
 
OUT_REG ad_iob4
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[4] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[4] ),
    .dat_out      ( ad_out[4] )
);
 
OUT_REG ad_iob5
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[5] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[5] ),
    .dat_out      ( ad_out[5] )
);
 
OUT_REG ad_iob6
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[6] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[6] ),
    .dat_out      ( ad_out[6] )
);
 
OUT_REG ad_iob7
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[7] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[7] ),
    .dat_out      ( ad_out[7] )
);
 
OUT_REG ad_iob8
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[8] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[8] ),
    .dat_out      ( ad_out[8] )
);
 
OUT_REG ad_iob9
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[9] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[9] ),
    .dat_out      ( ad_out[9] )
);
 
OUT_REG ad_iob10
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[10] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[10] ),
    .dat_out      ( ad_out[10] )
);
 
OUT_REG ad_iob11
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[11] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[11] ),
    .dat_out      ( ad_out[11] )
);
 
OUT_REG ad_iob12
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[12] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[12] ),
    .dat_out      ( ad_out[12] )
);
 
OUT_REG ad_iob13
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[13] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[13] ),
    .dat_out      ( ad_out[13] )
);
 
OUT_REG ad_iob14
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[14] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[14] ),
    .dat_out      ( ad_out[14] )
);
 
OUT_REG ad_iob15
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[15] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[15] ),
    .dat_out      ( ad_out[15] )
);
 
OUT_REG ad_iob16
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[16] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[16] ),
    .dat_out      ( ad_out[16] )
);
 
OUT_REG ad_iob17
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[17] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[17] ),
    .dat_out      ( ad_out[17] )
);
 
OUT_REG ad_iob18
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[18] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[18] ),
    .dat_out      ( ad_out[18] )
);
 
OUT_REG ad_iob19
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[19] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[19] ),
    .dat_out      ( ad_out[19] )
);
 
OUT_REG ad_iob20
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[20] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[20] ),
    .dat_out      ( ad_out[20] )
);
 
OUT_REG ad_iob21
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[21] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[21] ),
    .dat_out      ( ad_out[21] )
);
 
OUT_REG ad_iob22
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[22] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[22] ),
    .dat_out      ( ad_out[22] )
);
 
OUT_REG ad_iob23
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[23] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[23] ),
    .dat_out      ( ad_out[23] )
);
 
OUT_REG ad_iob24
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[24] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[24] ),
    .dat_out      ( ad_out[24] )
);
 
OUT_REG ad_iob25
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[25] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[25] ),
    .dat_out      ( ad_out[25] )
);
 
OUT_REG ad_iob26
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[26] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[26] ),
    .dat_out      ( ad_out[26] )
);
 
OUT_REG ad_iob27
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[27] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[27] ),
    .dat_out      ( ad_out[27] )
);
 
OUT_REG ad_iob28
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[28] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[28] ),
    .dat_out      ( ad_out[28] )
);
 
OUT_REG ad_iob29
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[29] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[29] ),
    .dat_out      ( ad_out[29] )
);
 
OUT_REG ad_iob30
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[30] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[30] ),
    .dat_out      ( ad_out[30] )
);
 
OUT_REG ad_iob31
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[31] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[31] ),
    .dat_out      ( ad_out[31] )
);
 
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
wire [3:0] cbe_en_ctrl   = {4{ cbe_en_in }} ;
 
OUT_REG cbe_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[0] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[0] ) ,
    .en_in        ( cbe_en_ctrl[0] ) ,
    .en_out       ( cbe_en_out[0] ),
    .dat_out      ( cbe_out[0] )
);
 
OUT_REG cbe_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[1] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[1] ) ,
    .en_in        ( cbe_en_ctrl[1] ) ,
    .en_out       ( cbe_en_out[1] ),
    .dat_out      ( cbe_out[1] )
);
 
OUT_REG cbe_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[2] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[2] ) ,
    .en_in        ( cbe_en_ctrl[2] ) ,
    .en_out       ( cbe_en_out[2] ),
    .dat_out      ( cbe_out[2] )
);
 
OUT_REG cbe_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[3] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[3] ) ,
    .en_in        ( cbe_en_ctrl[3] ) ,
    .en_out       ( cbe_en_out[3] ),
    .dat_out      ( cbe_out[3] )
);
 
OUT_REG frame_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( frame_load_in ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( frame_in ) ,
    .en_in        ( frame_en_in ) ,
    .en_out       ( frame_en_out ),
    .dat_out      ( frame_out )
);
 
OUT_REG irdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( irdy_in ) ,
    .en_in        ( irdy_en_in ) ,
    .en_out       ( irdy_en_out ),
    .dat_out      ( irdy_out )
);
 
OUT_REG trdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( trdy_in ) ,
    .en_in        ( trdy_en_in ) ,
    .en_out       ( trdy_en_out ),
    .dat_out      ( trdy_out )
);
 
OUT_REG stop_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( stop_in ) ,
    .en_in        ( stop_en_in ) ,
    .en_out       ( stop_en_out ),
    .dat_out      ( stop_out )
);
 
OUT_REG devsel_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( devsel_in ) ,
    .en_in        ( devsel_en_in ) ,
    .en_out       ( devsel_en_out ),
    .dat_out      ( devsel_out )
);
 
OUT_REG par_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( par_in ) ,
    .en_in        ( par_en_in ) ,
    .en_out       ( par_en_out ),
    .dat_out      ( par_out )
);
 
OUT_REG perr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( perr_in ) ,
    .en_in        ( perr_en_in ) ,
    .en_out       ( perr_en_out ),
    .dat_out      ( perr_out )
);
 
OUT_REG serr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( serr_in ) ,
    .en_in        ( serr_en_in ) ,
    .en_out       ( serr_en_out ),
    .dat_out      ( serr_out )
);
 
OUT_REG req_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( req_in ) ,
    .en_in        ( 1'b1 ) ,
    .en_out       ( req_en_out ),
    .dat_out      ( req_out )
);
 
endmodule

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_io_mux.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_io_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
46			`// New project directory structure`
47	2	mihad	`//`
48	6	mihad	`//`
49	2	mihad
50			`// this module instantiates output flip flops for PCI interface and`
51			`// some fanout downsizing logic because of heavily constrained PCI signals`
52			`include "constants.v"
53	6	mihad	`include "timescale.v"
54
55	2	mihad	`module PCI_IO_MUX`
56			`(`
57			`reset_in,`
58			`clk_in,`
59			`frame_in,`
60			`frame_en_in,`
61			`frame_load_in,`
62			`irdy_in,`
63			`irdy_en_in,`
64			`devsel_in,`
65			`devsel_en_in,`
66			`trdy_in,`
67			`trdy_en_in,`
68			`stop_in,`
69			`stop_en_in,`
70			`master_load_in,`
71			`target_load_in,`
72			`cbe_in,`
73			`cbe_en_in,`
74			`mas_ad_in,`
75			`tar_ad_in,`
76
77			`par_in,`
78			`par_en_in,`
79			`perr_in,`
80			`perr_en_in,`
81			`serr_in,`
82			`serr_en_in,`
83
84			`req_in,`
85
86			`mas_ad_en_in,`
87			`tar_ad_en_in,`
88			`tar_ad_en_reg_in,`
89
90			`ad_en_out,`
91			`frame_en_out,`
92			`irdy_en_out,`
93			`devsel_en_out,`
94			`trdy_en_out,`
95			`stop_en_out,`
96			`cbe_en_out,`
97
98			`frame_out,`
99			`irdy_out,`
100			`devsel_out,`
101			`trdy_out,`
102			`stop_out,`
103			`cbe_out,`
104			`ad_out,`
105
106			`par_out,`
107			`par_en_out,`
108			`perr_out,`
109			`perr_en_out,`
110			`serr_out,`
111			`serr_en_out,`
112
113			`req_out,`
114			`req_en_out`
115
116			`);`
117
118			`input reset_in, clk_in ;`
119
120			`input frame_in ;`
121			`input frame_en_in ;`
122			`input frame_load_in ;`
123			`input irdy_in ;`
124			`input irdy_en_in ;`
125			`input devsel_in ;`
126			`input devsel_en_in ;`
127			`input trdy_in ;`
128			`input trdy_en_in ;`
129			`input stop_in ;`
130			`input stop_en_in ;`
131			`input master_load_in ;`
132			`input target_load_in ;`
133
134			`input [3:0] cbe_in ;`
135			`input cbe_en_in ;`
136			`input [31:0] mas_ad_in ;`
137			`input [31:0] tar_ad_in ;`
138
139			`input mas_ad_en_in ;`
140			`input tar_ad_en_in ;`
141			`input tar_ad_en_reg_in ;`
142
143			`input par_in ;`
144			`input par_en_in ;`
145			`input perr_in ;`
146			`input perr_en_in ;`
147			`input serr_in ;`
148			`input serr_en_in ;`
149
150			`output frame_en_out ;`
151			`output irdy_en_out ;`
152			`output devsel_en_out ;`
153			`output trdy_en_out ;`
154			`output stop_en_out ;`
155			`output [31:0] ad_en_out ;`
156			`output [3:0] cbe_en_out ;`
157
158			`output frame_out ;`
159			`output irdy_out ;`
160			`output devsel_out ;`
161			`output trdy_out ;`
162			`output stop_out ;`
163			`output [3:0] cbe_out ;`
164			`output [31:0] ad_out ;`
165
166			`output par_out ;`
167			`output par_en_out ;`
168			`output perr_out ;`
169			`output perr_en_out ;`
170			`output serr_out ;`
171			`output serr_en_out ;`
172
173			`input req_in ;`
174
175			`output req_out ;`
176			`output req_en_out ;`
177
178
179			`wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;`
180
181			`wire ad_en_ctrl_low ;`
182			`IO_MUX_EN_MULT ad_en_low_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_low)) ;`
183
184			`wire ad_en_ctrl_mlow ;`
185			`IO_MUX_EN_MULT ad_en_mlow_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mlow)) ;`
186
187			`wire ad_en_ctrl_mhigh ;`
188			`IO_MUX_EN_MULT ad_en_mhigh_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_mhigh)) ;`
189
190			`wire ad_en_ctrl_high ;`
191			`IO_MUX_EN_MULT ad_en_high_gen(.mas_ad_en_in(mas_ad_en_in), .tar_ad_en_in(tar_ad_en_in), .ad_en_out(ad_en_ctrl_high)) ;`
192
193			`wire ad_load_ctrl_low ;`
194			`IO_MUX_LOAD_MUX ad_load_low_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_low));`
195
196			`wire ad_load_ctrl_mlow ;`
197			`IO_MUX_LOAD_MUX ad_load_mlow_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mlow));`
198
199			`wire ad_load_ctrl_mhigh ;`
200			`IO_MUX_LOAD_MUX ad_load_mhigh_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_mhigh));`
201
202			`wire ad_load_ctrl_high ;`
203			`IO_MUX_LOAD_MUX ad_load_high_gen(.tar_ad_en_reg_in(tar_ad_en_reg_in), .mas_ad_load_in(master_load_in), .tar_ad_load_in(target_load_in), .ad_load_out(ad_load_ctrl_high)) ;`
204
205			`OUT_REG ad_iob0`
206			`(`
207			`.reset_in ( reset_in ),`
208			`.clk_in ( clk_in) ,`
209			`.dat_en_in ( ad_load_ctrl_low ),`
210			`.en_en_in ( 1'b1 ),`
211			`.dat_in ( temp_ad[0] ) ,`
212			`.en_in ( ad_en_ctrl_low ) ,`
213			`.en_out ( ad_en_out[0] ),`
214			`.dat_out ( ad_out[0] )`
215			`);`
216
217			`OUT_REG ad_iob1`
218			`(`
219			`.reset_in ( reset_in ),`
220			`.clk_in ( clk_in) ,`
221			`.dat_en_in ( ad_load_ctrl_low ),`
222			`.en_en_in ( 1'b1 ),`
223			`.dat_in ( temp_ad[1] ) ,`
224			`.en_in ( ad_en_ctrl_low ) ,`
225			`.en_out ( ad_en_out[1] ),`
226			`.dat_out ( ad_out[1] )`
227			`);`
228
229			`OUT_REG ad_iob2`
230			`(`
231			`.reset_in ( reset_in ),`
232			`.clk_in ( clk_in) ,`
233			`.dat_en_in ( ad_load_ctrl_low ),`
234			`.en_en_in ( 1'b1 ),`
235			`.dat_in ( temp_ad[2] ) ,`
236			`.en_in ( ad_en_ctrl_low ) ,`
237			`.en_out ( ad_en_out[2] ),`
238			`.dat_out ( ad_out[2] )`
239			`);`
240
241			`OUT_REG ad_iob3`
242			`(`
243			`.reset_in ( reset_in ),`
244			`.clk_in ( clk_in) ,`
245			`.dat_en_in ( ad_load_ctrl_low ),`
246			`.en_en_in ( 1'b1 ),`
247			`.dat_in ( temp_ad[3] ) ,`
248			`.en_in ( ad_en_ctrl_low ) ,`
249			`.en_out ( ad_en_out[3] ),`
250			`.dat_out ( ad_out[3] )`
251			`);`
252
253			`OUT_REG ad_iob4`
254			`(`
255			`.reset_in ( reset_in ),`
256			`.clk_in ( clk_in) ,`
257			`.dat_en_in ( ad_load_ctrl_low ),`
258			`.en_en_in ( 1'b1 ),`
259			`.dat_in ( temp_ad[4] ) ,`
260			`.en_in ( ad_en_ctrl_low ) ,`
261			`.en_out ( ad_en_out[4] ),`
262			`.dat_out ( ad_out[4] )`
263			`);`
264
265			`OUT_REG ad_iob5`
266			`(`
267			`.reset_in ( reset_in ),`
268			`.clk_in ( clk_in) ,`
269			`.dat_en_in ( ad_load_ctrl_low ),`
270			`.en_en_in ( 1'b1 ),`
271			`.dat_in ( temp_ad[5] ) ,`
272			`.en_in ( ad_en_ctrl_low ) ,`
273			`.en_out ( ad_en_out[5] ),`
274			`.dat_out ( ad_out[5] )`
275			`);`
276
277			`OUT_REG ad_iob6`
278			`(`
279			`.reset_in ( reset_in ),`
280			`.clk_in ( clk_in) ,`
281			`.dat_en_in ( ad_load_ctrl_low ),`
282			`.en_en_in ( 1'b1 ),`
283			`.dat_in ( temp_ad[6] ) ,`
284			`.en_in ( ad_en_ctrl_low ) ,`
285			`.en_out ( ad_en_out[6] ),`
286			`.dat_out ( ad_out[6] )`
287			`);`
288
289			`OUT_REG ad_iob7`
290			`(`
291			`.reset_in ( reset_in ),`
292			`.clk_in ( clk_in) ,`
293			`.dat_en_in ( ad_load_ctrl_low ),`
294			`.en_en_in ( 1'b1 ),`
295			`.dat_in ( temp_ad[7] ) ,`
296			`.en_in ( ad_en_ctrl_low ) ,`
297			`.en_out ( ad_en_out[7] ),`
298			`.dat_out ( ad_out[7] )`
299			`);`
300
301			`OUT_REG ad_iob8`
302			`(`
303			`.reset_in ( reset_in ),`
304			`.clk_in ( clk_in) ,`
305			`.dat_en_in ( ad_load_ctrl_mlow ),`
306			`.en_en_in ( 1'b1 ),`
307			`.dat_in ( temp_ad[8] ) ,`
308			`.en_in ( ad_en_ctrl_mlow ) ,`
309			`.en_out ( ad_en_out[8] ),`
310			`.dat_out ( ad_out[8] )`
311			`);`
312
313			`OUT_REG ad_iob9`
314			`(`
315			`.reset_in ( reset_in ),`
316			`.clk_in ( clk_in) ,`
317			`.dat_en_in ( ad_load_ctrl_mlow ),`
318			`.en_en_in ( 1'b1 ),`
319			`.dat_in ( temp_ad[9] ) ,`
320			`.en_in ( ad_en_ctrl_mlow ) ,`
321			`.en_out ( ad_en_out[9] ),`
322			`.dat_out ( ad_out[9] )`
323			`);`
324
325			`OUT_REG ad_iob10`
326			`(`
327			`.reset_in ( reset_in ),`
328			`.clk_in ( clk_in) ,`
329			`.dat_en_in ( ad_load_ctrl_mlow ),`
330			`.en_en_in ( 1'b1 ),`
331			`.dat_in ( temp_ad[10] ) ,`
332			`.en_in ( ad_en_ctrl_mlow ) ,`
333			`.en_out ( ad_en_out[10] ),`
334			`.dat_out ( ad_out[10] )`
335			`);`
336
337			`OUT_REG ad_iob11`
338			`(`
339			`.reset_in ( reset_in ),`
340			`.clk_in ( clk_in) ,`
341			`.dat_en_in ( ad_load_ctrl_mlow ),`
342			`.en_en_in ( 1'b1 ),`
343			`.dat_in ( temp_ad[11] ) ,`
344			`.en_in ( ad_en_ctrl_mlow ) ,`
345			`.en_out ( ad_en_out[11] ),`
346			`.dat_out ( ad_out[11] )`
347			`);`
348
349			`OUT_REG ad_iob12`
350			`(`
351			`.reset_in ( reset_in ),`
352			`.clk_in ( clk_in) ,`
353			`.dat_en_in ( ad_load_ctrl_mlow ),`
354			`.en_en_in ( 1'b1 ),`
355			`.dat_in ( temp_ad[12] ) ,`
356			`.en_in ( ad_en_ctrl_mlow ) ,`
357			`.en_out ( ad_en_out[12] ),`
358			`.dat_out ( ad_out[12] )`
359			`);`
360
361			`OUT_REG ad_iob13`
362			`(`
363			`.reset_in ( reset_in ),`
364			`.clk_in ( clk_in) ,`
365			`.dat_en_in ( ad_load_ctrl_mlow ),`
366			`.en_en_in ( 1'b1 ),`
367			`.dat_in ( temp_ad[13] ) ,`
368			`.en_in ( ad_en_ctrl_mlow ) ,`
369			`.en_out ( ad_en_out[13] ),`
370			`.dat_out ( ad_out[13] )`
371			`);`
372
373			`OUT_REG ad_iob14`
374			`(`
375			`.reset_in ( reset_in ),`
376			`.clk_in ( clk_in) ,`
377			`.dat_en_in ( ad_load_ctrl_mlow ),`
378			`.en_en_in ( 1'b1 ),`
379			`.dat_in ( temp_ad[14] ) ,`
380			`.en_in ( ad_en_ctrl_mlow ) ,`
381			`.en_out ( ad_en_out[14] ),`
382			`.dat_out ( ad_out[14] )`
383			`);`
384
385			`OUT_REG ad_iob15`
386			`(`
387			`.reset_in ( reset_in ),`
388			`.clk_in ( clk_in) ,`
389			`.dat_en_in ( ad_load_ctrl_mlow ),`
390			`.en_en_in ( 1'b1 ),`
391			`.dat_in ( temp_ad[15] ) ,`
392			`.en_in ( ad_en_ctrl_mlow ) ,`
393			`.en_out ( ad_en_out[15] ),`
394			`.dat_out ( ad_out[15] )`
395			`);`
396
397			`OUT_REG ad_iob16`
398			`(`
399			`.reset_in ( reset_in ),`
400			`.clk_in ( clk_in) ,`
401			`.dat_en_in ( ad_load_ctrl_mhigh ),`
402			`.en_en_in ( 1'b1 ),`
403			`.dat_in ( temp_ad[16] ) ,`
404			`.en_in ( ad_en_ctrl_mhigh ) ,`
405			`.en_out ( ad_en_out[16] ),`
406			`.dat_out ( ad_out[16] )`
407			`);`
408
409			`OUT_REG ad_iob17`
410			`(`
411			`.reset_in ( reset_in ),`
412			`.clk_in ( clk_in) ,`
413			`.dat_en_in ( ad_load_ctrl_mhigh ),`
414			`.en_en_in ( 1'b1 ),`
415			`.dat_in ( temp_ad[17] ) ,`
416			`.en_in ( ad_en_ctrl_mhigh ) ,`
417			`.en_out ( ad_en_out[17] ),`
418			`.dat_out ( ad_out[17] )`
419			`);`
420
421			`OUT_REG ad_iob18`
422			`(`
423			`.reset_in ( reset_in ),`
424			`.clk_in ( clk_in) ,`
425			`.dat_en_in ( ad_load_ctrl_mhigh ),`
426			`.en_en_in ( 1'b1 ),`
427			`.dat_in ( temp_ad[18] ) ,`
428			`.en_in ( ad_en_ctrl_mhigh ) ,`
429			`.en_out ( ad_en_out[18] ),`
430			`.dat_out ( ad_out[18] )`
431			`);`
432
433			`OUT_REG ad_iob19`
434			`(`
435			`.reset_in ( reset_in ),`
436			`.clk_in ( clk_in) ,`
437			`.dat_en_in ( ad_load_ctrl_mhigh ),`
438			`.en_en_in ( 1'b1 ),`
439			`.dat_in ( temp_ad[19] ) ,`
440			`.en_in ( ad_en_ctrl_mhigh ) ,`
441			`.en_out ( ad_en_out[19] ),`
442			`.dat_out ( ad_out[19] )`
443			`);`
444
445			`OUT_REG ad_iob20`
446			`(`
447			`.reset_in ( reset_in ),`
448			`.clk_in ( clk_in) ,`
449			`.dat_en_in ( ad_load_ctrl_mhigh ),`
450			`.en_en_in ( 1'b1 ),`
451			`.dat_in ( temp_ad[20] ) ,`
452			`.en_in ( ad_en_ctrl_mhigh ) ,`
453			`.en_out ( ad_en_out[20] ),`
454			`.dat_out ( ad_out[20] )`
455			`);`
456
457			`OUT_REG ad_iob21`
458			`(`
459			`.reset_in ( reset_in ),`
460			`.clk_in ( clk_in) ,`
461			`.dat_en_in ( ad_load_ctrl_mhigh ),`
462			`.en_en_in ( 1'b1 ),`
463			`.dat_in ( temp_ad[21] ) ,`
464			`.en_in ( ad_en_ctrl_mhigh ) ,`
465			`.en_out ( ad_en_out[21] ),`
466			`.dat_out ( ad_out[21] )`
467			`);`
468
469			`OUT_REG ad_iob22`
470			`(`
471			`.reset_in ( reset_in ),`
472			`.clk_in ( clk_in) ,`
473			`.dat_en_in ( ad_load_ctrl_mhigh ),`
474			`.en_en_in ( 1'b1 ),`
475			`.dat_in ( temp_ad[22] ) ,`
476			`.en_in ( ad_en_ctrl_mhigh ) ,`
477			`.en_out ( ad_en_out[22] ),`
478			`.dat_out ( ad_out[22] )`
479			`);`
480
481			`OUT_REG ad_iob23`
482			`(`
483			`.reset_in ( reset_in ),`
484			`.clk_in ( clk_in) ,`
485			`.dat_en_in ( ad_load_ctrl_mhigh ),`
486			`.en_en_in ( 1'b1 ),`
487			`.dat_in ( temp_ad[23] ) ,`
488			`.en_in ( ad_en_ctrl_mhigh ) ,`
489			`.en_out ( ad_en_out[23] ),`
490			`.dat_out ( ad_out[23] )`
491			`);`
492
493			`OUT_REG ad_iob24`
494			`(`
495			`.reset_in ( reset_in ),`
496			`.clk_in ( clk_in) ,`
497			`.dat_en_in ( ad_load_ctrl_high ),`
498			`.en_en_in ( 1'b1 ),`
499			`.dat_in ( temp_ad[24] ) ,`
500			`.en_in ( ad_en_ctrl_high ) ,`
501			`.en_out ( ad_en_out[24] ),`
502			`.dat_out ( ad_out[24] )`
503			`);`
504
505			`OUT_REG ad_iob25`
506			`(`
507			`.reset_in ( reset_in ),`
508			`.clk_in ( clk_in) ,`
509			`.dat_en_in ( ad_load_ctrl_high ),`
510			`.en_en_in ( 1'b1 ),`
511			`.dat_in ( temp_ad[25] ) ,`
512			`.en_in ( ad_en_ctrl_high ) ,`
513			`.en_out ( ad_en_out[25] ),`
514			`.dat_out ( ad_out[25] )`
515			`);`
516
517			`OUT_REG ad_iob26`
518			`(`
519			`.reset_in ( reset_in ),`
520			`.clk_in ( clk_in) ,`
521			`.dat_en_in ( ad_load_ctrl_high ),`
522			`.en_en_in ( 1'b1 ),`
523			`.dat_in ( temp_ad[26] ) ,`
524			`.en_in ( ad_en_ctrl_high ) ,`
525			`.en_out ( ad_en_out[26] ),`
526			`.dat_out ( ad_out[26] )`
527			`);`
528
529			`OUT_REG ad_iob27`
530			`(`
531			`.reset_in ( reset_in ),`
532			`.clk_in ( clk_in) ,`
533			`.dat_en_in ( ad_load_ctrl_high ),`
534			`.en_en_in ( 1'b1 ),`
535			`.dat_in ( temp_ad[27] ) ,`
536			`.en_in ( ad_en_ctrl_high ) ,`
537			`.en_out ( ad_en_out[27] ),`
538			`.dat_out ( ad_out[27] )`
539			`);`
540
541			`OUT_REG ad_iob28`
542			`(`
543			`.reset_in ( reset_in ),`
544			`.clk_in ( clk_in) ,`
545			`.dat_en_in ( ad_load_ctrl_high ),`
546			`.en_en_in ( 1'b1 ),`
547			`.dat_in ( temp_ad[28] ) ,`
548			`.en_in ( ad_en_ctrl_high ) ,`
549			`.en_out ( ad_en_out[28] ),`
550			`.dat_out ( ad_out[28] )`
551			`);`
552
553			`OUT_REG ad_iob29`
554			`(`
555			`.reset_in ( reset_in ),`
556			`.clk_in ( clk_in) ,`
557			`.dat_en_in ( ad_load_ctrl_high ),`
558			`.en_en_in ( 1'b1 ),`
559			`.dat_in ( temp_ad[29] ) ,`
560			`.en_in ( ad_en_ctrl_high ) ,`
561			`.en_out ( ad_en_out[29] ),`
562			`.dat_out ( ad_out[29] )`
563			`);`
564
565			`OUT_REG ad_iob30`
566			`(`
567			`.reset_in ( reset_in ),`
568			`.clk_in ( clk_in) ,`
569			`.dat_en_in ( ad_load_ctrl_high ),`
570			`.en_en_in ( 1'b1 ),`
571			`.dat_in ( temp_ad[30] ) ,`
572			`.en_in ( ad_en_ctrl_high ) ,`
573			`.en_out ( ad_en_out[30] ),`
574			`.dat_out ( ad_out[30] )`
575			`);`
576
577			`OUT_REG ad_iob31`
578			`(`
579			`.reset_in ( reset_in ),`
580			`.clk_in ( clk_in) ,`
581			`.dat_en_in ( ad_load_ctrl_high ),`
582			`.en_en_in ( 1'b1 ),`
583			`.dat_in ( temp_ad[31] ) ,`
584			`.en_in ( ad_en_ctrl_high ) ,`
585			`.en_out ( ad_en_out[31] ),`
586			`.dat_out ( ad_out[31] )`
587			`);`
588
589			`wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;`
590			`wire [3:0] cbe_en_ctrl = {4{ cbe_en_in }} ;`
591
592			`OUT_REG cbe_iob0`
593			`(`
594			`.reset_in ( reset_in ),`
595			`.clk_in ( clk_in) ,`
596			`.dat_en_in ( cbe_load_ctrl[0] ),`
597			`.en_en_in ( 1'b1 ),`
598			`.dat_in ( cbe_in[0] ) ,`
599			`.en_in ( cbe_en_ctrl[0] ) ,`
600			`.en_out ( cbe_en_out[0] ),`
601			`.dat_out ( cbe_out[0] )`
602			`);`
603
604			`OUT_REG cbe_iob1`
605			`(`
606			`.reset_in ( reset_in ),`
607			`.clk_in ( clk_in) ,`
608			`.dat_en_in ( cbe_load_ctrl[1] ),`
609			`.en_en_in ( 1'b1 ),`
610			`.dat_in ( cbe_in[1] ) ,`
611			`.en_in ( cbe_en_ctrl[1] ) ,`
612			`.en_out ( cbe_en_out[1] ),`
613			`.dat_out ( cbe_out[1] )`
614			`);`
615
616			`OUT_REG cbe_iob2`
617			`(`
618			`.reset_in ( reset_in ),`
619			`.clk_in ( clk_in) ,`
620			`.dat_en_in ( cbe_load_ctrl[2] ),`
621			`.en_en_in ( 1'b1 ),`
622			`.dat_in ( cbe_in[2] ) ,`
623			`.en_in ( cbe_en_ctrl[2] ) ,`
624			`.en_out ( cbe_en_out[2] ),`
625			`.dat_out ( cbe_out[2] )`
626			`);`
627
628			`OUT_REG cbe_iob3`
629			`(`
630			`.reset_in ( reset_in ),`
631			`.clk_in ( clk_in) ,`
632			`.dat_en_in ( cbe_load_ctrl[3] ),`
633			`.en_en_in ( 1'b1 ),`
634			`.dat_in ( cbe_in[3] ) ,`
635			`.en_in ( cbe_en_ctrl[3] ) ,`
636			`.en_out ( cbe_en_out[3] ),`
637			`.dat_out ( cbe_out[3] )`
638			`);`
639
640			`OUT_REG frame_iob`
641			`(`
642			`.reset_in ( reset_in ),`
643			`.clk_in ( clk_in) ,`
644			`.dat_en_in ( frame_load_in ),`
645			`.en_en_in ( 1'b1 ),`
646			`.dat_in ( frame_in ) ,`
647			`.en_in ( frame_en_in ) ,`
648			`.en_out ( frame_en_out ),`
649			`.dat_out ( frame_out )`
650			`);`
651
652			`OUT_REG irdy_iob`
653			`(`
654			`.reset_in ( reset_in ),`
655			`.clk_in ( clk_in) ,`
656			`.dat_en_in ( 1'b1 ),`
657			`.en_en_in ( 1'b1 ),`
658			`.dat_in ( irdy_in ) ,`
659			`.en_in ( irdy_en_in ) ,`
660			`.en_out ( irdy_en_out ),`
661			`.dat_out ( irdy_out )`
662			`);`
663
664			`OUT_REG trdy_iob`
665			`(`
666			`.reset_in ( reset_in ),`
667			`.clk_in ( clk_in) ,`
668			`.dat_en_in ( 1'b1 ),`
669			`.en_en_in ( 1'b1 ),`
670			`.dat_in ( trdy_in ) ,`
671			`.en_in ( trdy_en_in ) ,`
672			`.en_out ( trdy_en_out ),`
673			`.dat_out ( trdy_out )`
674			`);`
675
676			`OUT_REG stop_iob`
677			`(`
678			`.reset_in ( reset_in ),`
679			`.clk_in ( clk_in) ,`
680			`.dat_en_in ( 1'b1 ),`
681			`.en_en_in ( 1'b1 ),`
682			`.dat_in ( stop_in ) ,`
683			`.en_in ( stop_en_in ) ,`
684			`.en_out ( stop_en_out ),`
685			`.dat_out ( stop_out )`
686			`);`
687
688			`OUT_REG devsel_iob`
689			`(`
690			`.reset_in ( reset_in ),`
691			`.clk_in ( clk_in) ,`
692			`.dat_en_in ( 1'b1 ),`
693			`.en_en_in ( 1'b1 ),`
694			`.dat_in ( devsel_in ) ,`
695			`.en_in ( devsel_en_in ) ,`
696			`.en_out ( devsel_en_out ),`
697			`.dat_out ( devsel_out )`
698			`);`
699
700			`OUT_REG par_iob`
701			`(`
702			`.reset_in ( reset_in ),`
703			`.clk_in ( clk_in) ,`
704			`.dat_en_in ( 1'b1 ),`
705			`.en_en_in ( 1'b1 ),`
706			`.dat_in ( par_in ) ,`
707			`.en_in ( par_en_in ) ,`
708			`.en_out ( par_en_out ),`
709			`.dat_out ( par_out )`
710			`);`
711
712			`OUT_REG perr_iob`
713			`(`
714			`.reset_in ( reset_in ),`
715			`.clk_in ( clk_in) ,`
716			`.dat_en_in ( 1'b1 ),`
717			`.en_en_in ( 1'b1 ),`
718			`.dat_in ( perr_in ) ,`
719			`.en_in ( perr_en_in ) ,`
720			`.en_out ( perr_en_out ),`
721			`.dat_out ( perr_out )`
722			`);`
723
724			`OUT_REG serr_iob`
725			`(`
726			`.reset_in ( reset_in ),`
727			`.clk_in ( clk_in) ,`
728			`.dat_en_in ( 1'b1 ),`
729			`.en_en_in ( 1'b1 ),`
730			`.dat_in ( serr_in ) ,`
731			`.en_in ( serr_en_in ) ,`
732			`.en_out ( serr_en_out ),`
733			`.dat_out ( serr_out )`
734			`);`
735
736			`OUT_REG req_iob`
737			`(`
738			`.reset_in ( reset_in ),`
739			`.clk_in ( clk_in) ,`
740			`.dat_en_in ( 1'b1 ),`
741			`.en_en_in ( 1'b1 ),`
742			`.dat_in ( req_in ) ,`
743			`.en_in ( 1'b1 ) ,`
744			`.en_out ( req_en_out ),`
745			`.dat_out ( req_out )`
746			`);`
747
748			`endmodule`