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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_master32_sm_if.v"                            ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/10/05 08:14:29  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
`include "pci_constants.v"
`include "bus_commands.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
/*====================================================================
Module provides interface between PCI bridge internals and PCI master
state machine
====================================================================*/
module PCI_MASTER32_SM_IF
(
    clk_in,
    reset_in,
 
    // interconnect to pci master state machine
    address_out,
    bc_out,
    data_out,
    data_in,
    be_out,
    req_out,
    rdy_out,
    last_out,
 
    next_data_out,
    next_be_out,
    next_last_out,
 
    // status inputs from master SM
    wait_in,
    wtransfer_in,
    rtransfer_in,
    retry_in,
    rerror_in,
    first_in ,
    mabort_in,
 
 
    // WISHBONE WRITE fifo inputs and outputs
    wbw_renable_out,
    wbw_fifo_addr_data_in,
    wbw_fifo_cbe_in,
    wbw_fifo_control_in,
    wbw_fifo_empty_in,
    wbw_fifo_transaction_ready_in,
 
    // WISHBONE READ fifo inputs and outputs
    wbr_fifo_wenable_out,
    wbr_fifo_data_out,
    wbr_fifo_be_out,
    wbr_fifo_control_out,
 
    // delayed transaction control logic inputs and outputs
    del_wdata_in,
    del_complete_out,
    del_req_in,
    del_addr_in,
    del_bc_in,
    del_be_in,
    del_burst_in,
    del_error_out,
    del_rty_exp_out,
    del_we_in,
 
    // configuration space interconnect
    // error reporting
    err_addr_out,
    err_bc_out,
    err_signal_out,
    err_source_out,
    err_rty_exp_out,
 
    cache_line_size_in,
 
    // two signals for pci control and status
    mabort_received_out,
    tabort_received_out,
 
    posted_write_not_present_out
);
 
// system inputs
input clk_in ;
input reset_in ;
 
// PCI master state machine interconnect
output  [31:0]  address_out ;   // address output
 
output  [3:0]   bc_out ;        // bus command output
reg     [3:0]   bc_out ;
 
output  [31:0]  data_out ;      // data output for writes
reg     [31:0]  data_out ;
 
input   [31:0]  data_in ;       // data input for reads
output  [3:0]   be_out  ;       // byte enable output
reg     [3:0]   be_out  ;
 
output          req_out ;       // request output
 
output          rdy_out ;       // ready output
reg             rdy_out ;
 
output          last_out ;      // last data indicator output
 
output  [31:0]  next_data_out ; // next data output
output  [3:0]   next_be_out ;   // next byte enable output
output          next_last_out ; // next transfer last indicator
 
input           wait_in,
                wtransfer_in,
                rtransfer_in,
                retry_in,
                rerror_in,
                first_in ,
                mabort_in ;
 
// WISHBONE write fifo interconnect
output          wbw_renable_out ;          // WBW_FIFO read enable signal
 
input   [31:0]  wbw_fifo_addr_data_in ;         // WBW_FIFO address/data bus
input   [3:0]   wbw_fifo_cbe_in ;               // WBW_FIFO command/byte enable bus
input   [3:0]   wbw_fifo_control_in ;           // WBW_FIFO control bus
input           wbw_fifo_empty_in ;             // WBW_FIFO's empty status indicator
input           wbw_fifo_transaction_ready_in ; // WBW_FIFO transaction ready indicator
 
// WISHBONE read FIFO interconnect
output          wbr_fifo_wenable_out ;          // write enable for WBR_FIFO
 
output  [31:0]  wbr_fifo_data_out ;             // data output to WBR_FIFO
 
output  [3:0]   wbr_fifo_be_out ;               // byte enable output for WBR_FIFO
 
output  [3:0]   wbr_fifo_control_out ;          // WBR_FIFO control output
 
// delayed transaction control logic inputs and outputs
input   [31:0]  del_wdata_in ;                  // delayed write data input
output          del_complete_out ;              // delayed transaction completed output
 
input           del_req_in ;                    // delayed transaction request
input   [31:0]  del_addr_in ;                   // delayed transaction address
input   [3:0]   del_bc_in ;                     // delayed transaction bus command input
input   [3:0]   del_be_in ;                     // delayed transaction byte enables input
input           del_burst_in ;                  // delayed transaction burst req. indicator
output          del_error_out ;                 // delayed transation error termination signal
 
output          del_rty_exp_out ;               // retry expired output for delayed transactions
 
input           del_we_in ;                     // delayed write request indicator
 
output  [31:0]  err_addr_out ;                  // erroneous address output
output  [3:0]   err_bc_out ;                    // erroneous bus command output
 
output          err_signal_out ;                // error signalization
 
output          err_source_out ;                // error source indicator
 
input   [7:0]   cache_line_size_in ;            // cache line size value input
 
output          err_rty_exp_out ;               // retry expired error output
 
output          mabort_received_out ;           // master abort signaled to status register
output          tabort_received_out ;           // target abort signaled to status register
 
output          posted_write_not_present_out ;  // used in target state machine - must deny read completions when this signal is 0
 
 
assign err_bc_out   = bc_out ;
 
// assign read outputs
/*==================================================================================================================
WISHBONE read FIFO data outputs - just link them to SM data outputs and delayed BE input
==================================================================================================================*/
assign wbr_fifo_data_out = data_in ;
assign wbr_fifo_be_out   = del_be_in ;
 
// decode if current bus command is configuration command
wire conf_cyc_bc = ( bc_out[3:1] == `BC_CONF_RW ) ;
 
// register for indicating that current data is also last in transfer
reg current_last ;
 
// register indicating that last data was transfered OK
reg last_transfered ;
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        last_transfered <= #`FF_DELAY 1'b0 ;
    else
        last_transfered <= #`FF_DELAY ~wait_in && last_out && wtransfer_in ;
end
 
// status signals output assignement
assign mabort_received_out = mabort_in ;
 
wire tabort_ff_in = ~wait_in && rerror_in ;
 
reg    tabort_received_out ;
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        tabort_received_out <= #`FF_DELAY 1'b0 ;
    else
        tabort_received_out <= #`FF_DELAY tabort_ff_in ;
end
 
// error recovery indicator
reg err_recovery ;
 
// operation is locked until error recovery is in progress or error bit is not cleared in configuration space
wire err_lock = err_recovery ;
 
// three requests are possible - posted write, delayed write and delayed read
reg del_write_req ;
reg posted_write_req ;
reg del_read_req ;
 
// assign request output
assign req_out = del_write_req || posted_write_req || del_read_req ;
 
// posted write is not present, when WB Write Fifo is empty and posted write transaction is not beeing requested at present time
assign posted_write_not_present_out = !posted_write_req && wbw_fifo_empty_in ;
 
// write requests are staged, so data is read from source into current data register and next data register
reg write_req_int ;
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        write_req_int <= #`FF_DELAY 1'b0 ;
    else
        write_req_int <= #`FF_DELAY posted_write_req || del_write_req ;
 
end
 
// ready output is generated one clock after request for reads and two after for writes
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        rdy_out <= #`FF_DELAY 1'b0 ;
    else
        rdy_out <= #`FF_DELAY del_read_req || ( (posted_write_req || del_write_req) && write_req_int) ;
end
 
// wires with logic used as inputs to request FFs
wire do_posted_write = ( wbw_fifo_transaction_ready_in && ~wbw_fifo_empty_in && ~err_lock ) ;
wire do_del          = ( del_req_in && ~err_lock && wbw_fifo_empty_in ) ;
wire do_del_write    = do_del &&  del_we_in ;
wire do_del_read     = do_del && ~del_we_in ;
 
// register for indicating current operation's data source
parameter DELAYED_WRITE = 1'b1 ;
parameter POSTED_WRITE  = 1'b0 ;
 
// new data source - depending on which transaction will be processed next - delayed read is here because source of byte enables must
// be specified for delayed reads also - data source is not relevant for delayed reads, so value is don't care anyway
wire new_data_source = (do_del_write || do_del_read) ? DELAYED_WRITE : POSTED_WRITE ; // input to data source register
wire data_source_change = ~req_out ;    // change (enable) for data source register - when no requests are in progress
 
reg data_source ;           // data source value
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        // default value is posted write source - wbw_fifo
        data_source <= #`FF_DELAY POSTED_WRITE ;
    else
    if (data_source_change)
        // change data source on rising clock edge
        data_source <= #`FF_DELAY new_data_source ;
end
 
// multiplexer for data output to PCI MASTER state machine
reg [31:0] source_data ;
reg [3:0]  source_be ;
always@(data_source or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or del_wdata_in or del_be_in or del_burst_in)
begin
    case (data_source)
        POSTED_WRITE:   begin
                            source_data = wbw_fifo_addr_data_in ;
                            source_be   = wbw_fifo_cbe_in ;
                        end
        DELAYED_WRITE:  begin
                            source_data = del_wdata_in ;
                            // read all bytes during delayed burst read!
                            source_be   = ~( del_be_in | {4{del_burst_in}} ) ;
                        end
    endcase
end
 
wire            waddr =  wbw_fifo_control_in[`ADDR_CTRL_BIT] ;
 
// address change indicator - address is allowed to be loaded only when no transaction is in progress!
wire            address_change = ~req_out ; // address change - whenever there is no request in progress
 
// new address - input to register storing address of current request - if posted write request will be next,
// load address and bus command from wbw_fifo, else load data from delayed transaction logic
wire     [31:0] new_address = ( ~req_out && do_posted_write ) ? wbw_fifo_addr_data_in[31:0] : del_addr_in[31:0] ;
wire     [3:0]  new_bc      = ( ~req_out && do_posted_write ) ? wbw_fifo_cbe_in : del_bc_in ;
 
// address counter enable - only for posted writes when data is actually transfered
wire addr_count_en = ~wait_in && posted_write_req && rtransfer_in ;
 
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        bc_out <= #`FF_DELAY `BC_RESERVED0 ;
    else
    if (address_change)
        bc_out <= #`FF_DELAY new_bc ;
end
 
reg [29:0] current_dword_address ;
 
// DWORD address counter with load
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        current_dword_address <= #`FF_DELAY 30'h0000_0000 ;
    else
    if (address_change)
        current_dword_address <= #`FF_DELAY new_address[31:2] ;
    else
    if (addr_count_en)
        current_dword_address <= #`FF_DELAY current_dword_address + 1'b1 ;
end
 
reg [1:0] current_byte_address ;
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        current_byte_address <= #`FF_DELAY 2'b00 ;
    else
    if (address_change)
        current_byte_address <= #`FF_DELAY new_address[1:0] ;
end
 
// address output to PCI master state machine assignement
assign address_out  = { current_dword_address, current_byte_address } ;
 
// the same for erroneous address assignement
assign err_addr_out = { current_dword_address, current_byte_address } ;
 
// cacheline size counter - for read transaction length control
// cache line count is enabled during burst reads when data is actually transfered
wire read_count_enable = ~wait_in && del_read_req && del_burst_in && wtransfer_in  ;
 
// cache line counter is loaded when del read request is not in progress
wire read_count_load   = ~del_read_req ;
 
reg [(`WBR_ADDR_LENGTH - 1):0] max_read_count ;
always@(cache_line_size_in or del_bc_in)
begin
    if ( (cache_line_size_in >= `WBR_DEPTH) || (~del_bc_in[1] && ~del_bc_in[0]) )
        max_read_count = `WBR_DEPTH - 1'b1;
    else
        max_read_count = cache_line_size_in ;
end
 
reg [(`WBR_ADDR_LENGTH - 1):0] read_count ;
 
// cache line bound indicator - it signals when data for one complete cacheline was read
wire read_bound_comb = ~|(read_count[(`WBR_ADDR_LENGTH - 1):2]) ;
reg  read_bound ;
always@(posedge clk_in or posedge reset_in)
begin
    if ( reset_in )
        read_bound <= #`FF_DELAY 1'b0 ;
    else if (read_count_load)
        read_bound <= #`FF_DELAY 1'b0 ;
    else if ( read_count_enable )
        read_bound <= #`FF_DELAY read_bound_comb ;
end
 
// down counter with load
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        read_count <= #`FF_DELAY 0 ;
    else
    if (read_count_load)
        read_count <= #`FF_DELAY max_read_count ;
    else
    if (read_count_enable)
        read_count <= #`FF_DELAY read_count - 1'b1 ;
 
end
 
// flip flop indicating error recovery is in progress
reg err_recovery_in ;
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        err_recovery <= #`FF_DELAY 1'b0 ;
    else
        err_recovery <= #`FF_DELAY err_recovery_in ;
end
 
/*// retry counter implementation
reg [7:0] retry_count ;
 
wire retry_expired = ~|(retry_count[7:1]) ;
 
// loading of retry counter - whenever no request is present or other termination than retry or wait is signalled
wire retry_load = ~req_out || (~wait_in && rtransfer_in) ;
 
// retry DOWN counter with load
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        retry_count <= #`FF_DELAY 8'hFF ;
    else
    if ( retry_load )
        retry_count <= #`FF_DELAY `PCI_RTY_CNT_MAX ;
    else
    if (retry_in)
        retry_count <= #`FF_DELAY retry_count - 1'b1 ;
end*/
 
/*==================================================================================================================
Delayed write requests are always single transfers!
Delayed write request starts, when no request is currently beeing processed and it is signaled from other side
of the bridge.
==================================================================================================================*/
// delayed write request FF input control
reg del_write_req_input ;
 
always@(
    do_del_write or
    del_write_req or
    posted_write_req or
    del_read_req or
    wait_in or
    //retry_in or
    //retry_expired or
    rtransfer_in or
    rerror_in or
    mabort_in
)
begin
    if (~del_write_req)
    begin
        // delayed write is not in progress and is requested
        // delayed write can be requested when no other request is in progress
        del_write_req_input = ~posted_write_req && ~del_read_req && do_del_write ;
    end
    else
    begin
        // delayed write request is in progress - assign input
        del_write_req_input = wait_in ||
                              ( /*~( retry_in && retry_expired) &&*/
                                ~rtransfer_in && ~rerror_in && ~mabort_in
                              );
    end
end
 
// delayed write request FLIP-FLOP
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        del_write_req <= #`FF_DELAY 1'b0 ;
    else
        del_write_req <= #`FF_DELAY del_write_req_input ;
end
 
/*================================================================================================
Posted write request indicator.
Posted write starts whenever no request is in progress and one whole posted write is
stored in WBW_FIFO. It ends on error terminations ( master, target abort, retry expired) or
data transfer terminations if last data is on top of FIFO.
Continues on wait, retry, and disconnect without data.
================================================================================================*/
// posted write request FF input control
reg posted_write_req_input ;
always@(
    do_posted_write or
    del_write_req or
    posted_write_req or
    del_read_req or
    wait_in or
    //retry_in or
    rerror_in or
    mabort_in or
    //retry_expired or
    rtransfer_in or
    last_transfered
)
begin
    if (~posted_write_req)
    begin
        // posted write is not in progress
        posted_write_req_input = ~del_write_req && ~del_read_req && do_posted_write ;
    end
    else
    begin
        posted_write_req_input = wait_in ||
                                 (/*~(retry_in && retry_expired && ~rtransfer_in) &&*/
                                  ~rerror_in && ~mabort_in &&
                                  ~(last_transfered)
                                 ) ;
 
    end
end
 
// posted write request flip flop
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        posted_write_req <= #`FF_DELAY 1'b0 ;
    else
        posted_write_req <= #`FF_DELAY posted_write_req_input ;
 
end
 
/*================================================================================================
Delayed read request indicator.
Delayed read starts whenever no request is in progress and delayed read request is signaled from
other side of bridge. It ends on error terminations ( master, target abort, retry expired) or
data transfer terminations if it is not burst transfer or on cache line bounds on burst transfer.
It also ends on disconnects.
Continues on wait and retry.
================================================================================================*/
// delayed read FF input control
reg del_read_req_input ;
always@(
    do_del_read or
    del_write_req or
    posted_write_req or
    del_read_req or
    last_transfered or
    wait_in or
    retry_in or
    //retry_expired or
    mabort_in or
    rtransfer_in or
    rerror_in or
    first_in or
    del_complete_out
)
begin
    if (~del_read_req)
    begin
        del_read_req_input = ~del_write_req && ~posted_write_req && ~del_complete_out && do_del_read ;
    end
    else
    begin
        del_read_req_input = wait_in ||
                             ( ~(retry_in && (~first_in /*|| retry_expired */)) &&
                               ~mabort_in && ~rerror_in &&
                               ~(last_transfered)
                             ) ;
    end
end
 
// delayed read request FF
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        del_read_req <= #`FF_DELAY 1'b0 ;
    else
        del_read_req <= #`FF_DELAY del_read_req_input ;
end
 
// wire indicating last entry of transaction on top of fifo
wire wlast = wbw_fifo_control_in[`LAST_CTRL_BIT] ;
 
wire last_int = posted_write_req && wlast || del_write_req ;
 
// intermidiate data, byte enable and last registers
reg [31:0] intermediate_data ;
reg  [3:0] intermediate_be ;
reg        intermediate_last ;
 
wire intermediate_enable = ( posted_write_req || del_write_req ) && ( ~write_req_int || (( ~rdy_out || ~wait_in && rtransfer_in ) && ~intermediate_last)) ;
 
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
    begin
        intermediate_data <= #`FF_DELAY 32'h0000_0000 ;
        intermediate_be   <= #`FF_DELAY 4'h0 ;
        intermediate_last <= #`FF_DELAY 1'b0 ;
    end
    else
    if ( intermediate_enable )
    begin
        intermediate_data <= #`FF_DELAY source_data ;
        intermediate_be   <= #`FF_DELAY source_be ;
        intermediate_last <= #`FF_DELAY last_int ;
    end
end
 
// multiplexer for next data
reg [31:0] next_data_out ;
reg [3:0] next_be_out   ;
reg write_next_last ;
reg [3:0] write_next_be ;
 
always@(rtransfer_in or intermediate_data or intermediate_be or intermediate_last or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or wlast)
begin
    if( rtransfer_in )
    begin
        next_data_out   = wbw_fifo_addr_data_in ;
        write_next_last = wlast ;
        write_next_be   = wbw_fifo_cbe_in ;
    end
    else
    begin
        next_data_out   = intermediate_data ;
        write_next_last = intermediate_last ;
        write_next_be   = intermediate_be ;
    end
end
 
always@(del_read_req or source_be or write_next_be)
begin
    if (del_read_req)
        next_be_out = source_be ;
    else
        next_be_out = write_next_be ;
end
/*================================================================================================
WBW_FIFO read enable - read from WBW_FIFO is performed on posted writes, when data transfer
termination is received - transfer or disconnect with data. Reads are enabled during error
recovery also, since erroneous transaction must be pulled out of FIFO!
================================================================================================*/
// wbw_fifo read enable input control
 
assign wbw_renable_out = ~req_out && (do_posted_write || err_recovery) ||
                              posted_write_req && ( ~write_req_int || (~rdy_out && ~intermediate_last) || (~wait_in && rtransfer_in && ~intermediate_last)) ;
 
/*================================================================================================
WBR_FIFO write enable control -
writes to FIFO are possible only when delayed read request is in progress and data transfer
or error termination is signalled. It is not enabled on retry or disconnect without data.
================================================================================================*/
// wbr_fifo write enable control - enabled when transfer is in progress and data is transfered or error is signalled
assign wbr_fifo_wenable_out = del_read_req && ~wait_in && ( rtransfer_in || mabort_in || rerror_in ) ;
 
/*================================================================================================
WBR_FIFO control output for identifying data entries.
This is necesary because of prefetched reads, which partially succeed. On error, error entry
gets in to signal it on WISHBONE bus if WISHBONE master reads up to this entry.
================================================================================================*/
assign wbr_fifo_control_out[`ADDR_CTRL_BIT]       = 1'b0 ;
assign wbr_fifo_control_out[`LAST_CTRL_BIT]       = last_transfered ;
assign wbr_fifo_control_out[`DATA_ERROR_CTRL_BIT] = rerror_in || (mabort_in && ~conf_cyc_bc) ;
assign wbr_fifo_control_out[`UNUSED_CTRL_BIT]     = 1'b0 ;
 
// retry expired error for posted writes control
//assign err_rty_exp_out = posted_write_req && ~wait_in && retry_in && retry_expired && ~rtransfer_in;
assign err_rty_exp_out = 1'b0 ;
 
// error source and error signal output control logic - only for posted writes
assign err_source_out = mabort_in /*|| err_rty_exp_out*/ ;
 
assign err_signal_out = /*err_rty_exp_out || */ posted_write_req && ~wait_in && (mabort_in || rerror_in) ;
 
//assign del_rty_exp_out = (~wait_in && (del_read_req || del_write_req)) && (retry_in && retry_expired && ~rtransfer_in) ;
assign del_rty_exp_out = 1'b0 ;
 
assign del_error_out   = ~wait_in && (del_write_req || del_read_req) && ( (mabort_in && ~conf_cyc_bc) || rerror_in ) ;
 
wire   del_write_complete = del_write_req && ( rtransfer_in || rerror_in || mabort_in ) ;
wire   del_read_complete  = del_read_req  && ( rerror_in || mabort_in || ( last_transfered ) || ( retry_in && ~first_in ) ) ;
 
assign del_complete_out = ~wait_in && ( del_write_complete || del_read_complete ) ;
 
// next last output generation
assign next_last_out = del_write_req || del_read_req && ( ~del_burst_in || read_bound ) || posted_write_req && ( write_next_last ) ;
/*==================================================================================================================
Error recovery FF gets a value of one, when during posted write error occurs. It is cleared when all the data provided
for erroneous transaction is pulled out of WBW_FIFO
==================================================================================================================*/
 
// error recovery flip flop input - used when posted write is terminated with an error
always@(
    err_recovery or
    last_out or
    wlast or
    err_signal_out or
    intermediate_last
)
begin
    // when error recovery is not set - drive its input so it gets set
    if ( ~err_recovery )
        err_recovery_in = ~last_out && ~intermediate_last && err_signal_out ;
    else
        // when error recovery is set, wbw_fifo is enabled - clear err_recovery when last data entry of erroneous transaction is pulled out of fifo
        err_recovery_in = ~wlast ;
end
 
wire data_out_load = (posted_write_req || del_write_req) && ( !rdy_out || ( !wait_in && rtransfer_in ) ) ;
 
wire be_out_load  = (req_out && !rdy_out) || ( posted_write_req && !wait_in && rtransfer_in ) ;
 
wire last_load  = req_out && ( ~rdy_out || ~wait_in && wtransfer_in ) ;
 
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        data_out <= #`FF_DELAY 32'h0000_0000 ;
    else
    if ( data_out_load )
        data_out <= #`FF_DELAY intermediate_data ;
end
 
always@(posedge clk_in or posedge reset_in)
begin
    if ( reset_in )
        be_out <= #`FF_DELAY 4'hF ;
    else
    if ( be_out_load )
        be_out <= #`FF_DELAY posted_write_req ? intermediate_be : source_be ;
end
 
always@(posedge reset_in or posedge clk_in)
begin
    if (reset_in)
        current_last <= #`FF_DELAY 1'b0 ;
    else
    if ( last_load )
        current_last <= #`FF_DELAY next_last_out ;
end
 
assign last_out = current_last ;
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_master32_sm_if.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	21	mihad	`// Revision 1.2 2001/10/05 08:14:29 mihad`
46			`// Updated all files with inclusion of timescale file for simulation purposes.`
47			`//`
48	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
49			`// New project directory structure`
50	2	mihad	`//`
51	6	mihad	`//`
52	2	mihad
53	21	mihad	`include "pci_constants.v"
54	2	mihad	`include "bus_commands.v"
55	21	mihad
56			`// synopsys translate_off`
57	6	mihad	`include "timescale.v"
58	21	mihad	`// synopsys translate_on`
59	2	mihad
60			`/*====================================================================`
61			`Module provides interface between PCI bridge internals and PCI master`
62			`state machine`
63			`====================================================================*/`
64			`module PCI_MASTER32_SM_IF`
65			`(`
66			`clk_in,`
67			`reset_in,`
68	21	mihad
69	2	mihad	`// interconnect to pci master state machine`
70			`address_out,`
71			`bc_out,`
72			`data_out,`
73			`data_in,`
74			`be_out,`
75			`req_out,`
76			`rdy_out,`
77			`last_out,`
78	21	mihad
79	2	mihad	`next_data_out,`
80			`next_be_out,`
81			`next_last_out,`
82
83			`// status inputs from master SM`
84			`wait_in,`
85			`wtransfer_in,`
86			`rtransfer_in,`
87			`retry_in,`
88			`rerror_in,`
89			`first_in ,`
90			`mabort_in,`
91
92
93			`// WISHBONE WRITE fifo inputs and outputs`
94			`wbw_renable_out,`
95			`wbw_fifo_addr_data_in,`
96			`wbw_fifo_cbe_in,`
97			`wbw_fifo_control_in,`
98			`wbw_fifo_empty_in,`
99			`wbw_fifo_transaction_ready_in,`
100	21	mihad
101	2	mihad	`// WISHBONE READ fifo inputs and outputs`
102			`wbr_fifo_wenable_out,`
103			`wbr_fifo_data_out,`
104			`wbr_fifo_be_out,`
105			`wbr_fifo_control_out,`
106
107			`// delayed transaction control logic inputs and outputs`
108			`del_wdata_in,`
109			`del_complete_out,`
110			`del_req_in,`
111			`del_addr_in,`
112			`del_bc_in,`
113			`del_be_in,`
114			`del_burst_in,`
115			`del_error_out,`
116			`del_rty_exp_out,`
117			`del_we_in,`
118
119			`// configuration space interconnect`
120			`// error reporting`
121			`err_addr_out,`
122			`err_bc_out,`
123			`err_signal_out,`
124			`err_source_out,`
125			`err_rty_exp_out,`
126
127			`cache_line_size_in,`
128	21	mihad
129			`// two signals for pci control and status`
130	2	mihad	`mabort_received_out,`
131	21	mihad	`tabort_received_out,`
132
133			`posted_write_not_present_out`
134	2	mihad	`);`
135
136			`// system inputs`
137			`input clk_in ;`
138			`input reset_in ;`
139
140			`// PCI master state machine interconnect`
141			`output [31:0] address_out ; // address output`
142
143			`output [3:0] bc_out ; // bus command output`
144	21	mihad	`reg [3:0] bc_out ;`
145	2	mihad
146			`output [31:0] data_out ; // data output for writes`
147			`reg [31:0] data_out ;`
148
149			`input [31:0] data_in ; // data input for reads`
150			`output [3:0] be_out ; // byte enable output`
151	21	mihad	`reg [3:0] be_out ;`
152	2	mihad
153			`output req_out ; // request output`
154
155			`output rdy_out ; // ready output`
156			`reg rdy_out ;`
157
158			`output last_out ; // last data indicator output`
159
160			`output [31:0] next_data_out ; // next data output`
161			`output [3:0] next_be_out ; // next byte enable output`
162			`output next_last_out ; // next transfer last indicator`
163
164			`input wait_in,`
165			`wtransfer_in,`
166			`rtransfer_in,`
167			`retry_in,`
168			`rerror_in,`
169			`first_in ,`
170			`mabort_in ;`
171
172			`// WISHBONE write fifo interconnect`
173			`output wbw_renable_out ; // WBW_FIFO read enable signal`
174
175			`input [31:0] wbw_fifo_addr_data_in ; // WBW_FIFO address/data bus`
176			`input [3:0] wbw_fifo_cbe_in ; // WBW_FIFO command/byte enable bus`
177			`input [3:0] wbw_fifo_control_in ; // WBW_FIFO control bus`
178			`input wbw_fifo_empty_in ; // WBW_FIFO's empty status indicator`
179			`input wbw_fifo_transaction_ready_in ; // WBW_FIFO transaction ready indicator`
180
181			`// WISHBONE read FIFO interconnect`
182			`output wbr_fifo_wenable_out ; // write enable for WBR_FIFO`
183
184			`output [31:0] wbr_fifo_data_out ; // data output to WBR_FIFO`
185
186			`output [3:0] wbr_fifo_be_out ; // byte enable output for WBR_FIFO`
187
188			`output [3:0] wbr_fifo_control_out ; // WBR_FIFO control output`
189
190			`// delayed transaction control logic inputs and outputs`
191			`input [31:0] del_wdata_in ; // delayed write data input`
192			`output del_complete_out ; // delayed transaction completed output`
193
194			`input del_req_in ; // delayed transaction request`
195			`input [31:0] del_addr_in ; // delayed transaction address`
196			`input [3:0] del_bc_in ; // delayed transaction bus command input`
197			`input [3:0] del_be_in ; // delayed transaction byte enables input`
198			`input del_burst_in ; // delayed transaction burst req. indicator`
199			`output del_error_out ; // delayed transation error termination signal`
200
201			`output del_rty_exp_out ; // retry expired output for delayed transactions`
202
203			`input del_we_in ; // delayed write request indicator`
204
205			`output [31:0] err_addr_out ; // erroneous address output`
206			`output [3:0] err_bc_out ; // erroneous bus command output`
207
208			`output err_signal_out ; // error signalization`
209
210			`output err_source_out ; // error source indicator`
211
212			`input [7:0] cache_line_size_in ; // cache line size value input`
213
214			`output err_rty_exp_out ; // retry expired error output`
215
216			`output mabort_received_out ; // master abort signaled to status register`
217			`output tabort_received_out ; // target abort signaled to status register`
218
219	21	mihad	`output posted_write_not_present_out ; // used in target state machine - must deny read completions when this signal is 0`
220	2	mihad
221	21	mihad
222	2	mihad	`assign err_bc_out = bc_out ;`
223
224			`// assign read outputs`
225			`/*==================================================================================================================`
226			`WISHBONE read FIFO data outputs - just link them to SM data outputs and delayed BE input`
227			`==================================================================================================================*/`
228			`assign wbr_fifo_data_out = data_in ;`
229			`assign wbr_fifo_be_out = del_be_in ;`
230
231			`// decode if current bus command is configuration command`
232			wire conf_cyc_bc = ( bc_out[3:1] == `BC_CONF_RW ) ;
233
234			`// register for indicating that current data is also last in transfer`
235			`reg current_last ;`
236
237			`// register indicating that last data was transfered OK`
238			`reg last_transfered ;`
239			`always@(posedge reset_in or posedge clk_in)`
240			`begin`
241			`if (reset_in)`
242			last_transfered <= #`FF_DELAY 1'b0 ;
243			`else`
244			last_transfered <= #`FF_DELAY ~wait_in && last_out && wtransfer_in ;
245			`end`
246
247			`// status signals output assignement`
248			`assign mabort_received_out = mabort_in ;`
249
250			`wire tabort_ff_in = ~wait_in && rerror_in ;`
251
252			`reg tabort_received_out ;`
253			`always@(posedge reset_in or posedge clk_in)`
254			`begin`
255			`if ( reset_in )`
256			tabort_received_out <= #`FF_DELAY 1'b0 ;
257			`else`
258			tabort_received_out <= #`FF_DELAY tabort_ff_in ;
259			`end`
260
261			`// error recovery indicator`
262			`reg err_recovery ;`
263
264			`// operation is locked until error recovery is in progress or error bit is not cleared in configuration space`
265	21	mihad	`wire err_lock = err_recovery ;`
266	2	mihad
267			`// three requests are possible - posted write, delayed write and delayed read`
268			`reg del_write_req ;`
269			`reg posted_write_req ;`
270			`reg del_read_req ;`
271
272			`// assign request output`
273			`assign req_out = del_write_req \|\| posted_write_req \|\| del_read_req ;`
274
275	21	mihad	`// posted write is not present, when WB Write Fifo is empty and posted write transaction is not beeing requested at present time`
276			`assign posted_write_not_present_out = !posted_write_req && wbw_fifo_empty_in ;`
277
278	2	mihad	`// write requests are staged, so data is read from source into current data register and next data register`
279			`reg write_req_int ;`
280			`always@(posedge reset_in or posedge clk_in)`
281			`begin`
282			`if ( reset_in )`
283			write_req_int <= #`FF_DELAY 1'b0 ;
284			`else`
285			write_req_int <= #`FF_DELAY posted_write_req \|\| del_write_req ;
286
287			`end`
288
289			`// ready output is generated one clock after request for reads and two after for writes`
290			`always@(posedge reset_in or posedge clk_in)`
291			`begin`
292			`if (reset_in)`
293			rdy_out <= #`FF_DELAY 1'b0 ;
294			`else`
295			rdy_out <= #`FF_DELAY del_read_req \|\| ( (posted_write_req \|\| del_write_req) && write_req_int) ;
296			`end`
297
298			`// wires with logic used as inputs to request FFs`
299			`wire do_posted_write = ( wbw_fifo_transaction_ready_in && ~wbw_fifo_empty_in && ~err_lock ) ;`
300			`wire do_del = ( del_req_in && ~err_lock && wbw_fifo_empty_in ) ;`
301			`wire do_del_write = do_del && del_we_in ;`
302			`wire do_del_read = do_del && ~del_we_in ;`
303
304			`// register for indicating current operation's data source`
305			`parameter DELAYED_WRITE = 1'b1 ;`
306			`parameter POSTED_WRITE = 1'b0 ;`
307
308			`// new data source - depending on which transaction will be processed next - delayed read is here because source of byte enables must`
309			`// be specified for delayed reads also - data source is not relevant for delayed reads, so value is don't care anyway`
310			`wire new_data_source = (do_del_write \|\| do_del_read) ? DELAYED_WRITE : POSTED_WRITE ; // input to data source register`
311			`wire data_source_change = ~req_out ; // change (enable) for data source register - when no requests are in progress`
312
313			`reg data_source ; // data source value`
314			`always@(posedge reset_in or posedge clk_in)`
315			`begin`
316			`if (reset_in)`
317			`// default value is posted write source - wbw_fifo`
318			data_source <= #`FF_DELAY POSTED_WRITE ;
319			`else`
320			`if (data_source_change)`
321			`// change data source on rising clock edge`
322			data_source <= #`FF_DELAY new_data_source ;
323			`end`
324
325			`// multiplexer for data output to PCI MASTER state machine`
326			`reg [31:0] source_data ;`
327			`reg [3:0] source_be ;`
328	21	mihad	`always@(data_source or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or del_wdata_in or del_be_in or del_burst_in)`
329	2	mihad	`begin`
330			`case (data_source)`
331			`POSTED_WRITE: begin`
332			`source_data = wbw_fifo_addr_data_in ;`
333			`source_be = wbw_fifo_cbe_in ;`
334			`end`
335			`DELAYED_WRITE: begin`
336			`source_data = del_wdata_in ;`
337	21	mihad	`// read all bytes during delayed burst read!`
338			`source_be = ~( del_be_in \| {4{del_burst_in}} ) ;`
339	2	mihad	`end`
340			`endcase`
341			`end`
342
343			wire waddr = wbw_fifo_control_in[`ADDR_CTRL_BIT] ;
344
345			`// address change indicator - address is allowed to be loaded only when no transaction is in progress!`
346			`wire address_change = ~req_out ; // address change - whenever there is no request in progress`
347
348			`// new address - input to register storing address of current request - if posted write request will be next,`
349			`// load address and bus command from wbw_fifo, else load data from delayed transaction logic`
350			`wire [31:0] new_address = ( ~req_out && do_posted_write ) ? wbw_fifo_addr_data_in[31:0] : del_addr_in[31:0] ;`
351			`wire [3:0] new_bc = ( ~req_out && do_posted_write ) ? wbw_fifo_cbe_in : del_bc_in ;`
352
353			`// address counter enable - only for posted writes when data is actually transfered`
354	21	mihad	`wire addr_count_en = ~wait_in && posted_write_req && rtransfer_in ;`
355	2	mihad
356			`always@(posedge reset_in or posedge clk_in)`
357			`begin`
358			`if (reset_in)`
359			bc_out <= #`FF_DELAY `BC_RESERVED0 ;
360			`else`
361			`if (address_change)`
362			bc_out <= #`FF_DELAY new_bc ;
363	21	mihad	`end`
364	2	mihad
365	21	mihad	`reg [29:0] current_dword_address ;`
366	2	mihad
367			`// DWORD address counter with load`
368			`always@(posedge reset_in or posedge clk_in)`
369			`begin`
370			`if (reset_in)`
371			current_dword_address <= #`FF_DELAY 30'h0000_0000 ;
372			`else`
373			`if (address_change)`
374			current_dword_address <= #`FF_DELAY new_address[31:2] ;
375			`else`
376			`if (addr_count_en)`
377			current_dword_address <= #`FF_DELAY current_dword_address + 1'b1 ;
378	21	mihad	`end`
379	2	mihad
380			`reg [1:0] current_byte_address ;`
381			`always@(posedge reset_in or posedge clk_in)`
382			`begin`
383			`if (reset_in)`
384			current_byte_address <= #`FF_DELAY 2'b00 ;
385			`else`
386			`if (address_change)`
387			current_byte_address <= #`FF_DELAY new_address[1:0] ;
388	21	mihad	`end`
389	2	mihad
390			`// address output to PCI master state machine assignement`
391			`assign address_out = { current_dword_address, current_byte_address } ;`
392
393			`// the same for erroneous address assignement`
394			`assign err_addr_out = { current_dword_address, current_byte_address } ;`
395
396			`// cacheline size counter - for read transaction length control`
397			`// cache line count is enabled during burst reads when data is actually transfered`
398			`wire read_count_enable = ~wait_in && del_read_req && del_burst_in && wtransfer_in ;`
399
400			`// cache line counter is loaded when del read request is not in progress`
401	21	mihad	`wire read_count_load = ~del_read_req ;`
402	2	mihad
403	21	mihad	reg [(`WBR_ADDR_LENGTH - 1):0] max_read_count ;
404	2	mihad	`always@(cache_line_size_in or del_bc_in)`
405			`begin`
406			if ( (cache_line_size_in >= `WBR_DEPTH) \|\| (~del_bc_in[1] && ~del_bc_in[0]) )
407			max_read_count = `WBR_DEPTH - 1'b1;
408			`else`
409			`max_read_count = cache_line_size_in ;`
410			`end`
411
412	21	mihad	reg [(`WBR_ADDR_LENGTH - 1):0] read_count ;
413	2	mihad
414			`// cache line bound indicator - it signals when data for one complete cacheline was read`
415	21	mihad	wire read_bound_comb = ~\|(read_count[(`WBR_ADDR_LENGTH - 1):2]) ;
416	2	mihad	`reg read_bound ;`
417	21	mihad	`always@(posedge clk_in or posedge reset_in)`
418	2	mihad	`begin`
419	21	mihad	`if ( reset_in )`
420	2	mihad	read_bound <= #`FF_DELAY 1'b0 ;
421	21	mihad	`else if (read_count_load)`
422			read_bound <= #`FF_DELAY 1'b0 ;
423	2	mihad	`else if ( read_count_enable )`
424			read_bound <= #`FF_DELAY read_bound_comb ;
425			`end`
426
427			`// down counter with load`
428			`always@(posedge reset_in or posedge clk_in)`
429			`begin`
430			`if (reset_in)`
431	21	mihad	read_count <= #`FF_DELAY 0 ;
432	2	mihad	`else`
433			`if (read_count_load)`
434			read_count <= #`FF_DELAY max_read_count ;
435			`else`
436			`if (read_count_enable)`
437			read_count <= #`FF_DELAY read_count - 1'b1 ;
438	21	mihad
439	2	mihad	`end`
440
441			`// flip flop indicating error recovery is in progress`
442			`reg err_recovery_in ;`
443			`always@(posedge reset_in or posedge clk_in)`
444			`begin`
445			`if (reset_in)`
446			err_recovery <= #`FF_DELAY 1'b0 ;
447			`else`
448			err_recovery <= #`FF_DELAY err_recovery_in ;
449			`end`
450
451			`/*// retry counter implementation`
452			`reg [7:0] retry_count ;`
453
454			`wire retry_expired = ~\|(retry_count[7:1]) ;`
455
456			`// loading of retry counter - whenever no request is present or other termination than retry or wait is signalled`
457			`wire retry_load = ~req_out \|\| (~wait_in && rtransfer_in) ;`
458
459			`// retry DOWN counter with load`
460			`always@(posedge reset_in or posedge clk_in)`
461			`begin`
462			`if (reset_in)`
463			retry_count <= #`FF_DELAY 8'hFF ;
464			`else`
465			`if ( retry_load )`
466			retry_count <= #`FF_DELAY `PCI_RTY_CNT_MAX ;
467			`else`
468			`if (retry_in)`
469			retry_count <= #`FF_DELAY retry_count - 1'b1 ;
470			`end*/`
471
472			`/*==================================================================================================================`
473			`Delayed write requests are always single transfers!`
474			`Delayed write request starts, when no request is currently beeing processed and it is signaled from other side`
475			`of the bridge.`
476			`==================================================================================================================*/`
477			`// delayed write request FF input control`
478			`reg del_write_req_input ;`
479
480			`always@(`
481	21	mihad	`do_del_write or`
482			`del_write_req or`
483			`posted_write_req or`
484			`del_read_req or`
485			`wait_in or`
486			`//retry_in or`
487	2	mihad	`//retry_expired or`
488			`rtransfer_in or`
489			`rerror_in or`
490			`mabort_in`
491			`)`
492			`begin`
493			`if (~del_write_req)`
494	21	mihad	`begin`
495	2	mihad	`// delayed write is not in progress and is requested`
496			`// delayed write can be requested when no other request is in progress`
497			`del_write_req_input = ~posted_write_req && ~del_read_req && do_del_write ;`
498			`end`
499			`else`
500			`begin`

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [pci_master32_sm_if.v] - Blame information for rev 21