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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: pci_target32_sm.v                                ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Tadej Markovic, tadej@opencores.org                   ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2002/09/24 19:09:17  mihad
// Number of state bits define was removed
//
// Revision 1.6  2002/09/24 18:30:00  mihad
// Changed state machine encoding to true one-hot
//
// Revision 1.5  2002/08/22 09:07:06  mihad
// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.
//
// Revision 1.4  2002/02/19 16:32:37  mihad
// Modified testbench and fixed some bugs
//
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
//
//
 
`include "pci_constants.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module PCI_TARGET32_SM
(
    // system inputs
    clk_in,
    reset_in,
    // master inputs
    pci_frame_in,
    pci_irdy_in,
    pci_idsel_in,
    pci_frame_reg_in,
    pci_irdy_reg_in,
    pci_idsel_reg_in,
    // target response outputs
    pci_trdy_out,
    pci_stop_out,
    pci_devsel_out,
    pci_trdy_en_out,
    pci_stop_en_out,
    pci_devsel_en_out,
    ad_load_out,
    ad_load_on_transfer_out,
    // address, data, bus command, byte enable in/outs
    pci_ad_reg_in,
    pci_ad_out,
    pci_ad_en_out,
    pci_cbe_reg_in,
    bckp_trdy_en_in,
    bckp_devsel_in,
    bckp_trdy_in,
    bckp_stop_in,
    pci_trdy_reg_in,
    pci_stop_reg_in,
 
    // backend side of state machine with control signals to pci_io_mux ...
    address_out,
    addr_claim_in,
    bc_out,
    bc0_out,
    data_out,
    data_in,
    be_out,
    req_out,
    rdy_out,
    addr_phase_out,
    bckp_devsel_out,
    bckp_trdy_out,
    bckp_stop_out,
    last_reg_out,
    frame_reg_out,
    fetch_pcir_fifo_out,
    load_medium_reg_out,
    sel_fifo_mreg_out,
    sel_conf_fifo_out,
    fetch_conf_out,
    load_to_pciw_fifo_out,
    load_to_conf_out,
    same_read_in,
    norm_access_to_config_in,
    read_completed_in,
    read_processing_in,
    target_abort_in,
    disconect_wo_data_in,
    disconect_w_data_in,
    target_abort_set_out,
    pciw_fifo_full_in,
    pcir_fifo_data_err_in,
    wbw_fifo_empty_in,
    wbu_del_read_comp_pending_in,
    wbu_frame_en_in
 
) ;
 
/*----------------------------------------------------------------------------------------------------------------------
Various parameters needed for state machine and other stuff
----------------------------------------------------------------------------------------------------------------------*/
parameter       S_IDLE          = 3'b001 ;
parameter       S_WAIT          = 3'b010 ;
parameter       S_TRANSFERE     = 3'b100 ;
 
 
/*==================================================================================================================
System inputs.
==================================================================================================================*/
// PCI side clock and reset
input   clk_in,
        reset_in ;
 
 
/*==================================================================================================================
PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
module. Enables are separate signals.
==================================================================================================================*/
// master inputs
input   pci_frame_in,
        pci_irdy_in,
        pci_idsel_in ;
input   pci_frame_reg_in,
        pci_irdy_reg_in,
        pci_idsel_reg_in ;
 
// target response outputs
output  pci_trdy_out,
        pci_stop_out,
        pci_devsel_out ;
output  pci_trdy_en_out,
        pci_stop_en_out,
        pci_devsel_en_out ;
output  ad_load_out ;
output  ad_load_on_transfer_out ;
// address, data, bus command, byte enable in/outs
input   [31:0]  pci_ad_reg_in ;
output  [31:0]  pci_ad_out ;
output          pci_ad_en_out ;
input   [3:0]   pci_cbe_reg_in ;
input           bckp_trdy_en_in ;
input           bckp_devsel_in ;
input           bckp_trdy_in ;
input           bckp_stop_in ;
input           pci_trdy_reg_in ;
input           pci_stop_reg_in ;
 
 
/*==================================================================================================================
Other side of PCI Target state machine
==================================================================================================================*/
// Data, byte enables, bus commands and address ports
output  [31:0]  address_out ;       // current request address output - registered
input           addr_claim_in ;     // current request address claim input
output  [3:0]   bc_out ;            // current request bus command output - registered
output          bc0_out ;           // current cycle RW signal output
input   [31:0]  data_in ;           // for read operations - current dataphase data input
output  [31:0]  data_out ;          // for write operations - current request data output - registered
output   [3:0]  be_out ;            // current dataphase byte enable outputs - registered
// Port connection control signals from PCI FSM
output          req_out ;           // Read is requested to WB master
output          rdy_out ;           // DATA / ADDRESS selection when read or write - registered
output          addr_phase_out ;    // Indicates address phase and also fast-back-to-back address phase - registered
output                  bckp_devsel_out ;       // DEVSEL output (which is registered) equivalent
output          bckp_trdy_out ;     // TRDY output (which is registered) equivalent
output                  bckp_stop_out ;         // STOP output (which is registered) equivalent
output          last_reg_out ;      // Indicates last data phase - registered
output          frame_reg_out ;     // FRAME output signal - registered
output          fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side
output          load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
output          sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register
output          sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"
output          fetch_conf_out ;    // Read enable for configuration space registers
output          load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO
output          load_to_conf_out ;  // Write enable to Configuration space registers
 
 
/*==================================================================================================================
Status
==================================================================================================================*/
input           same_read_in ;              // Indicates the same read request (important when read is finished on WB side)
input           norm_access_to_config_in ;  // Indicates the access to Configuration space with MEMORY commands
input           read_completed_in ;         // Indicates that read request is completed on WB side
input           read_processing_in ;        // Indicates that read request is processing on WB side
input           target_abort_in ;           // Indicates target abort termination
input           disconect_wo_data_in ;      // Indicates disconnect without data termination
input                   disconect_w_data_in ;           // Indicates disconnect with data termination
input           pciw_fifo_full_in ;         // Indicates that write PCIW_FIFO is full
input           pcir_fifo_data_err_in ;     // Indicates data error on current data read from PCIR_FIFO
input           wbw_fifo_empty_in ;         // Indicates that WB SLAVE UNIT has no data to be written to PCI bus
input                   wbu_del_read_comp_pending_in ; // Indicates that WB S�AVE UNIT has a delayed read pending
input           wbu_frame_en_in ;           // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if
                                            //   address on PCI bus is also claimed by decoder in this PCI TARGET UNIT
output          target_abort_set_out ;      // Signal used to be set in configuration space registers
 
/*==================================================================================================================
END of input / output PORT DEFINITONS !!!
==================================================================================================================*/
 
// Delayed frame signal for determining the address phase
reg             previous_frame ;
// Delayed read completed signal for preparing the data from pcir fifo
reg             read_completed_reg ;
// Delayed disconnect with/without data for stop loading data to PCIW_FIFO
//reg             disconect_wo_data_reg ;
 
wire config_disconnect ;
wire disconect_wo_data = disconect_wo_data_in || config_disconnect ;
wire disconect_w_data = disconect_w_data_in ;
// Delayed frame signal for determining the address phase!
always@(posedge clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        previous_frame <= #`FF_DELAY 1'b1 ;
        read_completed_reg <= #`FF_DELAY 1'b0 ;
    end
    else
    begin
        previous_frame <= #`FF_DELAY pci_frame_reg_in ;
        read_completed_reg <= #`FF_DELAY read_completed_in ;
    end
end
 
// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)
wire    addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;
 
`ifdef      HOST
    `ifdef  NO_CNF_IMAGE
            // Wire tells when there is configuration (read or write) command with IDSEL signal active
            wire    config_access = 1'b0 ;
            // Write and read progresses are used for determining next state
            wire    write_progress  =   ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
                                          (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
            wire    read_progress   =   ( (read_completed_in && wbw_fifo_empty_in) ) ;
    `else
            // Wire tells when there is configuration (read or write) command with IDSEL signal active
            wire    config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) &&     // idsel asserted with correct bus command(101x)
                                    (pci_ad_reg_in[1:0] == 2'b00) ;        // has to be type 0 configuration cycle
 
            // Write and read progresses are used for determining next state
            wire    write_progress  =   ( (norm_access_to_config_in) ||
                                                                  (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
                                          (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
            wire    read_progress   =   ( (~read_completed_in && norm_access_to_config_in) ||
                                          (read_completed_in && wbw_fifo_empty_in) ) ;
    `endif
`else
            // Wire tells when there is configuration (read or write) command with IDSEL signal active
            wire    config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) &&     // idsel asserted with correct bus command(101x)
                                    (pci_ad_reg_in[1:0] == 2'b00) ;        // has to be type 0 configuration cycle
 
            // Write and read progresses are used for determining next state
            wire    write_progress  =   ( (norm_access_to_config_in) ||
                                                                  (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
                                          (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;
            wire    read_progress   =   ( (~read_completed_in && norm_access_to_config_in) ||
                                          (read_completed_in && wbw_fifo_empty_in) ) ;
`endif
 
// Signal for loading data to medium register from pcir fifo when read completed from WB side!
wire    prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;
 
// Write allowed to PCIW_FIFO
wire    write_to_fifo   =   ((read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ||
                                                         (~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in)) ;
// Read allowed from PCIR_FIFO
wire    read_from_fifo  =   (read_completed_in && wbw_fifo_empty_in) ;
`ifdef      HOST
    `ifdef  NO_CNF_IMAGE
            // Read request is allowed to be proceed regarding the WB side
            wire    read_request    =   (~read_completed_in && ~read_processing_in) ;
    `else
            // Read request is allowed to be proceed regarding the WB side
            wire    read_request    =   (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
    `endif
`else
            // Read request is allowed to be proceed regarding the WB side
            wire    read_request    =   (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;
`endif
 
// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period
reg             rw_cbe0 ;
reg             wr_progress ;
reg             rd_progress ;
reg             rd_from_fifo ;
reg             rd_request ;
reg             wr_to_fifo ;
reg             same_read_reg ;
 
always@(posedge clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        rw_cbe0                         <= #`FF_DELAY 1'b0 ;
        wr_progress                     <= #`FF_DELAY 1'b0 ;
        rd_progress                     <= #`FF_DELAY 1'b0 ;
        rd_from_fifo                    <= #`FF_DELAY 1'b0 ;
        rd_request                      <= #`FF_DELAY 1'b0 ;
        wr_to_fifo                      <= #`FF_DELAY 1'b0 ;
        same_read_reg                   <= #`FF_DELAY 1'b0 ;
    end
    else
    begin
        if (addr_phase)
        begin
            rw_cbe0                     <= #`FF_DELAY pci_cbe_reg_in[0] ;
            wr_progress                 <= #`FF_DELAY write_progress ;
            rd_progress                 <= #`FF_DELAY read_progress ;
            rd_from_fifo                <= #`FF_DELAY read_from_fifo ;
            rd_request                  <= #`FF_DELAY read_request ;
            wr_to_fifo                  <= #`FF_DELAY write_to_fifo ;
            same_read_reg               <= #`FF_DELAY same_read_in ;
        end
    end
end
 
`ifdef      HOST
    `ifdef  NO_CNF_IMAGE
            wire    norm_access_to_conf_reg     = 1'b0 ;
            wire    cnf_progress                = 1'b0 ;
    `else
            reg     norm_access_to_conf_reg ;
            reg     cnf_progress ;
            always@(posedge clk_in or posedge reset_in)
            begin
                if (reset_in)
                begin
                    norm_access_to_conf_reg     <= #`FF_DELAY 1'b0 ;
                    cnf_progress                <= #`FF_DELAY 1'b0 ;
                end
                else
                begin
                    if (addr_phase)
                    begin
                        norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
                        cnf_progress            <= #`FF_DELAY config_access ;
                    end
                end
            end
    `endif
`else
            reg     norm_access_to_conf_reg ;
            reg     cnf_progress ;
            always@(posedge clk_in or posedge reset_in)
            begin
                if (reset_in)
                begin
                    norm_access_to_conf_reg     <= #`FF_DELAY 1'b0 ;
                    cnf_progress                <= #`FF_DELAY 1'b0 ;
                end
                else
                begin
                    if (addr_phase)
                    begin
                        norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
                        cnf_progress            <= #`FF_DELAY config_access ;
                    end
                end
            end
`endif
 
// Signal used in S_WAIT state to determin next state
wire s_wait_progress =  (
                        (~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
                        (~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && ~pcir_fifo_data_err_in) ||
                        (~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
                        (cnf_progress && ~target_abort_in)
                        ) ;
 
// Signal used in S_TRANSFERE state to determin next state
wire s_tran_progress =  (
                        (rw_cbe0 && !disconect_wo_data) ||
                        (~rw_cbe0 && !disconect_wo_data && !target_abort_in && !pcir_fifo_data_err_in)
                        ) ;
 
// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY
wire            pcit_sm_clk_en ;
// FSM states signals indicating the current state
reg             state_idle ;
reg             state_wait ;
reg             sm_transfere ;
reg             backoff ;
reg             state_default ;
wire            state_backoff   = sm_transfere && backoff ;
wire            state_transfere = sm_transfere && !backoff ;
 
always@(posedge clk_in or posedge reset_in)
begin
    if ( reset_in )
        backoff <= #`FF_DELAY 1'b0 ;
    else if ( state_idle )
        backoff <= #`FF_DELAY 1'b0 ;
    else
        backoff <= #`FF_DELAY (state_wait && !s_wait_progress) ||
                              (sm_transfere && !s_tran_progress && !pci_frame_in && !pci_irdy_in) ||
                              backoff ;
end
assign config_disconnect = sm_transfere && (norm_access_to_conf_reg || cnf_progress) ;
 
// Clock enable module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_CLK_EN         pci_target_clock_en
(
    .addr_phase             (addr_phase),
    .config_access          (config_access),
    .addr_claim_in          (addr_claim_in),
    .pci_frame_in           (pci_frame_in),
    .state_wait             (state_wait),
    .state_transfere        (sm_transfere),
    .state_default          (state_default),
    .clk_enable             (pcit_sm_clk_en)
);
 
reg [2:0]  c_state ; //current state register
reg [2:0]  n_state ; //next state input to current state register
 
// state machine register control
always@(posedge clk_in or posedge reset_in)
begin
    if (reset_in) // reset state machine to S_IDLE state
        c_state <= #`FF_DELAY S_IDLE ;
    else
        if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!
            c_state <= #`FF_DELAY n_state ;
end
 
// state machine logic
always@(c_state)
begin
    case (c_state)
    S_IDLE :
    begin
        state_idle      <= 1'b1 ;
        state_wait      <= 1'b0 ;
        sm_transfere <= 1'b0 ;
        state_default   <= 1'b0 ;
        n_state <= S_WAIT ;
    end
    S_WAIT :
    begin
        state_idle      <= 1'b0 ;
        state_wait      <= 1'b1 ;
        sm_transfere <= 1'b0 ;
        state_default   <= 1'b0 ;
        n_state <= S_TRANSFERE ;
    end
    S_TRANSFERE :
    begin
        state_idle      <= 1'b0 ;
        state_wait      <= 1'b0 ;
        sm_transfere <= 1'b1 ;
        state_default   <= 1'b0 ;
        n_state <= S_IDLE ;
    end
    default :
    begin
        state_idle      <= 1'b0 ;
        state_wait      <= 1'b0 ;
        sm_transfere <= 1'b0 ;
        state_default   <= 1'b1 ;
        n_state <= S_IDLE ;
    end
    endcase
end
 
        // if not retry and not target abort
        // NO CRITICAL SIGNALS
wire    trdy_w          =   (
        (state_wait && ~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) ||
        (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && !pcir_fifo_data_err_in) ||
        (state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) ||
        (state_wait && cnf_progress && ~target_abort_in)
                            ) ;
        // if not disconnect without data and not target abort (only during reads)
        // MUST BE ANDED WITH CRITICAL ~FRAME
wire    trdy_w_frm      =   (
        (state_transfere && !cnf_progress && !norm_access_to_conf_reg && rw_cbe0 && !disconect_wo_data) ||
        (state_transfere && !cnf_progress && !norm_access_to_conf_reg && ~rw_cbe0 && !disconect_wo_data && ~pcir_fifo_data_err_in) ||
        (state_transfere && !cnf_progress && !norm_access_to_conf_reg && disconect_w_data && pci_irdy_reg_in && (!rw_cbe0 && !pcir_fifo_data_err_in))
                            ) ;
        // if not disconnect without data and not target abort (only during reads)
        // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
wire    trdy_w_frm_irdy =   ( ~bckp_trdy_in ) ;
// TRDY critical module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_TRDY_CRIT      pci_target_trdy_critical
(
    .trdy_w                 (trdy_w),
    .trdy_w_frm             (trdy_w_frm),
    .trdy_w_frm_irdy        (trdy_w_frm_irdy),
    .pci_frame_in           (pci_frame_in),
    .pci_irdy_in            (pci_irdy_in),
    .pci_trdy_out           (pci_trdy_out)
);
 
        // if target abort or retry
        // NO CRITICAL SIGNALS
wire    stop_w          =   (
        (state_wait && target_abort_in) ||
        (state_wait && ~cnf_progress && rw_cbe0 && ~wr_progress) ||
        (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && ~rd_progress) ||
        (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) ||
        (state_wait && ~cnf_progress && ~rw_cbe0 && ~same_read_reg && ~norm_access_to_conf_reg)
                            ) ;
        // if asserted, wait for deactivating the frame
        // MUST BE ANDED WITH CRITICAL ~FRAME
wire    stop_w_frm      =   (
        (state_backoff && ~bckp_stop_in)
                            ) ;
        // if target abort or if disconnect without data (after data transfere)
        // MUST BE ANDED WITH CRITICAL ~FRAME AND ~IRDY
wire    stop_w_frm_irdy =   (
        (state_transfere && (disconect_wo_data)) ||
        (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
                            ) ;
// STOP critical module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_STOP_CRIT      pci_target_stop_critical
(
    .stop_w                 (stop_w),
    .stop_w_frm             (stop_w_frm),
    .stop_w_frm_irdy        (stop_w_frm_irdy),
    .pci_frame_in           (pci_frame_in),
    .pci_irdy_in            (pci_irdy_in),
    .pci_stop_out           (pci_stop_out)
);
 
        // if OK to respond and not target abort
        // NO CRITICAL SIGNALS
wire    devs_w          =   (
        (addr_phase && config_access) ||
        (addr_phase && ~config_access && addr_claim_in) ||
        (state_wait && ~target_abort_in && !(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && pcir_fifo_data_err_in) )
                            ) ;
 
        // if not target abort (only during reads) or if asserted, wait for deactivating the frame
        // MUST BE ANDED WITH CRITICAL ~FRAME
wire    devs_w_frm      =   (
        (state_transfere && rw_cbe0) ||
        (state_transfere && ~rw_cbe0 && ~pcir_fifo_data_err_in) ||
        (state_backoff && ~bckp_devsel_in)
                            ) ;
        // if not target abort (only during reads)
        // MUST BE ANDED WITH CRITICAL ~FRAME AND IRDY
wire    devs_w_frm_irdy =   (
        (state_transfere && ~rw_cbe0 && pcir_fifo_data_err_in)
                            ) ;
// DEVSEL critical module used for preserving the architecture because of minimum delay for critical inputs
PCI_TARGET32_DEVS_CRIT      pci_target_devsel_critical
(
    .devs_w                 (devs_w),
    .devs_w_frm             (devs_w_frm),
    .devs_w_frm_irdy        (devs_w_frm_irdy),
    .pci_frame_in           (pci_frame_in),
    .pci_irdy_in            (pci_irdy_in),
    .pci_devsel_out         (pci_devsel_out)
);
 
// signal used in AD enable module with preserving the hierarchy because of minimum delay for critical inputs
assign  pci_ad_en_out =    (
        (addr_phase && config_access && ~pci_cbe_reg_in[0]) ||
        (addr_phase && ~config_access && addr_claim_in && ~pci_cbe_reg_in[0]) ||
        (state_wait && ~rw_cbe0) ||
        (state_transfere && ~rw_cbe0) ||
        (state_backoff && ~rw_cbe0 && ~pci_frame_reg_in)
                            ) ;
 
wire fast_back_to_back  =   (addr_phase && ~pci_irdy_reg_in) ;
 
        // if cycle will progress or will not be stopped
        // NO CRITICAL SIGNALS
wire    ctrl_en       =
        /*(~wbu_frame_en_in && fast_back_to_back) ||*/
        (addr_phase && config_access) ||
        (addr_phase && ~config_access && addr_claim_in) ||
        (state_wait) ||
        (state_transfere && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ||
        (state_backoff && ~(pci_frame_reg_in && ~pci_irdy_reg_in && (~pci_stop_reg_in || ~pci_trdy_reg_in))) ;
 
assign pci_trdy_en_out   = ctrl_en ;
assign pci_stop_en_out   = ctrl_en ;
assign pci_devsel_en_out = ctrl_en ;
 
// target ready output signal delayed for one clock used in conjunction with irdy_reg to select which
//   data are registered in io mux module - from fifo or medoum register
reg             bckp_trdy_reg ;
// delayed indicators for states transfere and backoff
reg             state_transfere_reg ;
reg             state_backoff_reg ;
always@(posedge clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        bckp_trdy_reg <= #`FF_DELAY 1'b1 ;
        state_transfere_reg <= #`FF_DELAY 1'b0 ;
        state_backoff_reg <= #`FF_DELAY 1'b0 ;
    end
    else
    begin
        bckp_trdy_reg <= #`FF_DELAY bckp_trdy_in ;
        state_transfere_reg <= #`FF_DELAY state_transfere ;
        state_backoff_reg <= #`FF_DELAY state_backoff ;
    end
end
 
// Read control signals assignments
assign
    fetch_pcir_fifo_out =   (
        (prepare_rd_fifo_data) ||
        (state_wait && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~target_abort_in) ||
        (bckp_trdy_en_in && ~pci_trdy_reg_in && ~cnf_progress && ~rw_cbe0 && same_read_reg && rd_from_fifo && ~pci_irdy_reg_in)
                            ) ;
 
assign  ad_load_out         =   (state_wait) ;
 
assign  ad_load_on_transfer_out = (bckp_trdy_en_in && ~rw_cbe0) ;
 
assign  load_medium_reg_out =   (
        (prepare_rd_fifo_data) ||
        (state_wait && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~target_abort_in) ||
        (~pci_irdy_reg_in && ~rw_cbe0 && ~cnf_progress && same_read_reg && rd_from_fifo && ~pci_trdy_reg_in && bckp_trdy_en_in)
                                ) ;
 
assign  sel_fifo_mreg_out = (~pci_irdy_reg_in && ~bckp_trdy_reg) ;
 
`ifdef      HOST
    `ifdef  NO_CNF_IMAGE
            assign  sel_conf_fifo_out = 1'b0 ;
    `else
            assign  sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
    `endif
`else
            assign  sel_conf_fifo_out = (cnf_progress || norm_access_to_conf_reg) ;
`endif
 
// NOT USED NOW, SINCE READ IS ASYNCHRONOUS
//assign    fetch_conf_out = ((cnf_progress || norm_access_to_conf_reg) && ~rw_cbe0 && ~bckp_devsel_in) ;
assign  fetch_conf_out = 1'b0 ;
 
// Write control signals assignments
assign
    load_to_pciw_fifo_out = (
        (state_wait && (~cnf_progress && ~norm_access_to_conf_reg) && rw_cbe0 && wr_to_fifo && ~target_abort_in) ||
        (state_transfere_reg && ~state_backoff && rw_cbe0 && wr_to_fifo /*&& ~disconect_wo_data_reg*/ && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg)) ||
        ((state_backoff || state_backoff_reg) && rw_cbe0 && wr_to_fifo && ~pci_irdy_reg_in && ~bckp_trdy_reg && (~cnf_progress && ~norm_access_to_conf_reg))
                            ) ;
 
`ifdef      HOST
    `ifdef  NO_CNF_IMAGE
            assign  load_to_conf_out =  1'b0 ;
    `else
            assign  load_to_conf_out =  (
            (state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
            (state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
                                        ) ;
    `endif
`else
            assign  load_to_conf_out =  (
            (state_transfere_reg && cnf_progress && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg) ||
            (state_transfere_reg && norm_access_to_conf_reg && rw_cbe0 && ~pci_irdy_reg_in && ~bckp_trdy_reg)
                                        ) ;
`endif
 
// General control sigal assignments
assign  addr_phase_out = addr_phase ;
assign  last_reg_out = (pci_frame_reg_in && ~pci_irdy_reg_in) ;
assign  frame_reg_out = pci_frame_reg_in ;
assign  bckp_devsel_out = bckp_devsel_in ;
assign  bckp_trdy_out   = bckp_trdy_in ;
assign  bckp_stop_out   = bckp_stop_in ;
assign  target_abort_set_out = (bckp_devsel_in && bckp_trdy_in && ~bckp_stop_in && bckp_trdy_en_in) ;
// request signal for delayed sinc. module
reg master_will_request_read ;
always@(posedge clk_in or posedge reset_in)
begin
    if ( reset_in )
        master_will_request_read <= #`FF_DELAY 1'b0 ;
    else
        master_will_request_read <= #`FF_DELAY ((state_wait && ~target_abort_in) || (state_backoff && ~target_abort_set_out)) && ~cnf_progress && ~norm_access_to_conf_reg && ~rw_cbe0 && rd_request ;
end
// MORE OPTIMIZED READS, but not easy to control in a testbench!
//assign  req_out = master_will_request_read ; 
assign req_out = master_will_request_read && !pci_irdy_reg_in && !read_processing_in ;
 
// ready tells when address or data are written into fifo - RDY ? DATA : ADDRESS
assign  rdy_out = ~bckp_trdy_reg ;
 
// data and address outputs assignments!
assign  pci_ad_out = data_in ;
 
assign  data_out = pci_ad_reg_in ;
assign  be_out = pci_cbe_reg_in ;
assign  address_out = pci_ad_reg_in ;
assign  bc_out = pci_cbe_reg_in ;
assign  bc0_out = rw_cbe0 ;
 
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name: pci_target32_sm.v ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Tadej Markovic, tadej@opencores.org ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	73	mihad	`// Revision 1.7 2002/09/24 19:09:17 mihad`
46			`// Number of state bits define was removed`
47			`//`
48	56	mihad	`// Revision 1.6 2002/09/24 18:30:00 mihad`
49			`// Changed state machine encoding to true one-hot`
50			`//`
51	55	mihad	`// Revision 1.5 2002/08/22 09:07:06 mihad`
52			`// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.`
53			`//`
54	51	mihad	`// Revision 1.4 2002/02/19 16:32:37 mihad`
55			`// Modified testbench and fixed some bugs`
56			`//`
57	26	mihad	`// Revision 1.3 2002/02/01 15:25:12 mihad`
58			`// Repaired a few bugs, updated specification, added test bench files and design document`
59			`//`
60	21	mihad	`// Revision 1.2 2001/10/05 08:14:30 mihad`
61			`// Updated all files with inclusion of timescale file for simulation purposes.`
62			`//`
63	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:47 mihad`
64			`// New project directory structure`
65	2	mihad	`//`
66	6	mihad	`//`
67	2	mihad
68	21	mihad	`include "pci_constants.v"
69	2	mihad
70	21	mihad	`// synopsys translate_off`
71	6	mihad	`include "timescale.v"
72	21	mihad	`// synopsys translate_on`
73	2	mihad
74			`module PCI_TARGET32_SM`
75			`(`
76			`// system inputs`
77			`clk_in,`
78			`reset_in,`
79			`// master inputs`
80			`pci_frame_in,`
81			`pci_irdy_in,`
82			`pci_idsel_in,`
83			`pci_frame_reg_in,`
84			`pci_irdy_reg_in,`
85			`pci_idsel_reg_in,`
86			`// target response outputs`
87			`pci_trdy_out,`
88			`pci_stop_out,`
89			`pci_devsel_out,`
90			`pci_trdy_en_out,`
91			`pci_stop_en_out,`
92			`pci_devsel_en_out,`
93	21	mihad	`ad_load_out,`
94			`ad_load_on_transfer_out,`
95	2	mihad	`// address, data, bus command, byte enable in/outs`
96			`pci_ad_reg_in,`
97			`pci_ad_out,`
98			`pci_ad_en_out,`
99			`pci_cbe_reg_in,`
100			`bckp_trdy_en_in,`
101			`bckp_devsel_in,`
102			`bckp_trdy_in,`
103			`bckp_stop_in,`
104	21	mihad	`pci_trdy_reg_in,`
105			`pci_stop_reg_in,`
106	2	mihad
107			`// backend side of state machine with control signals to pci_io_mux ...`
108			`address_out,`
109			`addr_claim_in,`
110			`bc_out,`
111			`bc0_out,`
112			`data_out,`
113			`data_in,`
114			`be_out,`
115			`req_out,`
116			`rdy_out,`
117			`addr_phase_out,`
118	21	mihad	`bckp_devsel_out,`
119	2	mihad	`bckp_trdy_out,`
120	21	mihad	`bckp_stop_out,`
121	2	mihad	`last_reg_out,`
122			`frame_reg_out,`
123	21	mihad	`fetch_pcir_fifo_out,`
124			`load_medium_reg_out,`
125			`sel_fifo_mreg_out,`
126			`sel_conf_fifo_out,`
127			`fetch_conf_out,`
128			`load_to_pciw_fifo_out,`
129	2	mihad	`load_to_conf_out,`
130	21	mihad	`same_read_in,`
131			`norm_access_to_config_in,`
132			`read_completed_in,`
133			`read_processing_in,`
134			`target_abort_in,`
135			`disconect_wo_data_in,`
136			`disconect_w_data_in,`
137			`target_abort_set_out,`
138			`pciw_fifo_full_in,`
139			`pcir_fifo_data_err_in,`
140			`wbw_fifo_empty_in,`
141			`wbu_del_read_comp_pending_in,`
142			`wbu_frame_en_in`
143	2	mihad
144			`) ;`
145
146			`/*----------------------------------------------------------------------------------------------------------------------`
147			`Various parameters needed for state machine and other stuff`
148			`----------------------------------------------------------------------------------------------------------------------*/`
149	55	mihad	`parameter S_IDLE = 3'b001 ;`
150			`parameter S_WAIT = 3'b010 ;`
151			`parameter S_TRANSFERE = 3'b100 ;`
152	2	mihad
153
154			`/*==================================================================================================================`
155			`System inputs.`
156			`==================================================================================================================*/`
157			`// PCI side clock and reset`
158			`input clk_in,`
159			`reset_in ;`
160
161
162			`/*==================================================================================================================`
163			`PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation`
164			`module. Enables are separate signals.`
165			`==================================================================================================================*/`
166			`// master inputs`
167			`input pci_frame_in,`
168	21	mihad	`pci_irdy_in,`
169			`pci_idsel_in ;`
170	2	mihad	`input pci_frame_reg_in,`
171	21	mihad	`pci_irdy_reg_in,`
172			`pci_idsel_reg_in ;`
173
174	2	mihad	`// target response outputs`
175			`output pci_trdy_out,`
176			`pci_stop_out,`
177			`pci_devsel_out ;`
178			`output pci_trdy_en_out,`
179	21	mihad	`pci_stop_en_out,`
180			`pci_devsel_en_out ;`
181			`output ad_load_out ;`
182			`output ad_load_on_transfer_out ;`
183	2	mihad	`// address, data, bus command, byte enable in/outs`
184			`input [31:0] pci_ad_reg_in ;`
185			`output [31:0] pci_ad_out ;`
186			`output pci_ad_en_out ;`
187			`input [3:0] pci_cbe_reg_in ;`
188	21	mihad	`input bckp_trdy_en_in ;`
189			`input bckp_devsel_in ;`
190			`input bckp_trdy_in ;`
191			`input bckp_stop_in ;`
192			`input pci_trdy_reg_in ;`
193			`input pci_stop_reg_in ;`
194	2	mihad
195
196			`/*==================================================================================================================`
197			`Other side of PCI Target state machine`
198			`==================================================================================================================*/`
199			`// Data, byte enables, bus commands and address ports`
200	21	mihad	`output [31:0] address_out ; // current request address output - registered`
201			`input addr_claim_in ; // current request address claim input`
202			`output [3:0] bc_out ; // current request bus command output - registered`
203			`output bc0_out ; // current cycle RW signal output`
204			`input [31:0] data_in ; // for read operations - current dataphase data input`
205			`output [31:0] data_out ; // for write operations - current request data output - registered`
206			`output [3:0] be_out ; // current dataphase byte enable outputs - registered`
207	2	mihad	`// Port connection control signals from PCI FSM`
208	21	mihad	`output req_out ; // Read is requested to WB master`
209			`output rdy_out ; // DATA / ADDRESS selection when read or write - registered`
210			`output addr_phase_out ; // Indicates address phase and also fast-back-to-back address phase - registered`
211			`output bckp_devsel_out ; // DEVSEL output (which is registered) equivalent`
212			`output bckp_trdy_out ; // TRDY output (which is registered) equivalent`
213			`output bckp_stop_out ; // STOP output (which is registered) equivalent`
214			`output last_reg_out ; // Indicates last data phase - registered`
215			`output frame_reg_out ; // FRAME output signal - registered`
216			`output fetch_pcir_fifo_out ;// Read enable for PCIR_FIFO when when read is finishen on WB side`
217			`output load_medium_reg_out ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)`
218			`output sel_fifo_mreg_out ; // Read data selection between PCIR_FIFO and medium register`
219			`output sel_conf_fifo_out ; // Read data selection between Configuration registers and "FIFO"`
220			`output fetch_conf_out ; // Read enable for configuration space registers`
221			`output load_to_pciw_fifo_out ;// Write enable to PCIW_FIFO`
222			`output load_to_conf_out ; // Write enable to Configuration space registers`
223	2	mihad
224
225			`/*==================================================================================================================`
226			`Status`
227			`==================================================================================================================*/`
228	21	mihad	`input same_read_in ; // Indicates the same read request (important when read is finished on WB side)`
229			`input norm_access_to_config_in ; // Indicates the access to Configuration space with MEMORY commands`
230			`input read_completed_in ; // Indicates that read request is completed on WB side`
231			`input read_processing_in ; // Indicates that read request is processing on WB side`
232			`input target_abort_in ; // Indicates target abort termination`
233			`input disconect_wo_data_in ; // Indicates disconnect without data termination`
234			`input disconect_w_data_in ; // Indicates disconnect with data termination`
235			`input pciw_fifo_full_in ; // Indicates that write PCIW_FIFO is full`
236			`input pcir_fifo_data_err_in ; // Indicates data error on current data read from PCIR_FIFO`
237			`input wbw_fifo_empty_in ; // Indicates that WB SLAVE UNIT has no data to be written to PCI bus`
238			`input wbu_del_read_comp_pending_in ; // Indicates that WB S�AVE UNIT has a delayed read pending`
239			`input wbu_frame_en_in ; // Indicates that WB SLAVE UNIT is accessing the PCI bus (important if`
240			`// address on PCI bus is also claimed by decoder in this PCI TARGET UNIT`
241			`output target_abort_set_out ; // Signal used to be set in configuration space registers`
242	2	mihad
243			`/*==================================================================================================================`
244			`END of input / output PORT DEFINITONS !!!`
245			`==================================================================================================================*/`
246
247			`// Delayed frame signal for determining the address phase`
248	21	mihad	`reg previous_frame ;`
249	2	mihad	`// Delayed read completed signal for preparing the data from pcir fifo`
250	21	mihad	`reg read_completed_reg ;`
251			`// Delayed disconnect with/without data for stop loading data to PCIW_FIFO`
252			`//reg disconect_wo_data_reg ;`
253	2	mihad
254	21	mihad	`wire config_disconnect ;`
255			`wire disconect_wo_data = disconect_wo_data_in \|\| config_disconnect ;`
256			`wire disconect_w_data = disconect_w_data_in ;`
257	2	mihad	`// Delayed frame signal for determining the address phase!`
258			`always@(posedge clk_in or posedge reset_in)`
259			`begin`
260	21	mihad	`if (reset_in)`
261			`begin`
262			previous_frame <= #`FF_DELAY 1'b1 ;
263			read_completed_reg <= #`FF_DELAY 1'b0 ;
264			`end`
265	2	mihad	`else`
266	21	mihad	`begin`
267			previous_frame <= #`FF_DELAY pci_frame_reg_in ;
268			read_completed_reg <= #`FF_DELAY read_completed_in ;
269			`end`
270	2	mihad	`end`
271
272			`// Address phase is when previous frame was 1 and this frame is 0 and frame isn't generated from pci master (in WBU)`
273	21	mihad	`wire addr_phase = (previous_frame && ~pci_frame_reg_in && ~wbu_frame_en_in) ;`
274	2	mihad
275	21	mihad	`ifdef HOST
276			`ifdef NO_CNF_IMAGE
277			`// Wire tells when there is configuration (read or write) command with IDSEL signal active`
278			`wire config_access = 1'b0 ;`
279			`// Write and read progresses are used for determining next state`
280			`wire write_progress = ( (read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) \|\|`
281			`(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;`
282			`wire read_progress = ( (read_completed_in && wbw_fifo_empty_in) ) ;`
283			`else
284			`// Wire tells when there is configuration (read or write) command with IDSEL signal active`
285	51	mihad	`wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x)`
286			`(pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle`
287
288	21	mihad	`// Write and read progresses are used for determining next state`
289			`wire write_progress = ( (norm_access_to_config_in) \|\|`
290			`(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) \|\|`
291			`(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;`
292			`wire read_progress = ( (~read_completed_in && norm_access_to_config_in) \|\|`
293			`(read_completed_in && wbw_fifo_empty_in) ) ;`
294			`endif
295			`else
296			`// Wire tells when there is configuration (read or write) command with IDSEL signal active`
297	51	mihad	`wire config_access = (pci_idsel_reg_in && pci_cbe_reg_in[3]) && (~pci_cbe_reg_in[2] && pci_cbe_reg_in[1]) && // idsel asserted with correct bus command(101x)`
298			`(pci_ad_reg_in[1:0] == 2'b00) ; // has to be type 0 configuration cycle`
299
300	21	mihad	`// Write and read progresses are used for determining next state`
301			`wire write_progress = ( (norm_access_to_config_in) \|\|`
302			`(read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) \|\|`
303			`(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) ) ;`
304			`wire read_progress = ( (~read_completed_in && norm_access_to_config_in) \|\|`
305			`(read_completed_in && wbw_fifo_empty_in) ) ;`
306			`endif
307	2	mihad
308	21	mihad	`// Signal for loading data to medium register from pcir fifo when read completed from WB side!`
309			`wire prepare_rd_fifo_data = (read_completed_in && ~read_completed_reg) ;`
310	2	mihad
311			`// Write allowed to PCIW_FIFO`
312	21	mihad	`wire write_to_fifo = ((read_completed_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in) \|\|`
313			`(~read_processing_in && ~pciw_fifo_full_in && ~wbu_del_read_comp_pending_in)) ;`
314	2	mihad	`// Read allowed from PCIR_FIFO`
315	21	mihad	`wire read_from_fifo = (read_completed_in && wbw_fifo_empty_in) ;`
316			`ifdef HOST
317			`ifdef NO_CNF_IMAGE
318			`// Read request is allowed to be proceed regarding the WB side`
319			`wire read_request = (~read_completed_in && ~read_processing_in) ;`
320			`else
321			`// Read request is allowed to be proceed regarding the WB side`
322			`wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;`
323			`endif
324			`else
325			`// Read request is allowed to be proceed regarding the WB side`
326			`wire read_request = (~read_completed_in && ~read_processing_in && ~norm_access_to_config_in) ;`
327			`endif
328	2	mihad
329			`// Critically calculated signals are latched in this clock period (address phase) to be used in the next clock period`
330	21	mihad	`reg rw_cbe0 ;`
331			`reg wr_progress ;`
332			`reg rd_progress ;`
333			`reg rd_from_fifo ;`
334			`reg rd_request ;`
335			`reg wr_to_fifo ;`
336			`reg same_read_reg ;`
337	2	mihad
338			`always@(posedge clk_in or posedge reset_in)`
339			`begin`
340	21	mihad	`if (reset_in)`
341			`begin`
342			rw_cbe0 <= #`FF_DELAY 1'b0 ;
343			wr_progress <= #`FF_DELAY 1'b0 ;
344			rd_progress <= #`FF_DELAY 1'b0 ;
345			rd_from_fifo <= #`FF_DELAY 1'b0 ;
346			rd_request <= #`FF_DELAY 1'b0 ;
347			wr_to_fifo <= #`FF_DELAY 1'b0 ;
348			same_read_reg <= #`FF_DELAY 1'b0 ;
349			`end`
350			`else`
351			`begin`
352			`if (addr_phase)`
353			`begin`
354			rw_cbe0 <= #`FF_DELAY pci_cbe_reg_in[0] ;
355			wr_progress <= #`FF_DELAY write_progress ;
356			rd_progress <= #`FF_DELAY read_progress ;
357			rd_from_fifo <= #`FF_DELAY read_from_fifo ;
358			rd_request <= #`FF_DELAY read_request ;
359			wr_to_fifo <= #`FF_DELAY write_to_fifo ;
360			same_read_reg <= #`FF_DELAY same_read_in ;
361			`end`
362			`end`
363	2	mihad	`end`
364
365	21	mihad	`ifdef HOST
366			`ifdef NO_CNF_IMAGE
367			`wire norm_access_to_conf_reg = 1'b0 ;`
368			`wire cnf_progress = 1'b0 ;`
369			`else
370			`reg norm_access_to_conf_reg ;`
371			`reg cnf_progress ;`
372			`always@(posedge clk_in or posedge reset_in)`
373			`begin`
374			`if (reset_in)`
375			`begin`
376			norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ;
377			cnf_progress <= #`FF_DELAY 1'b0 ;
378			`end`
379			`else`
380			`begin`
381			`if (addr_phase)`
382			`begin`
383			norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
384			cnf_progress <= #`FF_DELAY config_access ;
385			`end`
386			`end`
387			`end`
388			`endif
389			`else
390			`reg norm_access_to_conf_reg ;`
391			`reg cnf_progress ;`
392			`always@(posedge clk_in or posedge reset_in)`
393			`begin`
394			`if (reset_in)`
395			`begin`
396			norm_access_to_conf_reg <= #`FF_DELAY 1'b0 ;
397			cnf_progress <= #`FF_DELAY 1'b0 ;
398			`end`
399			`else`
400			`begin`
401			`if (addr_phase)`
402			`begin`
403			norm_access_to_conf_reg <= #`FF_DELAY norm_access_to_config_in ;
404			cnf_progress <= #`FF_DELAY config_access ;
405			`end`
406			`end`
407			`end`
408			`endif
409
410	2	mihad	`// Signal used in S_WAIT state to determin next state`
411	21	mihad	`wire s_wait_progress = (`
412			`(~cnf_progress && rw_cbe0 && wr_progress && ~target_abort_in) \|\|`
413			`(~cnf_progress && ~rw_cbe0 && same_read_reg && rd_progress && ~target_abort_in && ~pcir_fifo_data_err_in) \|\|`
414			`(~cnf_progress && ~rw_cbe0 && ~same_read_reg && norm_access_to_conf_reg && ~target_abort_in) \|\|`
415			`(cnf_progress && ~target_abort_in)`
416			`) ;`
417	2	mihad
418			`// Signal used in S_TRANSFERE state to determin next state`
419	21	mihad	`wire s_tran_progress = (`
420			`(rw_cbe0 && !disconect_wo_data) \|\|`
421			`(~rw_cbe0 && !disconect_wo_data && !target_abort_in && !pcir_fifo_data_err_in)`
422			`) ;`
423
424	2	mihad	`// Clock enable for PCI state machine driven directly from critical inputs - FRAME and IRDY`
425	21	mihad	`wire pcit_sm_clk_en ;`
426	2	mihad	`// FSM states signals indicating the current state`
427	21	mihad	`reg state_idle ;`
428			`reg state_wait ;`
429			`reg sm_transfere ;`
430			`reg backoff ;`
431			`reg state_default ;`
432			`wire state_backoff = sm_transfere && backoff ;`
433			`wire state_transfere = sm_transfere && !backoff ;`
434
435			`always@(posedge clk_in or posedge reset_in)`
436			`begin`
437			`if ( reset_in )`
438			backoff <= #`FF_DELAY 1'b0 ;
439			`else if ( state_idle )`
440			backoff <= #`FF_DELAY 1'b0 ;
441			`else`
442			backoff <= #`FF_DELAY (state_wait && !s_wait_progress) \|\|
443			`(sm_transfere && !s_tran_progress && !pci_frame_in && !pci_irdy_in) \|\|`
444			`backoff ;`
445			`end`
446			`assign config_disconnect = sm_transfere && (norm_access_to_conf_reg \|\| cnf_progress) ;`
447
448	2	mihad	`// Clock enable module used for preserving the architecture because of minimum delay for critical inputs`
449	21	mihad	`PCI_TARGET32_CLK_EN pci_target_clock_en`
450	2	mihad	`(`
451	21	mihad	`.addr_phase (addr_phase),`
452			`.config_access (config_access),`
453			`.addr_claim_in (addr_claim_in),`
454			`.pci_frame_in (pci_frame_in),`
455			`.state_wait (state_wait),`
456			`.state_transfere (sm_transfere),`
457			`.state_default (state_default),`
458			`.clk_enable (pcit_sm_clk_en)`
459	2	mihad	`);`
460
461	56	mihad	`reg [2:0] c_state ; //current state register`
462			`reg [2:0] n_state ; //next state input to current state register`
463	2	mihad
464			`// state machine register control`
465			`always@(posedge clk_in or posedge reset_in)`
466			`begin`
467			`if (reset_in) // reset state machine to S_IDLE state`
468			c_state <= #`FF_DELAY S_IDLE ;
469			`else`
470	21	mihad	`if (pcit_sm_clk_en) // if conditions are true, then FSM goes to next state!`
471			c_state <= #`FF_DELAY n_state ;
472			`end`
473	2	mihad
474			`// state machine logic`
475	21	mihad	`always@(c_state)`
476	2	mihad	`begin`
477	21	mihad	`case (c_state)`
478			`S_IDLE :`
479			`begin`
480			`state_idle <= 1'b1 ;`
481			`state_wait <= 1'b0 ;`
482			`sm_transfere <= 1'b0 ;`
483			`state_default <= 1'b0 ;`
484			`n_state <= S_WAIT ;`
485			`end`
486			`S_WAIT :`
487			`begin`
488			`state_idle <= 1'b0 ;`
489			`state_wait <= 1'b1 ;`
490			`sm_transfere <= 1'b0 ;`
491			`state_default <= 1'b0 ;`
492			`n_state <= S_TRANSFERE ;`
493			`end`
494			`S_TRANSFERE :`
495			`begin`
496			`state_idle <= 1'b0 ;`
497			`state_wait <= 1'b0 ;`
498			`sm_transfere <= 1'b1 ;`
499			`state_default <= 1'b0 ;`
500			`n_state <= S_IDLE ;`

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