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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of pci bridge project                     ////
////  http://www.opencores.org/cvsweb.shtml/pci/                  ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Miha Dolenc, mihad@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module PCI_TPRAM
(
        // Generic synchronous two-port RAM interface
        clk_a,
    rst_a,
    ce_a,
    we_a,
    oe_a,
    addr_a,
    di_a,
    do_a,
        clk_b,
    rst_b,
    ce_b,
    we_b,
    oe_b,
    addr_b,
    di_b,
    do_b
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef PCI_ARTISAN_SDP
    `define PCI_PCI_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Artisan Synchronous Double-Port RAM (ra2sh)
    //
    art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
    (
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
    );
`endif
 
`ifdef AVANT_ATP
    `define PCI_PCI_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Avant! Asynchronous Two-Port RAM
    //
    avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
    );
`endif
 
`ifdef VIRAGE_STP
    `define PCI_PCI_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Virage Synchronous 2-port R/W RAM
    //
    virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
    );
`endif
 
`ifdef PCI_XILINX_RAMB4
    `define PCI_PCI_RAM_SELECTED
    //
    // Instantiation of FPGA memory:
    //
    // Virtex/Spartan2
    //
 
    //
    // Block 0
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
    );
 
    //
    // Block 1
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
    );
 
    //
    // Block 2
    //
    // block ram2 wires - non generic width of block rams
    wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
    wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
    wire [15:0] blk2_do_a ;
    wire [15:0] blk2_do_b ;
 
    assign do_a[39:32] = blk2_do_a[7:0] ;
    assign do_b[39:32] = blk2_do_b[7:0] ;
 
    RAMB4_S16_S16 ramb4_s16_s16_2(
            .CLKA(clk_a),
            .RSTA(rst_a),
            .ADDRA(addr_a),
            .DIA(blk2_di_a),
            .ENA(ce_a),
            .WEA(we_a),
            .DOA(blk2_do_a),
 
            .CLKB(clk_b),
            .RSTB(rst_b),
            .ADDRB(addr_b),
            .DIB(blk2_di_b),
            .ENB(ce_b),
            .WEB(we_b),
            .DOB(blk2_do_b)
    );
 
`endif
 
`ifdef PCI_XILINX_DIST_RAM
    `define PCI_PCI_RAM_SELECTED
    reg [(aw-1):0] out_address ;
    always@(posedge clk_b or posedge rst_b)
    begin
        if ( rst_b )
            out_address <= #1 0 ;
        else if (ce_b)
            out_address <= #1 addr_b ;
    end
 
    pci_ram_16x40d #(aw) pci_distributed_ram
    (
        .data_out       (do_b),
        .we             (we_a),
        .data_in        (di_a),
        .read_address   (out_address),
        .write_address  (addr_a),
        .wclk           (clk_a)
    );
 
    assign do_a = 0 ;
`endif
 
`ifdef PCI_PCI_RAM_SELECTED
`else
    //
    // Generic two-port synchronous RAM model
    //
 
    //
    // Generic RAM's registers and wires
    //
    reg [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
    reg [dw-1:0] do_reg_a;               // RAM data output register
    reg [dw-1:0] do_reg_b;               // RAM data output register
 
    //
    // Data output drivers
    //
    assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
    assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
    //
    // RAM read and write
    //
    always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
    //
    // RAM read and write
    //
    always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
    if (dw !== 40)
    begin
        $display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
        $finish ;
    end
    `ifdef XILINX_RAMB4
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
    // currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
    `ifdef ARTISAN_SDP
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
end
// synopsys translate_on
 
endmodule

Line No.	Rev	Author	Line
1	18	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of pci bridge project ////`
6			`//// http://www.opencores.org/cvsweb.shtml/pci/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// - Miha Dolenc, mihad@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	49	mihad	`// Revision 1.1 2002/02/01 14:43:31 mihad`
66			`// * empty log message *`
67	18	mihad	`//`
68	49	mihad	`//`
69	18	mihad
70			`// synopsys translate_off`
71			`include "timescale.v"
72			`// synopsys translate_on`
73			`include "pci_constants.v"
74
75			`module PCI_TPRAM`
76			`(`
77			`// Generic synchronous two-port RAM interface`
78			`clk_a,`
79			`rst_a,`
80			`ce_a,`
81			`we_a,`
82			`oe_a,`
83			`addr_a,`
84			`di_a,`
85			`do_a,`
86			`clk_b,`
87			`rst_b,`
88			`ce_b,`
89			`we_b,`
90			`oe_b,`
91			`addr_b,`
92			`di_b,`
93			`do_b`
94			`);`
95
96			`//`
97			`// Default address and data buses width`
98			`//`
99			`parameter aw = 8;`
100			`parameter dw = 40;`
101
102			`//`
103			`// Generic synchronous two-port RAM interface`
104			`//`
105			`input clk_a; // Clock`
106			`input rst_a; // Reset`
107			`input ce_a; // Chip enable input`
108			`input we_a; // Write enable input`
109			`input oe_a; // Output enable input`
110			`input [aw-1:0] addr_a; // address bus inputs`
111			`input [dw-1:0] di_a; // input data bus`
112			`output [dw-1:0] do_a; // output data bus`
113			`input clk_b; // Clock`
114			`input rst_b; // Reset`
115			`input ce_b; // Chip enable input`
116			`input we_b; // Write enable input`
117			`input oe_b; // Output enable input`
118			`input [aw-1:0] addr_b; // address bus inputs`
119			`input [dw-1:0] di_b; // input data bus`
120			`output [dw-1:0] do_b; // output data bus`
121
122			`//`
123			`// Internal wires and registers`
124			`//`
125
126
127			`ifdef PCI_ARTISAN_SDP
128	49	mihad	`define PCI_PCI_RAM_SELECTED
129	18	mihad	`//`
130			`// Instantiation of ASIC memory:`
131			`//`
132			`// Artisan Synchronous Double-Port RAM (ra2sh)`
133			`//`
134			`art_hsdp_256x40 /#(dw, 1<<aw, aw) / artisan_sdp`
135			`(`
136			`.qa(do_a),`
137			`.clka(clk_a),`
138			`.cena(~ce_a),`
139			`.wena(~we_a),`
140			`.aa(addr_a),`
141			`.da(di_a),`
142			`.oena(~oe_a),`
143			`.qb(do_b),`
144			`.clkb(clk_b),`
145			`.cenb(~ce_b),`
146			`.wenb(~we_b),`
147			`.ab(addr_b),`
148			`.db(di_b),`
149			`.oenb(~oe_b)`
150			`);`
151			`endif
152
153			`ifdef AVANT_ATP
154	49	mihad	`define PCI_PCI_RAM_SELECTED
155	18	mihad	`//`
156			`// Instantiation of ASIC memory:`
157			`//`
158			`// Avant! Asynchronous Two-Port RAM`
159			`//`
160			`avant_atp avant_atp(`
161			`.web(~we),`
162			`.reb(),`
163			`.oeb(~oe),`
164			`.rcsb(),`
165			`.wcsb(),`
166			`.ra(addr),`
167			`.wa(addr),`
168			`.di(di),`
169			`.do(do)`
170			`);`
171			`endif
172
173			`ifdef VIRAGE_STP
174	49	mihad	`define PCI_PCI_RAM_SELECTED
175	18	mihad	`//`
176			`// Instantiation of ASIC memory:`
177			`//`
178			`// Virage Synchronous 2-port R/W RAM`
179			`//`
180			`virage_stp virage_stp(`
181			`.QA(do_a),`
182			`.QB(do_b),`
183
184			`.ADRA(addr_a),`
185			`.DA(di_a),`
186			`.WEA(we_a),`
187			`.OEA(oe_a),`
188			`.MEA(ce_a),`
189			`.CLKA(clk_a),`
190
191			`.ADRB(adr_b),`
192			`.DB(di_b),`
193			`.WEB(we_b),`
194			`.OEB(oe_b),`
195			`.MEB(ce_b),`
196			`.CLKB(clk_b)`
197			`);`
198			`endif
199
200			`ifdef PCI_XILINX_RAMB4
201	49	mihad	`define PCI_PCI_RAM_SELECTED
202	18	mihad	`//`
203			`// Instantiation of FPGA memory:`
204			`//`
205			`// Virtex/Spartan2`
206			`//`
207
208			`//`
209			`// Block 0`
210			`//`
211
212			`RAMB4_S16_S16 ramb4_s16_s16_0(`
213			`.CLKA(clk_a),`
214			`.RSTA(rst_a),`
215			`.ADDRA(addr_a),`
216			`.DIA(di_a[15:0]),`
217			`.ENA(ce_a),`
218			`.WEA(we_a),`
219			`.DOA(do_a[15:0]),`
220
221			`.CLKB(clk_b),`
222			`.RSTB(rst_b),`
223			`.ADDRB(addr_b),`
224			`.DIB(di_b[15:0]),`
225			`.ENB(ce_b),`
226			`.WEB(we_b),`
227			`.DOB(do_b[15:0])`
228			`);`
229
230			`//`
231			`// Block 1`
232			`//`
233
234			`RAMB4_S16_S16 ramb4_s16_s16_1(`
235			`.CLKA(clk_a),`
236			`.RSTA(rst_a),`
237			`.ADDRA(addr_a),`
238			`.DIA(di_a[31:16]),`
239			`.ENA(ce_a),`
240			`.WEA(we_a),`
241			`.DOA(do_a[31:16]),`
242
243			`.CLKB(clk_b),`
244			`.RSTB(rst_b),`
245			`.ADDRB(addr_b),`
246			`.DIB(di_b[31:16]),`
247			`.ENB(ce_b),`
248			`.WEB(we_b),`
249			`.DOB(do_b[31:16])`
250			`);`
251
252			`//`
253			`// Block 2`
254			`//`
255			`// block ram2 wires - non generic width of block rams`
256			`wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;`
257			`wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;`
258
259			`wire [15:0] blk2_do_a ;`
260			`wire [15:0] blk2_do_b ;`
261
262			`assign do_a[39:32] = blk2_do_a[7:0] ;`
263			`assign do_b[39:32] = blk2_do_b[7:0] ;`
264
265			`RAMB4_S16_S16 ramb4_s16_s16_2(`
266			`.CLKA(clk_a),`
267			`.RSTA(rst_a),`
268			`.ADDRA(addr_a),`
269			`.DIA(blk2_di_a),`
270			`.ENA(ce_a),`
271			`.WEA(we_a),`
272			`.DOA(blk2_do_a),`
273
274			`.CLKB(clk_b),`
275			`.RSTB(rst_b),`
276			`.ADDRB(addr_b),`
277			`.DIB(blk2_di_b),`
278			`.ENB(ce_b),`
279			`.WEB(we_b),`
280			`.DOB(blk2_do_b)`
281			`);`
282
283			`endif
284
285			`ifdef PCI_XILINX_DIST_RAM
286	49	mihad	`define PCI_PCI_RAM_SELECTED
287	18	mihad	`reg [(aw-1):0] out_address ;`
288			`always@(posedge clk_b or posedge rst_b)`
289			`begin`
290			`if ( rst_b )`
291			`out_address <= #1 0 ;`
292			`else if (ce_b)`
293			`out_address <= #1 addr_b ;`
294			`end`
295
296	49	mihad	`pci_ram_16x40d #(aw) pci_distributed_ram`
297	18	mihad	`(`
298			`.data_out (do_b),`
299			`.we (we_a),`
300			`.data_in (di_a),`
301			`.read_address (out_address),`
302			`.write_address (addr_a),`
303			`.wclk (clk_a)`
304			`);`
305	49	mihad
306			`assign do_a = 0 ;`
307	18	mihad	`endif
308
309	49	mihad	`ifdef PCI_PCI_RAM_SELECTED
310	18	mihad	`else
311			`//`
312			`// Generic two-port synchronous RAM model`
313			`//`
314
315			`//`
316			`// Generic RAM's registers and wires`
317			`//`
318			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
319			`reg [dw-1:0] do_reg_a; // RAM data output register`
320			`reg [dw-1:0] do_reg_b; // RAM data output register`
321
322			`//`
323			`// Data output drivers`
324			`//`
325			`assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};`
326			`assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};`
327
328			`//`
329			`// RAM read and write`
330			`//`
331			`always @(posedge clk_a)`
332			`if (ce_a && !we_a)`
333			`do_reg_a <= #1 mem[addr_a];`
334			`else if (ce_a && we_a)`
335			`mem[addr_a] <= #1 di_a;`
336
337			`//`
338			`// RAM read and write`
339			`//`
340			`always @(posedge clk_b)`
341			`if (ce_b && !we_b)`
342			`do_reg_b <= #1 mem[addr_b];`
343			`else if (ce_b && we_b)`
344			`mem[addr_b] <= #1 di_b;`
345			`endif
346
347			`// synopsys translate_off`
348			`initial`
349			`begin`
350			`if (dw !== 40)`
351			`begin`
352			`$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;`
353			`$finish ;`
354			`end`
355			`ifdef XILINX_RAMB4
356			`if (aw !== 8)`
357			`begin`
358			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
359			`$finish ;`
360			`end`
361			`endif
362			`// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models`
363			`ifdef ARTISAN_SDP
364			`if (aw !== 8)`
365			`begin`
366			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
367			`$finish ;`
368			`end`
369			`endif
370			`end`
371			`// synopsys translate_on`
372
373			`endmodule`

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