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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_addr_mux.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_addr_mux.v"                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images
`include "constants.v"
 
module WB_ADDR_MUX
(
    address_in,
    bar0_in,
    bar1_in,
    bar2_in,
    bar3_in,
    bar4_in,
    bar5_in,
    am0_in,
    am1_in,
    am2_in,
    am3_in,
    am4_in,
    am5_in,
    ta0_in,
    ta1_in,
    ta2_in,
    ta3_in,
    ta4_in,
    ta5_in,
    at_en_in,
    hit_out,
    address_out
);
 
input [31:0] address_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in   ;
input [5:0]  at_en_in ;
output [5:0] hit_out  ;
output [31:0] address_out ;
reg    [31:0] address_out ;
 
wire [31:0] addr0 ;
wire [31:0] addr1 ;
wire [31:0] addr2 ;
wire [31:0] addr3 ;
wire [31:0] addr4 ;
wire [31:0] addr5 ;
 
wire [5:0] hit ;
assign hit_out = hit ;
 
`ifdef GUEST
    // in guest bridge implementation configuration image can be taken out
    `ifdef WB_CNF_IMAGE
        DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
                        .hit       (hit[0]),
                        .addr_out  (addr0),
                        .addr_in   (address_in),
                        .base_addr (bar0_in),
                        .mask_addr (am0_in),
                        .tran_addr (ta0_in),
                        .at_en     (1'b0)
                    ) ;
    `else
 
        // configuration image not implemented
        assign hit[0] = 1'b0 ;
        assign addr0  = 32'h0000_0000 ;
    `endif
`else
    `ifdef HOST
        DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
                        .hit       (hit[0]),
                        .addr_out  (addr0),
                        .addr_in   (address_in),
                        .base_addr (bar0_in),
                        .mask_addr (am0_in),
                        .tran_addr (ta0_in),
                        .at_en     (1'b0)
                    ) ;
    `endif
`endif
 
// one image is always implemented
DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec1(
                .hit       (hit[1]),
                .addr_out  (addr1),
                .addr_in   (address_in),
                .base_addr (bar1_in),
                .mask_addr (am1_in),
                .tran_addr (ta1_in),
                .at_en     (at_en_in[1])
             ) ;
 
`ifdef WB_IMAGE2
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
                assign hit[5:3] = 3'b000 ;
                assign addr3    = 32'h0000_0000 ;
                assign addr4    = 32'h0000_0000 ;
                assign addr5    = 32'h0000_0000 ;
 
                // address multiplexer
                always@(hit or addr0 or addr1 or addr2)
                begin
                    address_out = addr0 ;
                    if ( hit[1] )
                        address_out = addr1 ;
                    else if ( hit[2] )
                        address_out = addr2 ;
                end
 
`else
    `ifdef WB_IMAGE3
 
        assign hit[5:4] = 2'b00 ;
        assign addr4    = 32'h0000_0000 ;
        assign addr5    = 32'h0000_0000 ;
 
        // address multiplexer
        always@(hit or addr0 or addr1 or addr2 or addr3)
        begin
            address_out = addr0 ;
            if ( hit[1] )
                address_out = addr1 ;
            else if ( hit[2] )
                address_out = addr2 ;
            else if ( hit[3] )
                address_out = addr3 ;
        end
 
 
    `else
        `ifdef WB_IMAGE4
 
            assign hit[5] = 1'b0 ;
            assign addr5    = 32'h0000_0000 ;
 
            // address multiplexer
            always@(hit or addr0 or addr1 or addr2 or addr3 or addr4)
            begin
                address_out = addr0 ;
                if ( hit[1] )
                    address_out = addr1 ;
                else if ( hit[2] )
                    address_out = addr2 ;
                else if ( hit[3] )
                    address_out = addr3 ;
                else if ( hit[4] )
                    address_out = addr4 ;
            end
 
        `else
            `ifdef WB_IMAGE5
                // address multiplexer
                always@(hit or addr0 or addr1 or addr2 or addr3 or addr4 or addr5)
                begin
                    address_out = addr0 ;
                    if ( hit[1] )
                        address_out = addr1 ;
                    else if ( hit[2] )
                        address_out = addr2 ;
                    else if ( hit[3] )
                        address_out = addr3 ;
                    else if ( hit[4] )
                        address_out = addr4 ;
                    else if ( hit[5] )
                        address_out = addr5 ;
                end
 
            `else
 
                assign hit[5:2] = 4'b0000 ;
                assign addr2    = 32'h0000_0000 ;
                assign addr3    = 32'h0000_0000 ;
                assign addr4    = 32'h0000_0000 ;
                assign addr5    = 32'h0000_0000 ;
 
                // address multiplexer
                always@(hit or addr0 or addr1)
                begin
                    address_out = addr0 ;
                    if ( hit[1] )
                        address_out = addr1 ;
                end
 
            `endif
        `endif
    `endif
`endif
 
`ifdef WB_IMAGE3
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
                    .hit       (hit[3]),
                    .addr_out  (addr3),
                    .addr_in   (address_in),
                    .base_addr (bar3_in),
                    .mask_addr (am3_in),
                    .tran_addr (ta3_in),
                    .at_en     (at_en_in[3])
                ) ;
`endif
 
`ifdef WB_IMAGE4
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
                    .hit       (hit[3]),
                    .addr_out  (addr3),
                    .addr_in   (address_in),
                    .base_addr (bar3_in),
                    .mask_addr (am3_in),
                    .tran_addr (ta3_in),
                    .at_en     (at_en_in[3])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
                    .hit       (hit[4]),
                    .addr_out  (addr4),
                    .addr_in   (address_in),
                    .base_addr (bar4_in),
                    .mask_addr (am4_in),
                    .tran_addr (ta4_in),
                    .at_en     (at_en_in[4])
                ) ;
`endif
 
`ifdef WB_IMAGE5
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
                    .hit       (hit[3]),
                    .addr_out  (addr3),
                    .addr_in   (address_in),
                    .base_addr (bar3_in),
                    .mask_addr (am3_in),
                    .tran_addr (ta3_in),
                    .at_en     (at_en_in[3])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
                    .hit       (hit[4]),
                    .addr_out  (addr4),
                    .addr_in   (address_in),
                    .base_addr (bar4_in),
                    .mask_addr (am4_in),
                    .tran_addr (ta4_in),
                    .at_en     (at_en_in[4])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec5(
                    .hit       (hit[5]),
                    .addr_out  (addr5),
                    .addr_in   (address_in),
                    .base_addr (bar5_in),
                    .mask_addr (am5_in),
                    .tran_addr (ta5_in),
                    .at_en     (at_en_in[5])
                ) ;
`endif
endmodule

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_addr_mux.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_addr_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`//`
46
47			`// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images`
48			`include "constants.v"
49
50			`module WB_ADDR_MUX`
51			`(`
52			`address_in,`
53			`bar0_in,`
54			`bar1_in,`
55			`bar2_in,`
56			`bar3_in,`
57			`bar4_in,`
58			`bar5_in,`
59			`am0_in,`
60			`am1_in,`
61			`am2_in,`
62			`am3_in,`
63			`am4_in,`
64			`am5_in,`
65			`ta0_in,`
66			`ta1_in,`
67			`ta2_in,`
68			`ta3_in,`
69			`ta4_in,`
70			`ta5_in,`
71			`at_en_in,`
72			`hit_out,`
73			`address_out`
74			`);`
75
76			`input [31:0] address_in ;`
77			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
78			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
79			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
80			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
81			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
82			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
83			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
84			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
85			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
86			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
87			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
88			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
89			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
90			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
91			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
92			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
93			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
94			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
95			`input [5:0] at_en_in ;`
96			`output [5:0] hit_out ;`
97			`output [31:0] address_out ;`
98			`reg [31:0] address_out ;`
99
100			`wire [31:0] addr0 ;`
101			`wire [31:0] addr1 ;`
102			`wire [31:0] addr2 ;`
103			`wire [31:0] addr3 ;`
104			`wire [31:0] addr4 ;`
105			`wire [31:0] addr5 ;`
106
107			`wire [5:0] hit ;`
108			`assign hit_out = hit ;`
109
110			`ifdef GUEST
111			`// in guest bridge implementation configuration image can be taken out`
112			`ifdef WB_CNF_IMAGE
113			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
114			`.hit (hit[0]),`
115			`.addr_out (addr0),`
116			`.addr_in (address_in),`
117			`.base_addr (bar0_in),`
118			`.mask_addr (am0_in),`
119			`.tran_addr (ta0_in),`
120			`.at_en (1'b0)`
121			`) ;`
122			`else
123
124			`// configuration image not implemented`
125			`assign hit[0] = 1'b0 ;`
126			`assign addr0 = 32'h0000_0000 ;`
127			`endif
128			`else
129			`ifdef HOST
130			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
131			`.hit (hit[0]),`
132			`.addr_out (addr0),`
133			`.addr_in (address_in),`
134			`.base_addr (bar0_in),`
135			`.mask_addr (am0_in),`
136			`.tran_addr (ta0_in),`
137			`.at_en (1'b0)`
138			`) ;`
139			`endif
140			`endif
141
142			`// one image is always implemented`
143			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec1(
144			`.hit (hit[1]),`
145			`.addr_out (addr1),`
146			`.addr_in (address_in),`
147			`.base_addr (bar1_in),`
148			`.mask_addr (am1_in),`
149			`.tran_addr (ta1_in),`
150			`.at_en (at_en_in[1])`
151			`) ;`
152
153			`ifdef WB_IMAGE2
154			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
155			`.hit (hit[2]),`
156			`.addr_out (addr2),`
157			`.addr_in (address_in),`
158			`.base_addr (bar2_in),`
159			`.mask_addr (am2_in),`
160			`.tran_addr (ta2_in),`
161			`.at_en (at_en_in[2])`
162			`) ;`
163
164			`assign hit[5:3] = 3'b000 ;`
165			`assign addr3 = 32'h0000_0000 ;`
166			`assign addr4 = 32'h0000_0000 ;`
167			`assign addr5 = 32'h0000_0000 ;`
168
169			`// address multiplexer`
170			`always@(hit or addr0 or addr1 or addr2)`
171			`begin`
172			`address_out = addr0 ;`
173			`if ( hit[1] )`
174			`address_out = addr1 ;`
175			`else if ( hit[2] )`
176			`address_out = addr2 ;`
177			`end`
178
179			`else
180			`ifdef WB_IMAGE3
181
182			`assign hit[5:4] = 2'b00 ;`
183			`assign addr4 = 32'h0000_0000 ;`
184			`assign addr5 = 32'h0000_0000 ;`
185
186			`// address multiplexer`
187			`always@(hit or addr0 or addr1 or addr2 or addr3)`
188			`begin`
189			`address_out = addr0 ;`
190			`if ( hit[1] )`
191			`address_out = addr1 ;`
192			`else if ( hit[2] )`
193			`address_out = addr2 ;`
194			`else if ( hit[3] )`
195			`address_out = addr3 ;`
196			`end`
197
198
199			`else
200			`ifdef WB_IMAGE4
201
202			`assign hit[5] = 1'b0 ;`
203			`assign addr5 = 32'h0000_0000 ;`
204
205			`// address multiplexer`
206			`always@(hit or addr0 or addr1 or addr2 or addr3 or addr4)`
207			`begin`
208			`address_out = addr0 ;`
209			`if ( hit[1] )`
210			`address_out = addr1 ;`
211			`else if ( hit[2] )`
212			`address_out = addr2 ;`
213			`else if ( hit[3] )`
214			`address_out = addr3 ;`
215			`else if ( hit[4] )`
216			`address_out = addr4 ;`
217			`end`
218
219			`else
220			`ifdef WB_IMAGE5
221			`// address multiplexer`
222			`always@(hit or addr0 or addr1 or addr2 or addr3 or addr4 or addr5)`
223			`begin`
224			`address_out = addr0 ;`
225			`if ( hit[1] )`
226			`address_out = addr1 ;`
227			`else if ( hit[2] )`
228			`address_out = addr2 ;`
229			`else if ( hit[3] )`
230			`address_out = addr3 ;`
231			`else if ( hit[4] )`
232			`address_out = addr4 ;`
233			`else if ( hit[5] )`
234			`address_out = addr5 ;`
235			`end`
236
237			`else
238
239			`assign hit[5:2] = 4'b0000 ;`
240			`assign addr2 = 32'h0000_0000 ;`
241			`assign addr3 = 32'h0000_0000 ;`
242			`assign addr4 = 32'h0000_0000 ;`
243			`assign addr5 = 32'h0000_0000 ;`
244
245			`// address multiplexer`
246			`always@(hit or addr0 or addr1)`
247			`begin`
248			`address_out = addr0 ;`
249			`if ( hit[1] )`
250			`address_out = addr1 ;`
251			`end`
252
253			`endif
254			`endif
255			`endif
256			`endif
257
258			`ifdef WB_IMAGE3
259			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
260			`.hit (hit[2]),`
261			`.addr_out (addr2),`
262			`.addr_in (address_in),`
263			`.base_addr (bar2_in),`
264			`.mask_addr (am2_in),`
265			`.tran_addr (ta2_in),`
266			`.at_en (at_en_in[2])`
267			`) ;`
268
269			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
270			`.hit (hit[3]),`
271			`.addr_out (addr3),`
272			`.addr_in (address_in),`
273			`.base_addr (bar3_in),`
274			`.mask_addr (am3_in),`
275			`.tran_addr (ta3_in),`
276			`.at_en (at_en_in[3])`
277			`) ;`
278			`endif
279
280			`ifdef WB_IMAGE4
281			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
282			`.hit (hit[2]),`
283			`.addr_out (addr2),`
284			`.addr_in (address_in),`
285			`.base_addr (bar2_in),`
286			`.mask_addr (am2_in),`
287			`.tran_addr (ta2_in),`
288			`.at_en (at_en_in[2])`
289			`) ;`
290
291			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
292			`.hit (hit[3]),`
293			`.addr_out (addr3),`
294			`.addr_in (address_in),`
295			`.base_addr (bar3_in),`
296			`.mask_addr (am3_in),`
297			`.tran_addr (ta3_in),`
298			`.at_en (at_en_in[3])`
299			`) ;`
300
301			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
302			`.hit (hit[4]),`
303			`.addr_out (addr4),`
304			`.addr_in (address_in),`
305			`.base_addr (bar4_in),`
306			`.mask_addr (am4_in),`
307			`.tran_addr (ta4_in),`
308			`.at_en (at_en_in[4])`
309			`) ;`
310			`endif
311
312			`ifdef WB_IMAGE5
313			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
314			`.hit (hit[2]),`
315			`.addr_out (addr2),`
316			`.addr_in (address_in),`
317			`.base_addr (bar2_in),`
318			`.mask_addr (am2_in),`
319			`.tran_addr (ta2_in),`
320			`.at_en (at_en_in[2])`
321			`) ;`
322
323			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
324			`.hit (hit[3]),`
325			`.addr_out (addr3),`
326			`.addr_in (address_in),`
327			`.base_addr (bar3_in),`
328			`.mask_addr (am3_in),`
329			`.tran_addr (ta3_in),`
330			`.at_en (at_en_in[3])`
331			`) ;`
332
333			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
334			`.hit (hit[4]),`
335			`.addr_out (addr4),`
336			`.addr_in (address_in),`
337			`.base_addr (bar4_in),`
338			`.mask_addr (am4_in),`
339			`.tran_addr (ta4_in),`
340			`.at_en (at_en_in[4])`
341			`) ;`
342
343			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec5(
344			`.hit (hit[5]),`
345			`.addr_out (addr5),`
346			`.addr_in (address_in),`
347			`.base_addr (bar5_in),`
348			`.mask_addr (am5_in),`
349			`.tran_addr (ta5_in),`
350			`.at_en (at_en_in[5])`
351			`) ;`
352			`endif
353			`endmodule`