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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_addr_mux.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_addr_mux.v"                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
//
//
 
// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images
`include "constants.v"
`include "timescale.v"
 
module WB_ADDR_MUX
(
    address_in,
    bar0_in,
    bar1_in,
    bar2_in,
    bar3_in,
    bar4_in,
    bar5_in,
    am0_in,
    am1_in,
    am2_in,
    am3_in,
    am4_in,
    am5_in,
    ta0_in,
    ta1_in,
    ta2_in,
    ta3_in,
    ta4_in,
    ta5_in,
    at_en_in,
    hit_out,
    address_out
);
 
input [31:0] address_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in   ;
input [5:0]  at_en_in ;
output [5:0] hit_out  ;
output [31:0] address_out ;
reg    [31:0] address_out ;
 
wire [31:0] addr0 ;
wire [31:0] addr1 ;
wire [31:0] addr2 ;
wire [31:0] addr3 ;
wire [31:0] addr4 ;
wire [31:0] addr5 ;
 
wire [5:0] hit ;
assign hit_out = hit ;
 
`ifdef GUEST
    // in guest bridge implementation configuration image can be taken out
    `ifdef WB_CNF_IMAGE
        DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
                        .hit       (hit[0]),
                        .addr_out  (addr0),
                        .addr_in   (address_in),
                        .base_addr (bar0_in),
                        .mask_addr (am0_in),
                        .tran_addr (ta0_in),
                        .at_en     (1'b0)
                    ) ;
    `else
 
        // configuration image not implemented
        assign hit[0] = 1'b0 ;
        assign addr0  = 32'h0000_0000 ;
    `endif
`else
    `ifdef HOST
        DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
                        .hit       (hit[0]),
                        .addr_out  (addr0),
                        .addr_in   (address_in),
                        .base_addr (bar0_in),
                        .mask_addr (am0_in),
                        .tran_addr (ta0_in),
                        .at_en     (1'b0)
                    ) ;
    `endif
`endif
 
// one image is always implemented
DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec1(
                .hit       (hit[1]),
                .addr_out  (addr1),
                .addr_in   (address_in),
                .base_addr (bar1_in),
                .mask_addr (am1_in),
                .tran_addr (ta1_in),
                .at_en     (at_en_in[1])
             ) ;
 
`ifdef WB_IMAGE2
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
                assign hit[5:3] = 3'b000 ;
                assign addr3    = 32'h0000_0000 ;
                assign addr4    = 32'h0000_0000 ;
                assign addr5    = 32'h0000_0000 ;
 
                // address multiplexer
                always@(hit or addr0 or addr1 or addr2)
                begin
                    address_out = addr0 ;
                    if ( hit[1] )
                        address_out = addr1 ;
                    else if ( hit[2] )
                        address_out = addr2 ;
                end
 
`else
    `ifdef WB_IMAGE3
 
        assign hit[5:4] = 2'b00 ;
        assign addr4    = 32'h0000_0000 ;
        assign addr5    = 32'h0000_0000 ;
 
        // address multiplexer
        always@(hit or addr0 or addr1 or addr2 or addr3)
        begin
            address_out = addr0 ;
            if ( hit[1] )
                address_out = addr1 ;
            else if ( hit[2] )
                address_out = addr2 ;
            else if ( hit[3] )
                address_out = addr3 ;
        end
 
 
    `else
        `ifdef WB_IMAGE4
 
            assign hit[5] = 1'b0 ;
            assign addr5    = 32'h0000_0000 ;
 
            // address multiplexer
            always@(hit or addr0 or addr1 or addr2 or addr3 or addr4)
            begin
                address_out = addr0 ;
                if ( hit[1] )
                    address_out = addr1 ;
                else if ( hit[2] )
                    address_out = addr2 ;
                else if ( hit[3] )
                    address_out = addr3 ;
                else if ( hit[4] )
                    address_out = addr4 ;
            end
 
        `else
            `ifdef WB_IMAGE5
                // address multiplexer
                always@(hit or addr0 or addr1 or addr2 or addr3 or addr4 or addr5)
                begin
                    address_out = addr0 ;
                    if ( hit[1] )
                        address_out = addr1 ;
                    else if ( hit[2] )
                        address_out = addr2 ;
                    else if ( hit[3] )
                        address_out = addr3 ;
                    else if ( hit[4] )
                        address_out = addr4 ;
                    else if ( hit[5] )
                        address_out = addr5 ;
                end
 
            `else
 
                assign hit[5:2] = 4'b0000 ;
                assign addr2    = 32'h0000_0000 ;
                assign addr3    = 32'h0000_0000 ;
                assign addr4    = 32'h0000_0000 ;
                assign addr5    = 32'h0000_0000 ;
 
                // address multiplexer
                always@(hit or addr0 or addr1)
                begin
                    address_out = addr0 ;
                    if ( hit[1] )
                        address_out = addr1 ;
                end
 
            `endif
        `endif
    `endif
`endif
 
`ifdef WB_IMAGE3
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
                    .hit       (hit[3]),
                    .addr_out  (addr3),
                    .addr_in   (address_in),
                    .base_addr (bar3_in),
                    .mask_addr (am3_in),
                    .tran_addr (ta3_in),
                    .at_en     (at_en_in[3])
                ) ;
`endif
 
`ifdef WB_IMAGE4
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
                    .hit       (hit[3]),
                    .addr_out  (addr3),
                    .addr_in   (address_in),
                    .base_addr (bar3_in),
                    .mask_addr (am3_in),
                    .tran_addr (ta3_in),
                    .at_en     (at_en_in[3])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
                    .hit       (hit[4]),
                    .addr_out  (addr4),
                    .addr_in   (address_in),
                    .base_addr (bar4_in),
                    .mask_addr (am4_in),
                    .tran_addr (ta4_in),
                    .at_en     (at_en_in[4])
                ) ;
`endif
 
`ifdef WB_IMAGE5
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
                    .hit       (hit[2]),
                    .addr_out  (addr2),
                    .addr_in   (address_in),
                    .base_addr (bar2_in),
                    .mask_addr (am2_in),
                    .tran_addr (ta2_in),
                    .at_en     (at_en_in[2])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
                    .hit       (hit[3]),
                    .addr_out  (addr3),
                    .addr_in   (address_in),
                    .base_addr (bar3_in),
                    .mask_addr (am3_in),
                    .tran_addr (ta3_in),
                    .at_en     (at_en_in[3])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
                    .hit       (hit[4]),
                    .addr_out  (addr4),
                    .addr_in   (address_in),
                    .base_addr (bar4_in),
                    .mask_addr (am4_in),
                    .tran_addr (ta4_in),
                    .at_en     (at_en_in[4])
                ) ;
 
    DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec5(
                    .hit       (hit[5]),
                    .addr_out  (addr5),
                    .addr_in   (address_in),
                    .base_addr (bar5_in),
                    .mask_addr (am5_in),
                    .tran_addr (ta5_in),
                    .at_en     (at_en_in[5])
                ) ;
`endif
endmodule

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_addr_mux.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_addr_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:47 mihad`
46			`// New project directory structure`
47	2	mihad	`//`
48	6	mihad	`//`
49	2	mihad
50			`// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images`
51			`include "constants.v"
52	6	mihad	`include "timescale.v"
53	2	mihad
54			`module WB_ADDR_MUX`
55			`(`
56			`address_in,`
57			`bar0_in,`
58			`bar1_in,`
59			`bar2_in,`
60			`bar3_in,`
61			`bar4_in,`
62			`bar5_in,`
63			`am0_in,`
64			`am1_in,`
65			`am2_in,`
66			`am3_in,`
67			`am4_in,`
68			`am5_in,`
69			`ta0_in,`
70			`ta1_in,`
71			`ta2_in,`
72			`ta3_in,`
73			`ta4_in,`
74			`ta5_in,`
75			`at_en_in,`
76			`hit_out,`
77			`address_out`
78			`);`
79
80			`input [31:0] address_in ;`
81			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
82			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
83			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
84			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
85			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
86			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
87			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
88			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
89			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
90			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
91			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
92			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
93			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
94			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
95			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
96			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
97			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
98			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
99			`input [5:0] at_en_in ;`
100			`output [5:0] hit_out ;`
101			`output [31:0] address_out ;`
102			`reg [31:0] address_out ;`
103
104			`wire [31:0] addr0 ;`
105			`wire [31:0] addr1 ;`
106			`wire [31:0] addr2 ;`
107			`wire [31:0] addr3 ;`
108			`wire [31:0] addr4 ;`
109			`wire [31:0] addr5 ;`
110
111			`wire [5:0] hit ;`
112			`assign hit_out = hit ;`
113
114			`ifdef GUEST
115			`// in guest bridge implementation configuration image can be taken out`
116			`ifdef WB_CNF_IMAGE
117			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
118			`.hit (hit[0]),`
119			`.addr_out (addr0),`
120			`.addr_in (address_in),`
121			`.base_addr (bar0_in),`
122			`.mask_addr (am0_in),`
123			`.tran_addr (ta0_in),`
124			`.at_en (1'b0)`
125			`) ;`
126			`else
127
128			`// configuration image not implemented`
129			`assign hit[0] = 1'b0 ;`
130			`assign addr0 = 32'h0000_0000 ;`
131			`endif
132			`else
133			`ifdef HOST
134			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec0(
135			`.hit (hit[0]),`
136			`.addr_out (addr0),`
137			`.addr_in (address_in),`
138			`.base_addr (bar0_in),`
139			`.mask_addr (am0_in),`
140			`.tran_addr (ta0_in),`
141			`.at_en (1'b0)`
142			`) ;`
143			`endif
144			`endif
145
146			`// one image is always implemented`
147			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec1(
148			`.hit (hit[1]),`
149			`.addr_out (addr1),`
150			`.addr_in (address_in),`
151			`.base_addr (bar1_in),`
152			`.mask_addr (am1_in),`
153			`.tran_addr (ta1_in),`
154			`.at_en (at_en_in[1])`
155			`) ;`
156
157			`ifdef WB_IMAGE2
158			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
159			`.hit (hit[2]),`
160			`.addr_out (addr2),`
161			`.addr_in (address_in),`
162			`.base_addr (bar2_in),`
163			`.mask_addr (am2_in),`
164			`.tran_addr (ta2_in),`
165			`.at_en (at_en_in[2])`
166			`) ;`
167
168			`assign hit[5:3] = 3'b000 ;`
169			`assign addr3 = 32'h0000_0000 ;`
170			`assign addr4 = 32'h0000_0000 ;`
171			`assign addr5 = 32'h0000_0000 ;`
172
173			`// address multiplexer`
174			`always@(hit or addr0 or addr1 or addr2)`
175			`begin`
176			`address_out = addr0 ;`
177			`if ( hit[1] )`
178			`address_out = addr1 ;`
179			`else if ( hit[2] )`
180			`address_out = addr2 ;`
181			`end`
182
183			`else
184			`ifdef WB_IMAGE3
185
186			`assign hit[5:4] = 2'b00 ;`
187			`assign addr4 = 32'h0000_0000 ;`
188			`assign addr5 = 32'h0000_0000 ;`
189
190			`// address multiplexer`
191			`always@(hit or addr0 or addr1 or addr2 or addr3)`
192			`begin`
193			`address_out = addr0 ;`
194			`if ( hit[1] )`
195			`address_out = addr1 ;`
196			`else if ( hit[2] )`
197			`address_out = addr2 ;`
198			`else if ( hit[3] )`
199			`address_out = addr3 ;`
200			`end`
201
202
203			`else
204			`ifdef WB_IMAGE4
205
206			`assign hit[5] = 1'b0 ;`
207			`assign addr5 = 32'h0000_0000 ;`
208
209			`// address multiplexer`
210			`always@(hit or addr0 or addr1 or addr2 or addr3 or addr4)`
211			`begin`
212			`address_out = addr0 ;`
213			`if ( hit[1] )`
214			`address_out = addr1 ;`
215			`else if ( hit[2] )`
216			`address_out = addr2 ;`
217			`else if ( hit[3] )`
218			`address_out = addr3 ;`
219			`else if ( hit[4] )`
220			`address_out = addr4 ;`
221			`end`
222
223			`else
224			`ifdef WB_IMAGE5
225			`// address multiplexer`
226			`always@(hit or addr0 or addr1 or addr2 or addr3 or addr4 or addr5)`
227			`begin`
228			`address_out = addr0 ;`
229			`if ( hit[1] )`
230			`address_out = addr1 ;`
231			`else if ( hit[2] )`
232			`address_out = addr2 ;`
233			`else if ( hit[3] )`
234			`address_out = addr3 ;`
235			`else if ( hit[4] )`
236			`address_out = addr4 ;`
237			`else if ( hit[5] )`
238			`address_out = addr5 ;`
239			`end`
240
241			`else
242
243			`assign hit[5:2] = 4'b0000 ;`
244			`assign addr2 = 32'h0000_0000 ;`
245			`assign addr3 = 32'h0000_0000 ;`
246			`assign addr4 = 32'h0000_0000 ;`
247			`assign addr5 = 32'h0000_0000 ;`
248
249			`// address multiplexer`
250			`always@(hit or addr0 or addr1)`
251			`begin`
252			`address_out = addr0 ;`
253			`if ( hit[1] )`
254			`address_out = addr1 ;`
255			`end`
256
257			`endif
258			`endif
259			`endif
260			`endif
261
262			`ifdef WB_IMAGE3
263			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
264			`.hit (hit[2]),`
265			`.addr_out (addr2),`
266			`.addr_in (address_in),`
267			`.base_addr (bar2_in),`
268			`.mask_addr (am2_in),`
269			`.tran_addr (ta2_in),`
270			`.at_en (at_en_in[2])`
271			`) ;`
272
273			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
274			`.hit (hit[3]),`
275			`.addr_out (addr3),`
276			`.addr_in (address_in),`
277			`.base_addr (bar3_in),`
278			`.mask_addr (am3_in),`
279			`.tran_addr (ta3_in),`
280			`.at_en (at_en_in[3])`
281			`) ;`
282			`endif
283
284			`ifdef WB_IMAGE4
285			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
286			`.hit (hit[2]),`
287			`.addr_out (addr2),`
288			`.addr_in (address_in),`
289			`.base_addr (bar2_in),`
290			`.mask_addr (am2_in),`
291			`.tran_addr (ta2_in),`
292			`.at_en (at_en_in[2])`
293			`) ;`
294
295			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
296			`.hit (hit[3]),`
297			`.addr_out (addr3),`
298			`.addr_in (address_in),`
299			`.base_addr (bar3_in),`
300			`.mask_addr (am3_in),`
301			`.tran_addr (ta3_in),`
302			`.at_en (at_en_in[3])`
303			`) ;`
304
305			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
306			`.hit (hit[4]),`
307			`.addr_out (addr4),`
308			`.addr_in (address_in),`
309			`.base_addr (bar4_in),`
310			`.mask_addr (am4_in),`
311			`.tran_addr (ta4_in),`
312			`.at_en (at_en_in[4])`
313			`) ;`
314			`endif
315
316			`ifdef WB_IMAGE5
317			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec2(
318			`.hit (hit[2]),`
319			`.addr_out (addr2),`
320			`.addr_in (address_in),`
321			`.base_addr (bar2_in),`
322			`.mask_addr (am2_in),`
323			`.tran_addr (ta2_in),`
324			`.at_en (at_en_in[2])`
325			`) ;`
326
327			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec3(
328			`.hit (hit[3]),`
329			`.addr_out (addr3),`
330			`.addr_in (address_in),`
331			`.base_addr (bar3_in),`
332			`.mask_addr (am3_in),`
333			`.tran_addr (ta3_in),`
334			`.at_en (at_en_in[3])`
335			`) ;`
336
337			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec4(
338			`.hit (hit[4]),`
339			`.addr_out (addr4),`
340			`.addr_in (address_in),`
341			`.base_addr (bar4_in),`
342			`.mask_addr (am4_in),`
343			`.tran_addr (ta4_in),`
344			`.at_en (at_en_in[4])`
345			`) ;`
346
347			DECODER #(`WB_NUM_OF_DEC_ADDR_LINES) dec5(
348			`.hit (hit[5]),`
349			`.addr_out (addr5),`
350			`.addr_in (address_in),`
351			`.base_addr (bar5_in),`
352			`.mask_addr (am5_in),`
353			`.tran_addr (ta5_in),`
354			`.at_en (at_en_in[5])`
355			`) ;`
356			`endif
357			`endmodule`