URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_tpram.v] - Blame information for rev 60

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of pci bridge project                     ////
////  http://www.opencores.org/cvsweb.shtml/pci/                  ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Miha Dolenc, mihad@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/08/19 16:51:36  mihad
// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module WB_TPRAM
(
        // Generic synchronous two-port RAM interface
        clk_a,
    rst_a,
    ce_a,
    we_a,
    oe_a,
    addr_a,
    di_a,
    do_a,
        clk_b,
    rst_b,
    ce_b,
    we_b,
    oe_b,
    addr_b,
    di_b,
    do_b
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
//
// Internal wires and registers
//
 
`ifdef WB_VS_STP
    `define PCI_WB_RAM_SELECTED
    vs_hdtp_64x40 i_vs_hdtp_64x40
    (
        .RCK        (clk_b),
        .WCK        (clk_a),
        .RADR       (addr_b),
        .WADR       (addr_a),
        .DI         (di_a),
        .DOUT       (do_b),
        .REN        (1'b0),
        .WEN        (!we_a)
    );
 
    assign do_a = 0 ;
`endif
 
`ifdef WB_ARTISAN_SDP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Artisan Synchronous Double-Port RAM (ra2sh)
    //
    art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
    (
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
    );
 
`endif
 
`ifdef AVANT_ATP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Avant! Asynchronous Two-Port RAM
    //
    avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
    );
 
`endif
 
`ifdef VIRAGE_STP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Virage Synchronous 2-port R/W RAM
    //
    virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
    );
 
`endif
 
`ifdef WB_XILINX_DIST_RAM
    `define PCI_WB_RAM_SELECTED
 
    reg [(aw-1):0] out_address ;
    always@(posedge clk_b or posedge rst_b)
    begin
        if ( rst_b )
            out_address <= #1 0 ;
        else if (ce_b)
            out_address <= #1 addr_b ;
    end
 
    pci_ram_16x40d #(aw) wb_distributed_ram
    (
        .data_out       (do_b),
        .we             (we_a),
        .data_in        (di_a),
        .read_address   (out_address),
        .write_address  (addr_a),
        .wclk           (clk_a)
    );
    assign do_a = 0 ;
`endif
`ifdef WB_XILINX_RAMB4
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of FPGA memory:
    //
    // Virtex/Spartan2
    //
 
    //
    // Block 0
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
    );
 
    //
    // Block 1
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
    );
 
    //
    // Block 2
    //
    // block ram2 wires - non generic width of block rams
    wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
    wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
    wire [15:0] blk2_do_a ;
    wire [15:0] blk2_do_b ;
 
    assign do_a[39:32] = blk2_do_a[7:0] ;
    assign do_b[39:32] = blk2_do_b[7:0] ;
 
    RAMB4_S16_S16 ramb4_s16_s16_2(
            .CLKA(clk_a),
            .RSTA(rst_a),
            .ADDRA(addr_a),
            .DIA(blk2_di_a),
            .ENA(ce_a),
            .WEA(we_a),
            .DOA(blk2_do_a),
 
            .CLKB(clk_b),
            .RSTB(rst_b),
            .ADDRB(addr_b),
            .DIB(blk2_di_b),
            .ENB(ce_b),
            .WEB(we_b),
            .DOB(blk2_do_b)
    );
 
`endif
 
`ifdef PCI_WB_RAM_SELECTED
`else
    //
    // Generic two-port synchronous RAM model
    //
 
    //
    // Generic RAM's registers and wires
    //
    reg [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
    reg [dw-1:0] do_reg_a;               // RAM data output register
    reg [dw-1:0] do_reg_b;               // RAM data output register
 
    //
    // Data output drivers
    //
    assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
    assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
    //
    // RAM read and write
    //
    always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
    //
    // RAM read and write
    //
    always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
    if (dw !== 40)
    begin
        $display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
        $finish ;
    end
    `ifdef XILINX_RAMB4
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
    // currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
    `ifdef ARTISAN_SDP
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
end
// synopsys translate_on
 
endmodule

Line No.	Rev	Author	Line
1	18	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of pci bridge project ////`
6			`//// http://www.opencores.org/cvsweb.shtml/pci/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// - Miha Dolenc, mihad@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	60	mihad	`// Revision 1.2 2002/08/19 16:51:36 mihad`
66			`// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives`
67			`//`
68	49	mihad	`// Revision 1.1 2002/02/01 14:43:31 mihad`
69			`// * empty log message *`
70	18	mihad	`//`
71	49	mihad	`//`
72	18	mihad
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			`include "pci_constants.v"
77
78			`module WB_TPRAM`
79			`(`
80			`// Generic synchronous two-port RAM interface`
81			`clk_a,`
82			`rst_a,`
83			`ce_a,`
84			`we_a,`
85			`oe_a,`
86			`addr_a,`
87			`di_a,`
88			`do_a,`
89			`clk_b,`
90			`rst_b,`
91			`ce_b,`
92			`we_b,`
93			`oe_b,`
94			`addr_b,`
95			`di_b,`
96			`do_b`
97			`);`
98
99			`//`
100			`// Default address and data buses width`
101			`//`
102			`parameter aw = 8;`
103			`parameter dw = 40;`
104
105			`//`
106			`// Generic synchronous two-port RAM interface`
107			`//`
108			`input clk_a; // Clock`
109			`input rst_a; // Reset`
110			`input ce_a; // Chip enable input`
111			`input we_a; // Write enable input`
112			`input oe_a; // Output enable input`
113			`input [aw-1:0] addr_a; // address bus inputs`
114			`input [dw-1:0] di_a; // input data bus`
115			`output [dw-1:0] do_a; // output data bus`
116			`input clk_b; // Clock`
117			`input rst_b; // Reset`
118			`input ce_b; // Chip enable input`
119			`input we_b; // Write enable input`
120			`input oe_b; // Output enable input`
121			`input [aw-1:0] addr_b; // address bus inputs`
122			`input [dw-1:0] di_b; // input data bus`
123			`output [dw-1:0] do_b; // output data bus`
124
125			`//`
126			`// Internal wires and registers`
127			`//`
128
129	60	mihad	`ifdef WB_VS_STP
130			`define PCI_WB_RAM_SELECTED
131			`vs_hdtp_64x40 i_vs_hdtp_64x40`
132			`(`
133			`.RCK (clk_b),`
134			`.WCK (clk_a),`
135			`.RADR (addr_b),`
136			`.WADR (addr_a),`
137			`.DI (di_a),`
138			`.DOUT (do_b),`
139			`.REN (1'b0),`
140			`.WEN (!we_a)`
141			`);`
142
143			`assign do_a = 0 ;`
144			`endif
145	18	mihad
146			`ifdef WB_ARTISAN_SDP
147	49	mihad	`define PCI_WB_RAM_SELECTED
148	18	mihad	`//`
149			`// Instantiation of ASIC memory:`
150			`//`
151			`// Artisan Synchronous Double-Port RAM (ra2sh)`
152			`//`
153			`art_hsdp_256x40 /#(dw, 1<<aw, aw) / artisan_sdp`
154			`(`
155			`.qa(do_a),`
156			`.clka(clk_a),`
157			`.cena(~ce_a),`
158			`.wena(~we_a),`
159			`.aa(addr_a),`
160			`.da(di_a),`
161			`.oena(~oe_a),`
162			`.qb(do_b),`
163			`.clkb(clk_b),`
164			`.cenb(~ce_b),`
165			`.wenb(~we_b),`
166			`.ab(addr_b),`
167			`.db(di_b),`
168			`.oenb(~oe_b)`
169			`);`
170
171			`endif
172
173			`ifdef AVANT_ATP
174	49	mihad	`define PCI_WB_RAM_SELECTED
175	18	mihad	`//`
176			`// Instantiation of ASIC memory:`
177			`//`
178			`// Avant! Asynchronous Two-Port RAM`
179			`//`
180			`avant_atp avant_atp(`
181			`.web(~we),`
182			`.reb(),`
183			`.oeb(~oe),`
184			`.rcsb(),`
185			`.wcsb(),`
186			`.ra(addr),`
187			`.wa(addr),`
188			`.di(di),`
189			`.do(do)`
190			`);`
191
192			`endif
193
194			`ifdef VIRAGE_STP
195	49	mihad	`define PCI_WB_RAM_SELECTED
196	18	mihad	`//`
197			`// Instantiation of ASIC memory:`
198			`//`
199			`// Virage Synchronous 2-port R/W RAM`
200			`//`
201			`virage_stp virage_stp(`
202			`.QA(do_a),`
203			`.QB(do_b),`
204
205			`.ADRA(addr_a),`
206			`.DA(di_a),`
207			`.WEA(we_a),`
208			`.OEA(oe_a),`
209			`.MEA(ce_a),`
210			`.CLKA(clk_a),`
211
212			`.ADRB(adr_b),`
213			`.DB(di_b),`
214			`.WEB(we_b),`
215			`.OEB(oe_b),`
216			`.MEB(ce_b),`
217			`.CLKB(clk_b)`
218			`);`
219
220			`endif
221
222	49	mihad	`ifdef WB_XILINX_DIST_RAM
223			`define PCI_WB_RAM_SELECTED
224
225			`reg [(aw-1):0] out_address ;`
226			`always@(posedge clk_b or posedge rst_b)`
227			`begin`
228			`if ( rst_b )`
229			`out_address <= #1 0 ;`
230			`else if (ce_b)`
231			`out_address <= #1 addr_b ;`
232			`end`
233
234			`pci_ram_16x40d #(aw) wb_distributed_ram`
235			`(`
236			`.data_out (do_b),`
237			`.we (we_a),`
238			`.data_in (di_a),`
239			`.read_address (out_address),`
240			`.write_address (addr_a),`
241			`.wclk (clk_a)`
242			`);`
243			`assign do_a = 0 ;`
244			`endif
245	18	mihad	`ifdef WB_XILINX_RAMB4
246	49	mihad	`define PCI_WB_RAM_SELECTED
247	18	mihad	`//`
248			`// Instantiation of FPGA memory:`
249			`//`
250			`// Virtex/Spartan2`
251			`//`
252
253			`//`
254			`// Block 0`
255			`//`
256
257			`RAMB4_S16_S16 ramb4_s16_s16_0(`
258			`.CLKA(clk_a),`
259			`.RSTA(rst_a),`
260			`.ADDRA(addr_a),`
261			`.DIA(di_a[15:0]),`
262			`.ENA(ce_a),`
263			`.WEA(we_a),`
264			`.DOA(do_a[15:0]),`
265
266			`.CLKB(clk_b),`
267			`.RSTB(rst_b),`
268			`.ADDRB(addr_b),`
269			`.DIB(di_b[15:0]),`
270			`.ENB(ce_b),`
271			`.WEB(we_b),`
272			`.DOB(do_b[15:0])`
273			`);`
274
275			`//`
276			`// Block 1`
277			`//`
278
279			`RAMB4_S16_S16 ramb4_s16_s16_1(`
280			`.CLKA(clk_a),`
281			`.RSTA(rst_a),`
282			`.ADDRA(addr_a),`
283			`.DIA(di_a[31:16]),`
284			`.ENA(ce_a),`
285			`.WEA(we_a),`
286			`.DOA(do_a[31:16]),`
287
288			`.CLKB(clk_b),`
289			`.RSTB(rst_b),`
290			`.ADDRB(addr_b),`
291			`.DIB(di_b[31:16]),`
292			`.ENB(ce_b),`
293			`.WEB(we_b),`
294			`.DOB(do_b[31:16])`
295			`);`
296
297			`//`
298			`// Block 2`
299			`//`
300			`// block ram2 wires - non generic width of block rams`
301			`wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;`
302			`wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;`
303
304			`wire [15:0] blk2_do_a ;`
305			`wire [15:0] blk2_do_b ;`
306
307			`assign do_a[39:32] = blk2_do_a[7:0] ;`
308			`assign do_b[39:32] = blk2_do_b[7:0] ;`
309
310			`RAMB4_S16_S16 ramb4_s16_s16_2(`
311			`.CLKA(clk_a),`
312			`.RSTA(rst_a),`
313			`.ADDRA(addr_a),`
314			`.DIA(blk2_di_a),`
315			`.ENA(ce_a),`
316			`.WEA(we_a),`
317			`.DOA(blk2_do_a),`
318
319			`.CLKB(clk_b),`
320			`.RSTB(rst_b),`
321			`.ADDRB(addr_b),`
322			`.DIB(blk2_di_b),`
323			`.ENB(ce_b),`
324			`.WEB(we_b),`
325			`.DOB(blk2_do_b)`
326			`);`
327
328			`endif
329
330	49	mihad	`ifdef PCI_WB_RAM_SELECTED
331	18	mihad	`else
332			`//`
333			`// Generic two-port synchronous RAM model`
334			`//`
335
336			`//`
337			`// Generic RAM's registers and wires`
338			`//`
339			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
340			`reg [dw-1:0] do_reg_a; // RAM data output register`
341			`reg [dw-1:0] do_reg_b; // RAM data output register`
342
343			`//`
344			`// Data output drivers`
345			`//`
346			`assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};`
347			`assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};`
348
349			`//`
350			`// RAM read and write`
351			`//`
352			`always @(posedge clk_a)`
353			`if (ce_a && !we_a)`
354			`do_reg_a <= #1 mem[addr_a];`
355			`else if (ce_a && we_a)`
356			`mem[addr_a] <= #1 di_a;`
357
358			`//`
359			`// RAM read and write`
360			`//`
361			`always @(posedge clk_b)`
362			`if (ce_b && !we_b)`
363			`do_reg_b <= #1 mem[addr_b];`
364			`else if (ce_b && we_b)`
365			`mem[addr_b] <= #1 di_b;`
366			`endif
367
368			`// synopsys translate_off`
369			`initial`
370			`begin`
371			`if (dw !== 40)`
372			`begin`
373			`$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;`
374			`$finish ;`
375			`end`
376			`ifdef XILINX_RAMB4
377			`if (aw !== 8)`
378			`begin`
379			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
380			`$finish ;`
381			`end`
382			`endif
383			`// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models`
384			`ifdef ARTISAN_SDP
385			`if (aw !== 8)`
386			`begin`
387			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
388			`$finish ;`
389			`end`
390			`endif
391			`end`
392			`// synopsys translate_on`
393
394			`endmodule`

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wb_tpram.v] - Blame information for rev 60