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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of pci bridge project                     ////
////  http://www.opencores.org/cvsweb.shtml/pci/                  ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Miha Dolenc, mihad@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
//
// Revision 1.3  2002/09/30 17:22:27  mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.2  2002/08/19 16:51:36  mihad
// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module WB_TPRAM
(
        // Generic synchronous two-port RAM interface
        clk_a,
    rst_a,
    ce_a,
    we_a,
    oe_a,
    addr_a,
    di_a,
    do_a,
        clk_b,
    rst_b,
    ce_b,
    we_b,
    oe_b,
    addr_b,
    di_b,
    do_b
`ifdef PCI_BIST
    ,
    // debug chain signals
    trst,
    SO,
    SI,
    shift_DR,
    capture_DR,
    extest,
    tck
`endif
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
`ifdef PCI_BIST
// debug chain signals
input   trst ;
output  SO ;
input   SI ;
input   shift_DR ;
input   capture_DR ;
input   extest ;
input   tck ;
`endif
 
//
// Internal wires and registers
//
 
`ifdef WB_VS_STP
    `define PCI_WB_RAM_SELECTED
    `ifdef PCI_BIST
        vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
    `else
        vs_hdtp_64x40 i_vs_hdtp_64x40
    `endif
        (
            .RCK        (clk_b),
            .WCK        (clk_a),
            .RADR       (addr_b),
            .WADR       (addr_a),
            .DI         (di_a),
            .DOUT       (do_b),
            .REN        (1'b0),
            .WEN        (!we_a)
        `ifdef PCI_BIST
            ,
            // reset
            .trst        (trst),
 
            // debug chain signals
            .SO         (SO),
            .SI         (SI),
            .shift_DR   (shift_DR),
            .capture_DR (capture_DR),
            .extest     (extest),
            .tck        (tck)
        `endif
        );
 
    assign do_a = 0 ;
`endif
 
`ifdef WB_ARTISAN_SDP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Artisan Synchronous Double-Port RAM (ra2sh)
    //
    art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
    (
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
    );
 
`endif
 
`ifdef AVANT_ATP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Avant! Asynchronous Two-Port RAM
    //
    avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
    );
 
`endif
 
`ifdef VIRAGE_STP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Virage Synchronous 2-port R/W RAM
    //
    virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
    );
 
`endif
 
`ifdef WB_XILINX_DIST_RAM
    `define PCI_WB_RAM_SELECTED
 
    reg [(aw-1):0] out_address ;
    always@(posedge clk_b or posedge rst_b)
    begin
        if ( rst_b )
            out_address <= #1 0 ;
        else if (ce_b)
            out_address <= #1 addr_b ;
    end
 
    pci_ram_16x40d #(aw) wb_distributed_ram
    (
        .data_out       (do_b),
        .we             (we_a),
        .data_in        (di_a),
        .read_address   (out_address),
        .write_address  (addr_a),
        .wclk           (clk_a)
    );
    assign do_a = 0 ;
`endif
`ifdef WB_XILINX_RAMB4
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of FPGA memory:
    //
    // Virtex/Spartan2
    //
 
    //
    // Block 0
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
    );
 
    //
    // Block 1
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
    );
 
    //
    // Block 2
    //
    // block ram2 wires - non generic width of block rams
    wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
    wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
    wire [15:0] blk2_do_a ;
    wire [15:0] blk2_do_b ;
 
    assign do_a[39:32] = blk2_do_a[7:0] ;
    assign do_b[39:32] = blk2_do_b[7:0] ;
 
    RAMB4_S16_S16 ramb4_s16_s16_2(
            .CLKA(clk_a),
            .RSTA(rst_a),
            .ADDRA(addr_a),
            .DIA(blk2_di_a),
            .ENA(ce_a),
            .WEA(we_a),
            .DOA(blk2_do_a),
 
            .CLKB(clk_b),
            .RSTB(rst_b),
            .ADDRB(addr_b),
            .DIB(blk2_di_b),
            .ENB(ce_b),
            .WEB(we_b),
            .DOB(blk2_do_b)
    );
 
`endif
 
`ifdef PCI_WB_RAM_SELECTED
`else
    //
    // Generic two-port synchronous RAM model
    //
 
    //
    // Generic RAM's registers and wires
    //
    reg [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
    reg [dw-1:0] do_reg_a;               // RAM data output register
    reg [dw-1:0] do_reg_b;               // RAM data output register
 
    //
    // Data output drivers
    //
    assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
    assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
    //
    // RAM read and write
    //
    always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
    //
    // RAM read and write
    //
    always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
    if (dw !== 40)
    begin
        $display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
        $finish ;
    end
    `ifdef XILINX_RAMB4
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
    // currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
    `ifdef ARTISAN_SDP
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
end
// synopsys translate_on
 
endmodule

Line No.	Rev	Author	Line
1	18	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of pci bridge project ////`
6			`//// http://www.opencores.org/cvsweb.shtml/pci/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// - Miha Dolenc, mihad@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	63	mihad	`// Revision 1.4 2002/10/08 17:17:06 mihad`
66			`// Added BIST signals for RAMs.`
67			`//`
68	62	mihad	`// Revision 1.3 2002/09/30 17:22:27 mihad`
69			`// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!`
70			`//`
71	60	mihad	`// Revision 1.2 2002/08/19 16:51:36 mihad`
72			`// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives`
73			`//`
74	49	mihad	`// Revision 1.1 2002/02/01 14:43:31 mihad`
75			`// * empty log message *`
76	18	mihad	`//`
77	49	mihad	`//`
78	18	mihad
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "pci_constants.v"
83
84			`module WB_TPRAM`
85			`(`
86			`// Generic synchronous two-port RAM interface`
87			`clk_a,`
88			`rst_a,`
89			`ce_a,`
90			`we_a,`
91			`oe_a,`
92			`addr_a,`
93			`di_a,`
94			`do_a,`
95			`clk_b,`
96			`rst_b,`
97			`ce_b,`
98			`we_b,`
99			`oe_b,`
100			`addr_b,`
101			`di_b,`
102			`do_b`
103	62	mihad	`ifdef PCI_BIST
104			`,`
105			`// debug chain signals`
106	63	mihad	`trst,`
107	62	mihad	`SO,`
108			`SI,`
109			`shift_DR,`
110			`capture_DR,`
111			`extest,`
112			`tck`
113			`endif
114	18	mihad	`);`
115
116			`//`
117			`// Default address and data buses width`
118			`//`
119			`parameter aw = 8;`
120			`parameter dw = 40;`
121
122			`//`
123			`// Generic synchronous two-port RAM interface`
124			`//`
125			`input clk_a; // Clock`
126			`input rst_a; // Reset`
127			`input ce_a; // Chip enable input`
128			`input we_a; // Write enable input`
129			`input oe_a; // Output enable input`
130			`input [aw-1:0] addr_a; // address bus inputs`
131			`input [dw-1:0] di_a; // input data bus`
132			`output [dw-1:0] do_a; // output data bus`
133			`input clk_b; // Clock`
134			`input rst_b; // Reset`
135			`input ce_b; // Chip enable input`
136			`input we_b; // Write enable input`
137			`input oe_b; // Output enable input`
138			`input [aw-1:0] addr_b; // address bus inputs`
139			`input [dw-1:0] di_b; // input data bus`
140			`output [dw-1:0] do_b; // output data bus`
141
142	62	mihad	`ifdef PCI_BIST
143			`// debug chain signals`
144	63	mihad	`input trst ;`
145	62	mihad	`output SO ;`
146			`input SI ;`
147			`input shift_DR ;`
148			`input capture_DR ;`
149			`input extest ;`
150			`input tck ;`
151			`endif
152
153	18	mihad	`//`
154			`// Internal wires and registers`
155			`//`
156
157	60	mihad	`ifdef WB_VS_STP
158			`define PCI_WB_RAM_SELECTED
159	62	mihad	`ifdef PCI_BIST
160			`vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist`
161			`else
162			`vs_hdtp_64x40 i_vs_hdtp_64x40`
163			`endif
164			`(`
165			`.RCK (clk_b),`
166			`.WCK (clk_a),`
167			`.RADR (addr_b),`
168			`.WADR (addr_a),`
169			`.DI (di_a),`
170			`.DOUT (do_b),`
171			`.REN (1'b0),`
172			`.WEN (!we_a)`
173			`ifdef PCI_BIST
174			`,`
175			`// reset`
176	63	mihad	`.trst (trst),`
177	62	mihad
178			`// debug chain signals`
179			`.SO (SO),`
180			`.SI (SI),`
181			`.shift_DR (shift_DR),`
182			`.capture_DR (capture_DR),`
183			`.extest (extest),`
184			`.tck (tck)`
185			`endif
186			`);`
187	60	mihad
188			`assign do_a = 0 ;`
189			`endif
190	18	mihad
191			`ifdef WB_ARTISAN_SDP
192	49	mihad	`define PCI_WB_RAM_SELECTED
193	18	mihad	`//`
194			`// Instantiation of ASIC memory:`
195			`//`
196			`// Artisan Synchronous Double-Port RAM (ra2sh)`
197			`//`
198			`art_hsdp_256x40 /#(dw, 1<<aw, aw) / artisan_sdp`
199			`(`
200			`.qa(do_a),`
201			`.clka(clk_a),`
202			`.cena(~ce_a),`
203			`.wena(~we_a),`
204			`.aa(addr_a),`
205			`.da(di_a),`
206			`.oena(~oe_a),`
207			`.qb(do_b),`
208			`.clkb(clk_b),`
209			`.cenb(~ce_b),`
210			`.wenb(~we_b),`
211			`.ab(addr_b),`
212			`.db(di_b),`
213			`.oenb(~oe_b)`
214			`);`
215
216			`endif
217
218			`ifdef AVANT_ATP
219	49	mihad	`define PCI_WB_RAM_SELECTED
220	18	mihad	`//`
221			`// Instantiation of ASIC memory:`
222			`//`
223			`// Avant! Asynchronous Two-Port RAM`
224			`//`
225			`avant_atp avant_atp(`
226			`.web(~we),`
227			`.reb(),`
228			`.oeb(~oe),`
229			`.rcsb(),`
230			`.wcsb(),`
231			`.ra(addr),`
232			`.wa(addr),`
233			`.di(di),`
234			`.do(do)`
235			`);`
236
237			`endif
238
239			`ifdef VIRAGE_STP
240	49	mihad	`define PCI_WB_RAM_SELECTED
241	18	mihad	`//`
242			`// Instantiation of ASIC memory:`
243			`//`
244			`// Virage Synchronous 2-port R/W RAM`
245			`//`
246			`virage_stp virage_stp(`
247			`.QA(do_a),`
248			`.QB(do_b),`
249
250			`.ADRA(addr_a),`
251			`.DA(di_a),`
252			`.WEA(we_a),`
253			`.OEA(oe_a),`
254			`.MEA(ce_a),`
255			`.CLKA(clk_a),`
256
257			`.ADRB(adr_b),`
258			`.DB(di_b),`
259			`.WEB(we_b),`
260			`.OEB(oe_b),`
261			`.MEB(ce_b),`
262			`.CLKB(clk_b)`
263			`);`
264
265			`endif
266
267	49	mihad	`ifdef WB_XILINX_DIST_RAM
268			`define PCI_WB_RAM_SELECTED
269
270			`reg [(aw-1):0] out_address ;`
271			`always@(posedge clk_b or posedge rst_b)`
272			`begin`
273			`if ( rst_b )`
274			`out_address <= #1 0 ;`
275			`else if (ce_b)`
276			`out_address <= #1 addr_b ;`
277			`end`
278
279			`pci_ram_16x40d #(aw) wb_distributed_ram`
280			`(`
281			`.data_out (do_b),`
282			`.we (we_a),`
283			`.data_in (di_a),`
284			`.read_address (out_address),`
285			`.write_address (addr_a),`
286			`.wclk (clk_a)`
287			`);`
288			`assign do_a = 0 ;`
289			`endif
290	18	mihad	`ifdef WB_XILINX_RAMB4
291	49	mihad	`define PCI_WB_RAM_SELECTED
292	18	mihad	`//`
293			`// Instantiation of FPGA memory:`
294			`//`
295			`// Virtex/Spartan2`
296			`//`
297
298			`//`
299			`// Block 0`
300			`//`
301
302			`RAMB4_S16_S16 ramb4_s16_s16_0(`
303			`.CLKA(clk_a),`
304			`.RSTA(rst_a),`
305			`.ADDRA(addr_a),`
306			`.DIA(di_a[15:0]),`
307			`.ENA(ce_a),`
308			`.WEA(we_a),`
309			`.DOA(do_a[15:0]),`
310
311			`.CLKB(clk_b),`
312			`.RSTB(rst_b),`
313			`.ADDRB(addr_b),`
314			`.DIB(di_b[15:0]),`
315			`.ENB(ce_b),`
316			`.WEB(we_b),`
317			`.DOB(do_b[15:0])`
318			`);`
319
320			`//`
321			`// Block 1`
322			`//`
323
324			`RAMB4_S16_S16 ramb4_s16_s16_1(`
325			`.CLKA(clk_a),`
326			`.RSTA(rst_a),`
327			`.ADDRA(addr_a),`
328			`.DIA(di_a[31:16]),`
329			`.ENA(ce_a),`
330			`.WEA(we_a),`
331			`.DOA(do_a[31:16]),`
332
333			`.CLKB(clk_b),`
334			`.RSTB(rst_b),`
335			`.ADDRB(addr_b),`
336			`.DIB(di_b[31:16]),`
337			`.ENB(ce_b),`
338			`.WEB(we_b),`
339			`.DOB(do_b[31:16])`
340			`);`
341
342			`//`
343			`// Block 2`
344			`//`
345			`// block ram2 wires - non generic width of block rams`
346			`wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;`
347			`wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;`
348
349			`wire [15:0] blk2_do_a ;`
350			`wire [15:0] blk2_do_b ;`
351
352			`assign do_a[39:32] = blk2_do_a[7:0] ;`
353			`assign do_b[39:32] = blk2_do_b[7:0] ;`
354
355			`RAMB4_S16_S16 ramb4_s16_s16_2(`
356			`.CLKA(clk_a),`
357			`.RSTA(rst_a),`
358			`.ADDRA(addr_a),`
359			`.DIA(blk2_di_a),`
360			`.ENA(ce_a),`
361			`.WEA(we_a),`
362			`.DOA(blk2_do_a),`
363
364			`.CLKB(clk_b),`
365			`.RSTB(rst_b),`
366			`.ADDRB(addr_b),`
367			`.DIB(blk2_di_b),`
368			`.ENB(ce_b),`
369			`.WEB(we_b),`
370			`.DOB(blk2_do_b)`
371			`);`
372
373			`endif
374
375	49	mihad	`ifdef PCI_WB_RAM_SELECTED
376	18	mihad	`else
377			`//`
378			`// Generic two-port synchronous RAM model`
379			`//`
380
381			`//`
382			`// Generic RAM's registers and wires`
383			`//`
384			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
385			`reg [dw-1:0] do_reg_a; // RAM data output register`
386			`reg [dw-1:0] do_reg_b; // RAM data output register`
387
388			`//`
389			`// Data output drivers`
390			`//`
391			`assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};`
392			`assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};`
393
394			`//`
395			`// RAM read and write`
396			`//`
397			`always @(posedge clk_a)`
398			`if (ce_a && !we_a)`
399			`do_reg_a <= #1 mem[addr_a];`
400			`else if (ce_a && we_a)`
401			`mem[addr_a] <= #1 di_a;`
402
403			`//`
404			`// RAM read and write`
405			`//`
406			`always @(posedge clk_b)`
407			`if (ce_b && !we_b)`
408			`do_reg_b <= #1 mem[addr_b];`
409			`else if (ce_b && we_b)`
410			`mem[addr_b] <= #1 di_b;`
411			`endif
412
413			`// synopsys translate_off`
414			`initial`
415			`begin`
416			`if (dw !== 40)`
417			`begin`
418			`$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;`
419			`$finish ;`
420			`end`
421			`ifdef XILINX_RAMB4
422			`if (aw !== 8)`
423			`begin`
424			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
425			`$finish ;`
426			`end`
427			`endif
428			`// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models`
429			`ifdef ARTISAN_SDP
430			`if (aw !== 8)`
431			`begin`
432			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
433			`$finish ;`
434			`end`
435			`endif
436			`end`
437			`// synopsys translate_on`
438
439			`endmodule`

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