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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wbr_fifo_control.v"                              ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
/* FIFO_CONTROL module provides read/write address and status generation for
   FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
`include "constants.v"
`ifdef FPGA
    // fifo design in FPGA will be synchronous
    `ifdef SYNCHRONOUS
    `else
        `define SYNCHRONOUS
    `endif
`endif
 
module WBR_FIFO_CONTROL
(
    rclock_in,
    wclock_in,
    renable_in,
    wenable_in,
    reset_in,
    flush_in,
    empty_out,
    waddr_out,
    raddr_out,
    rallow_out,
    wallow_out
) ;
 
parameter ADDR_LENGTH = 7 ;
 
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input  rclock_in, wclock_in;
 
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
//                 write address changes on rising edge of wclock_in when writes are allowed
input  renable_in, wenable_in;
 
// reset input
input  reset_in;
 
// flush input
input flush_in ;
 
// empty status output
output empty_out;
 
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
 
// read and write allow outputs
output rallow_out, wallow_out ;
 
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
 
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
assign waddr_out = waddr ;
 
// grey code registers
// grey code pipeline for write address
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
 
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next  = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
 
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
 
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next  = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
 
// FF for registered empty flag
reg empty ;
 
// write allow wire
wire wallow = wenable_in ;
 
// write allow output assignment
assign wallow_out = wallow ;
 
// read allow wire
wire rallow ;
 
// clear generation for FFs and registers
wire clear = reset_in || flush_in ;
 
`ifdef SYNCHRONOUS
 
    reg wclock_nempty_detect ;
    always@(posedge reset_in or posedge wclock_in)
    begin
        if (reset_in)
            wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
        else
            wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
    end
 
    // special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
    reg stretched_empty ;
    always@(posedge rclock_in or posedge clear)
    begin
        if(clear)
            stretched_empty <= #`FF_DELAY 1'b1 ;
        else
            stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
    end
 
    // empty output is actual empty + 1 read clock cycle ( stretched empty )
    assign empty_out = empty  || stretched_empty ;
 
    //rallow generation    
    assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
 
    // rallow output assignment
    assign rallow_out = renable_in ;
 
    // at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
    // when FIFO is empty, this register provides actual read address, so first location can be read
    reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
 
    // address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
    // done for zero wait state burst
    assign raddr_out = rallow ? raddr_plus_one : raddr ;
 
    // enable for this register
    wire raddr_plus_one_en = rallow ;
    always@(posedge rclock_in or posedge clear)
    begin
        if (clear)
        begin
            raddr_plus_one[(ADDR_LENGTH - 1):1] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0}} ;
            raddr_plus_one[0] <= #`FF_DELAY 1'b1 ;
        end
        else if (raddr_plus_one_en)
            raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
    end
 
    // raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
    always@(posedge rclock_in or posedge clear)
    begin
            if (clear)
            // initial value is 000......00
                    raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
            else if (rallow)
                raddr <= #`FF_DELAY raddr_plus_one ;
    end
 
`else
    // asynchronous RAM storage for FIFOs - somewhat simpler control logic
    //rallow generation    
    assign rallow = renable_in && ~empty ;
 
    assign rallow_out = rallow ;
 
    // read address counter - normal counter, nothing to it
    // for asynchronous implementation, there is no need for pointing to next address.
    // On clock edge that read is performed, read address will change and on the next clock edge
    // asynchronous memory will provide next data
    always@(posedge rclock_in or posedge clear)
    begin
            if (clear)
            // initial value is 000......00
                    raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
            else if (rallow)
                    raddr <= #`FF_DELAY raddr + 1'b1 ;
    end
 
    assign empty_out = empty ;
    assign raddr_out = raddr ;
`endif
 
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 3 Grey addresses:
    - rgrey_addr is Grey Code of current read address
    - rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
 
// grey code register for read address - represents current Read Address
always@(posedge rclock_in or posedge clear)
begin
        if (clear)
    begin
        // initial value is 100.......01
                rgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
        rgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
        rgrey_addr[0] <= #`FF_DELAY 1'b1 ;
    end
        else
                if (rallow)
                        rgrey_addr <= #`FF_DELAY rgrey_next ;
end
 
// grey code register for next read address - represents Grey Code of next read address    
always@(posedge rclock_in or posedge clear)
begin
        if (clear)
    begin
        // initial value is 100......00
                rgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
        rgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
    end
        else
                if (rallow)
            rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
 
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and two Grey Code Registers:
    - wgrey_addr represents current Grey Coded write address
    - wgrey_next represents Grey Coded next write address
----------------------------------------------------------------------------------------------*/
// grey code register for write address
always@(posedge wclock_in or posedge clear)
begin
        if (clear)
    begin
        // initial value is 100.....001
        wgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
        wgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
        wgrey_addr[0] <= #`FF_DELAY 1'b1 ;
    end
        else
                if (wallow)
                        wgrey_addr <= #`FF_DELAY wgrey_next ;
end
 
// grey code register for next write address
always@(posedge wclock_in or posedge clear)
begin
        if (clear)
    begin
        // initial value is 100......00
                wgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
        wgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
    end
        else
        if (wallow)
            wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
end
 
// write address counter - nothing special
always@(posedge wclock_in or posedge clear)
begin
        if (clear)
        // initial value 00.........00
                waddr <= #`FF_DELAY { (ADDR_LENGTH){1'b0} } ;
        else
                if (wallow)
                        waddr <= #`FF_DELAY waddr + 1'b1 ;
end
 
 
/*------------------------------------------------------------------------------------------------------------------------------
Registered empty control:
registered empty is set on rising edge of rclock_in,
when only one location is used and read in/from fifo. It's kept high until something is written to FIFO, which is registered on
the next read clock.
--------------------------------------------------------------------------------------------------------------------------------*/
// combinatorial input for registered emty FlipFlop
wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
 
always@(posedge rclock_in or posedge clear)
begin
    if (clear)
        empty <= #`FF_DELAY 1'b1 ;
        else
        empty <= #`FF_DELAY reg_empty ;
end
 
endmodule

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbr_fifo_control.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wbr_fifo_control.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`//`
46
47			`/* FIFO_CONTROL module provides read/write address and status generation for`
48			`FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */`
49			`include "constants.v"
50			`ifdef FPGA
51			`// fifo design in FPGA will be synchronous`
52			`ifdef SYNCHRONOUS
53			`else
54			`define SYNCHRONOUS
55			`endif
56			`endif
57
58			`module WBR_FIFO_CONTROL`
59			`(`
60			`rclock_in,`
61			`wclock_in,`
62			`renable_in,`
63			`wenable_in,`
64			`reset_in,`
65			`flush_in,`
66			`empty_out,`
67			`waddr_out,`
68			`raddr_out,`
69			`rallow_out,`
70			`wallow_out`
71			`) ;`
72
73			`parameter ADDR_LENGTH = 7 ;`
74
75			`// independent clock inputs - rclock_in = read clock, wclock_in = write clock`
76			`input rclock_in, wclock_in;`
77
78			`// enable inputs - read address changes on rising edge of rclock_in when reads are allowed`
79			`// write address changes on rising edge of wclock_in when writes are allowed`
80			`input renable_in, wenable_in;`
81
82			`// reset input`
83			`input reset_in;`
84
85			`// flush input`
86			`input flush_in ;`
87
88			`// empty status output`
89			`output empty_out;`
90
91			`// read and write addresses outputs`
92			`output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;`
93
94			`// read and write allow outputs`
95			`output rallow_out, wallow_out ;`
96
97			`// read address register`
98			`reg [(ADDR_LENGTH - 1):0] raddr ;`
99
100			`// write address register`
101			`reg [(ADDR_LENGTH - 1):0] waddr;`
102			`assign waddr_out = waddr ;`
103
104			`// grey code registers`
105			`// grey code pipeline for write address`
106			`reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current`
107			`reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next`
108
109			`// next write gray address calculation - bitwise xor between address and shifted address`
110			`wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;`
111
112			`// grey code pipeline for read address`
113			`reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current`
114			`reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next`
115
116			`// next read gray address calculation - bitwise xor between address and shifted address`
117			`wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;`
118
119			`// FF for registered empty flag`
120			`reg empty ;`
121
122			`// write allow wire`
123			`wire wallow = wenable_in ;`
124
125			`// write allow output assignment`
126			`assign wallow_out = wallow ;`
127
128			`// read allow wire`
129			`wire rallow ;`
130
131			`// clear generation for FFs and registers`
132			`wire clear = reset_in \|\| flush_in ;`
133
134			`ifdef SYNCHRONOUS
135
136			`reg wclock_nempty_detect ;`
137			`always@(posedge reset_in or posedge wclock_in)`
138			`begin`
139			`if (reset_in)`
140			wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
141			`else`
142			wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
143			`end`
144
145			`// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write`
146			`reg stretched_empty ;`
147			`always@(posedge rclock_in or posedge clear)`
148			`begin`
149			`if(clear)`
150			stretched_empty <= #`FF_DELAY 1'b1 ;
151			`else`
152			stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
153			`end`
154
155			`// empty output is actual empty + 1 read clock cycle ( stretched empty )`
156			`assign empty_out = empty \|\| stretched_empty ;`
157
158			`//rallow generation`
159			`assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty`
160
161			`// rallow output assignment`
162			`assign rallow_out = renable_in ;`
163
164			`// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary`
165			`// when FIFO is empty, this register provides actual read address, so first location can be read`
166			`reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;`
167
168			`// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out`
169			`// done for zero wait state burst`
170			`assign raddr_out = rallow ? raddr_plus_one : raddr ;`
171
172			`// enable for this register`
173			`wire raddr_plus_one_en = rallow ;`
174			`always@(posedge rclock_in or posedge clear)`
175			`begin`
176			`if (clear)`
177			`begin`
178			raddr_plus_one[(ADDR_LENGTH - 1):1] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0}} ;
179			raddr_plus_one[0] <= #`FF_DELAY 1'b1 ;
180			`end`
181			`else if (raddr_plus_one_en)`
182			raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
183			`end`
184
185			`// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high`
186			`always@(posedge rclock_in or posedge clear)`
187			`begin`
188			`if (clear)`
189			`// initial value is 000......00`
190			raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
191			`else if (rallow)`
192			raddr <= #`FF_DELAY raddr_plus_one ;
193			`end`
194
195			`else
196			`// asynchronous RAM storage for FIFOs - somewhat simpler control logic`
197			`//rallow generation`
198			`assign rallow = renable_in && ~empty ;`
199
200			`assign rallow_out = rallow ;`
201
202			`// read address counter - normal counter, nothing to it`
203			`// for asynchronous implementation, there is no need for pointing to next address.`
204			`// On clock edge that read is performed, read address will change and on the next clock edge`
205			`// asynchronous memory will provide next data`
206			`always@(posedge rclock_in or posedge clear)`
207			`begin`
208			`if (clear)`
209			`// initial value is 000......00`
210			raddr <= #`FF_DELAY { ADDR_LENGTH{1'b0}} ;
211			`else if (rallow)`
212			raddr <= #`FF_DELAY raddr + 1'b1 ;
213			`end`
214
215			`assign empty_out = empty ;`
216			`assign raddr_out = raddr ;`
217			`endif
218
219			`/*-----------------------------------------------------------------------------------------------`
220			`Read address control consists of Read address counter and Grey Address pipeline`
221			`There are 3 Grey addresses:`
222			`- rgrey_addr is Grey Code of current read address`
223			`- rgrey_next is Grey Code of next read address`
224			`--------------------------------------------------------------------------------------------------*/`
225
226			`// grey code register for read address - represents current Read Address`
227			`always@(posedge rclock_in or posedge clear)`
228			`begin`
229			`if (clear)`
230			`begin`
231			`// initial value is 100.......01`
232			rgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
233			rgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
234			rgrey_addr[0] <= #`FF_DELAY 1'b1 ;
235			`end`
236			`else`
237			`if (rallow)`
238			rgrey_addr <= #`FF_DELAY rgrey_next ;
239			`end`
240
241			`// grey code register for next read address - represents Grey Code of next read address`
242			`always@(posedge rclock_in or posedge clear)`
243			`begin`
244			`if (clear)`
245			`begin`
246			`// initial value is 100......00`
247			rgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
248			rgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
249			`end`
250			`else`
251			`if (rallow)`
252			rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
253			`end`
254
255			`/*--------------------------------------------------------------------------------------------`
256			`Write address control consists of write address counter and two Grey Code Registers:`
257			`- wgrey_addr represents current Grey Coded write address`
258			`- wgrey_next represents Grey Coded next write address`
259			`----------------------------------------------------------------------------------------------*/`
260			`// grey code register for write address`
261			`always@(posedge wclock_in or posedge clear)`
262			`begin`
263			`if (clear)`
264			`begin`
265			`// initial value is 100.....001`
266			wgrey_addr[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
267			wgrey_addr[(ADDR_LENGTH - 2):1] <= #`FF_DELAY { (ADDR_LENGTH - 2){1'b0} } ;
268			wgrey_addr[0] <= #`FF_DELAY 1'b1 ;
269			`end`
270			`else`
271			`if (wallow)`
272			wgrey_addr <= #`FF_DELAY wgrey_next ;
273			`end`
274
275			`// grey code register for next write address`
276			`always@(posedge wclock_in or posedge clear)`
277			`begin`
278			`if (clear)`
279			`begin`
280			`// initial value is 100......00`
281			wgrey_next[(ADDR_LENGTH - 1)] <= #`FF_DELAY 1'b1 ;
282			wgrey_next[(ADDR_LENGTH - 2):0] <= #`FF_DELAY { (ADDR_LENGTH - 1){1'b0} } ;
283			`end`
284			`else`
285			`if (wallow)`
286			wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
287			`end`
288
289			`// write address counter - nothing special`
290			`always@(posedge wclock_in or posedge clear)`
291			`begin`
292			`if (clear)`
293			`// initial value 00.........00`
294			waddr <= #`FF_DELAY { (ADDR_LENGTH){1'b0} } ;
295			`else`
296			`if (wallow)`
297			waddr <= #`FF_DELAY waddr + 1'b1 ;
298			`end`
299
300
301			`/*------------------------------------------------------------------------------------------------------------------------------`
302			`Registered empty control:`
303			`registered empty is set on rising edge of rclock_in,`
304			`when only one location is used and read in/from fifo. It's kept high until something is written to FIFO, which is registered on`
305			`the next read clock.`
306			`--------------------------------------------------------------------------------------------------------------------------------*/`
307			`// combinatorial input for registered emty FlipFlop`
308			`wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) \|\| (rgrey_addr == wgrey_addr) ;`
309
310			`always@(posedge rclock_in or posedge clear)`
311			`begin`
312			`if (clear)`
313			empty <= #`FF_DELAY 1'b1 ;
314			`else`
315			empty <= #`FF_DELAY reg_empty ;
316			`end`
317
318			`endmodule`