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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wbr_fifo_control.v"                              ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/02/01 15:25:13  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
//
//
 
/* FIFO_CONTROL module provides read/write address and status generation for
   FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
`include "pci_constants.v"
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module WBR_FIFO_CONTROL
(
    rclock_in,
    wclock_in,
    renable_in,
    wenable_in,
    reset_in,
    flush_in,
    empty_out,
    waddr_out,
    raddr_out,
    rallow_out,
    wallow_out
) ;
 
parameter ADDR_LENGTH = 7 ;
 
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input  rclock_in, wclock_in;
 
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
//                 write address changes on rising edge of wclock_in when writes are allowed
input  renable_in, wenable_in;
 
// reset input
input  reset_in;
 
// flush input
input flush_in ;
 
// empty status output
output empty_out;
 
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
 
// read and write allow outputs
output rallow_out, wallow_out ;
 
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
 
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
assign waddr_out = waddr ;
 
// grey code registers
// grey code pipeline for write address
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
 
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next  = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
 
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
 
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next  = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
 
// FF for registered empty flag
reg empty ;
 
// write allow wire
wire wallow = wenable_in ;
 
// write allow output assignment
assign wallow_out = wallow ;
 
// read allow wire
wire rallow ;
 
// clear generation for FFs and registers
wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
 
reg wclock_nempty_detect ;
always@(posedge reset_in or posedge wclock_in)
begin
    if (reset_in)
        wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
    else
        wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
end
 
// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
reg stretched_empty ;
always@(posedge rclock_in or posedge clear)
begin
    if(clear)
        stretched_empty <= #`FF_DELAY 1'b1 ;
    else
        stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
end
 
// empty output is actual empty + 1 read clock cycle ( stretched empty )
assign empty_out = empty  || stretched_empty ;
 
//rallow generation
assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
 
// rallow output assignment
assign rallow_out = renable_in ;
 
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
 
// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
// done for zero wait state burst
assign raddr_out = rallow ? raddr_plus_one : raddr ;
 
always@(posedge rclock_in or posedge clear)
begin
    if (clear)
        // initial value is 3
        raddr_plus_one <= #`FF_DELAY 3 ;
    else if (flush_in)
        raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ; // when read fifo is flushed, values from write side are copied to read side
    else if (rallow)
        raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
end
 
// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
always@(posedge rclock_in or posedge clear)
begin
    if (clear)
        // initial value is 2
        raddr <= #`FF_DELAY 2 ;
    else if (flush_in)
        raddr <= #`FF_DELAY waddr ;                 // when flushed, copy value from write side
    else if (rallow)
        raddr <= #`FF_DELAY raddr_plus_one ;
end
 
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 3 Grey addresses:
    - rgrey_addr is Grey Code of current read address
    - rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
 
// grey code register for read address - represents current Read Address
always@(posedge rclock_in or posedge clear)
begin
    if (clear)
        // initial value is 0
        rgrey_addr <= #`FF_DELAY 0 ;
    else if (flush_in)
        rgrey_addr <= #`FF_DELAY wgrey_addr ;   // when flushed, copy value from write side
    else if (rallow)
        rgrey_addr <= #`FF_DELAY rgrey_next ;
end
 
// grey code register for next read address - represents Grey Code of next read address
always@(posedge rclock_in or posedge clear)
begin
    if (clear)
        // initial value is 1
        rgrey_next <= #`FF_DELAY 1 ;
    else if (flush_in)
        rgrey_next <= #`FF_DELAY wgrey_next ;
    else if (rallow)
        rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
 
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and two Grey Code Registers:
    - wgrey_addr represents current Grey Coded write address
    - wgrey_next represents Grey Coded next write address
----------------------------------------------------------------------------------------------*/
// grey code register for write address
always@(posedge wclock_in or posedge clear)
begin
    if (clear)
    begin
        // initial value is 0
        wgrey_addr <= #`FF_DELAY 0 ;
    end
    else
    if (wallow)
        wgrey_addr <= #`FF_DELAY wgrey_next ;
end
 
// grey code register for next write address
always@(posedge wclock_in or posedge clear)
begin
    if (clear)
    begin
        // initial value is 1
        wgrey_next <= #`FF_DELAY 1 ;
    end
    else
    if (wallow)
        wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
end
 
// write address counter - nothing special except initial value
always@(posedge wclock_in or posedge clear)
begin
    if (clear)
        // initial value is 2
        waddr <= #`FF_DELAY 2 ;
    else
    if (wallow)
        waddr <= #`FF_DELAY waddr + 1'b1 ;
end
 
 
/*------------------------------------------------------------------------------------------------------------------------------
Registered empty control:
registered empty is set on rising edge of rclock_in,
when only one location is used and read in/from fifo. It's kept high until something is written to FIFO, which is registered on
the next read clock.
--------------------------------------------------------------------------------------------------------------------------------*/
// combinatorial input for registered emty FlipFlop
wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
 
always@(posedge rclock_in or posedge clear)
begin
    if (clear)
        empty <= #`FF_DELAY 1'b1 ;
    else if (flush_in)
        empty <= #1 1'b1 ;  // when flushed, set empty to active
        else
        empty <= #`FF_DELAY reg_empty ;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wbr_fifo_control.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	58	mihad	`// Revision 1.3 2002/02/01 15:25:13 mihad`
46			`// Repaired a few bugs, updated specification, added test bench files and design document`
47			`//`
48	21	mihad	`// Revision 1.2 2001/10/05 08:14:30 mihad`
49			`// Updated all files with inclusion of timescale file for simulation purposes.`
50			`//`
51	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:47 mihad`
52			`// New project directory structure`
53	2	mihad	`//`
54	6	mihad	`//`
55	2	mihad
56			`/* FIFO_CONTROL module provides read/write address and status generation for`
57			`FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */`
58	21	mihad	`include "pci_constants.v"
59			`// synopsys translate_off`
60	6	mihad	`include "timescale.v"
61	21	mihad	`// synopsys translate_on`
62	2	mihad
63			`module WBR_FIFO_CONTROL`
64			`(`
65			`rclock_in,`
66	21	mihad	`wclock_in,`
67			`renable_in,`
68			`wenable_in,`
69			`reset_in,`
70			`flush_in,`
71			`empty_out,`
72			`waddr_out,`
73			`raddr_out,`
74			`rallow_out,`
75	2	mihad	`wallow_out`
76			`) ;`
77
78			`parameter ADDR_LENGTH = 7 ;`
79
80			`// independent clock inputs - rclock_in = read clock, wclock_in = write clock`
81			`input rclock_in, wclock_in;`
82
83			`// enable inputs - read address changes on rising edge of rclock_in when reads are allowed`
84			`// write address changes on rising edge of wclock_in when writes are allowed`
85			`input renable_in, wenable_in;`
86
87			`// reset input`
88			`input reset_in;`
89
90			`// flush input`
91			`input flush_in ;`
92
93			`// empty status output`
94			`output empty_out;`
95
96			`// read and write addresses outputs`
97			`output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;`
98
99			`// read and write allow outputs`
100			`output rallow_out, wallow_out ;`
101
102			`// read address register`
103			`reg [(ADDR_LENGTH - 1):0] raddr ;`
104
105			`// write address register`
106			`reg [(ADDR_LENGTH - 1):0] waddr;`
107			`assign waddr_out = waddr ;`
108
109			`// grey code registers`
110			`// grey code pipeline for write address`
111			`reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current`
112			`reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next`
113
114			`// next write gray address calculation - bitwise xor between address and shifted address`
115			`wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;`
116
117			`// grey code pipeline for read address`
118			`reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current`
119			`reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next`
120
121			`// next read gray address calculation - bitwise xor between address and shifted address`
122			`wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;`
123
124			`// FF for registered empty flag`
125			`reg empty ;`
126
127			`// write allow wire`
128			`wire wallow = wenable_in ;`
129
130			`// write allow output assignment`
131			`assign wallow_out = wallow ;`
132
133			`// read allow wire`
134			`wire rallow ;`
135
136			`// clear generation for FFs and registers`
137	58	mihad	`wire clear = reset_in /\|\| flush_in/ ; // flush changed to synchronous operation`
138	2	mihad
139	21	mihad	`reg wclock_nempty_detect ;`
140			`always@(posedge reset_in or posedge wclock_in)`
141			`begin`
142			`if (reset_in)`
143			wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
144			`else`
145			wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
146			`end`
147	2	mihad
148	21	mihad	`// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write`
149			`reg stretched_empty ;`
150			`always@(posedge rclock_in or posedge clear)`
151			`begin`
152			`if(clear)`
153			stretched_empty <= #`FF_DELAY 1'b1 ;
154			`else`
155			stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
156			`end`
157	2	mihad
158	21	mihad	`// empty output is actual empty + 1 read clock cycle ( stretched empty )`
159			`assign empty_out = empty \|\| stretched_empty ;`
160	2	mihad
161	21	mihad	`//rallow generation`
162			`assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty`
163	2	mihad
164	21	mihad	`// rallow output assignment`
165			`assign rallow_out = renable_in ;`
166	2	mihad
167	21	mihad	`// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary`
168			`// when FIFO is empty, this register provides actual read address, so first location can be read`
169			`reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;`
170	2	mihad
171	21	mihad	`// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out`
172			`// done for zero wait state burst`
173			`assign raddr_out = rallow ? raddr_plus_one : raddr ;`
174	2	mihad
175	21	mihad	`always@(posedge rclock_in or posedge clear)`
176			`begin`
177			`if (clear)`
178			`// initial value is 3`
179			raddr_plus_one <= #`FF_DELAY 3 ;
180	58	mihad	`else if (flush_in)`
181			raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ; // when read fifo is flushed, values from write side are copied to read side
182	21	mihad	`else if (rallow)`
183			raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
184			`end`
185	2	mihad
186	21	mihad	`// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high`
187			`always@(posedge rclock_in or posedge clear)`
188			`begin`
189			`if (clear)`
190			`// initial value is 2`
191			raddr <= #`FF_DELAY 2 ;
192	58	mihad	`else if (flush_in)`
193			raddr <= #`FF_DELAY waddr ; // when flushed, copy value from write side
194	21	mihad	`else if (rallow)`
195			raddr <= #`FF_DELAY raddr_plus_one ;
196			`end`
197	2	mihad
198			`/*-----------------------------------------------------------------------------------------------`
199			`Read address control consists of Read address counter and Grey Address pipeline`
200	21	mihad	`There are 3 Grey addresses:`
201	2	mihad	`- rgrey_addr is Grey Code of current read address`
202			`- rgrey_next is Grey Code of next read address`
203			`--------------------------------------------------------------------------------------------------*/`
204
205			`// grey code register for read address - represents current Read Address`
206			`always@(posedge rclock_in or posedge clear)`
207			`begin`
208	21	mihad	`if (clear)`
209			`// initial value is 0`
210			rgrey_addr <= #`FF_DELAY 0 ;
211	58	mihad	`else if (flush_in)`
212			rgrey_addr <= #`FF_DELAY wgrey_addr ; // when flushed, copy value from write side
213			`else if (rallow)`
214	21	mihad	rgrey_addr <= #`FF_DELAY rgrey_next ;
215	2	mihad	`end`
216
217	21	mihad	`// grey code register for next read address - represents Grey Code of next read address`
218	2	mihad	`always@(posedge rclock_in or posedge clear)`
219			`begin`
220	21	mihad	`if (clear)`
221			`// initial value is 1`
222			rgrey_next <= #`FF_DELAY 1 ;
223	58	mihad	`else if (flush_in)`
224			rgrey_next <= #`FF_DELAY wgrey_next ;
225			`else if (rallow)`
226	21	mihad	rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
227	2	mihad	`end`
228
229			`/*--------------------------------------------------------------------------------------------`
230			`Write address control consists of write address counter and two Grey Code Registers:`
231			`- wgrey_addr represents current Grey Coded write address`
232			`- wgrey_next represents Grey Coded next write address`
233			`----------------------------------------------------------------------------------------------*/`
234			`// grey code register for write address`
235			`always@(posedge wclock_in or posedge clear)`
236			`begin`
237	21	mihad	`if (clear)`
238	2	mihad	`begin`
239	21	mihad	`// initial value is 0`
240			wgrey_addr <= #`FF_DELAY 0 ;
241	2	mihad	`end`
242	21	mihad	`else`
243			`if (wallow)`
244			wgrey_addr <= #`FF_DELAY wgrey_next ;
245	2	mihad	`end`
246
247			`// grey code register for next write address`
248			`always@(posedge wclock_in or posedge clear)`
249			`begin`
250	21	mihad	`if (clear)`
251	2	mihad	`begin`
252	21	mihad	`// initial value is 1`
253			wgrey_next <= #`FF_DELAY 1 ;
254	2	mihad	`end`
255	21	mihad	`else`
256			`if (wallow)`
257			wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
258	2	mihad	`end`
259
260	21	mihad	`// write address counter - nothing special except initial value`
261	2	mihad	`always@(posedge wclock_in or posedge clear)`
262			`begin`
263	21	mihad	`if (clear)`
264			`// initial value is 2`
265			waddr <= #`FF_DELAY 2 ;
266			`else`
267			`if (wallow)`
268			waddr <= #`FF_DELAY waddr + 1'b1 ;
269	2	mihad	`end`
270
271
272			`/*------------------------------------------------------------------------------------------------------------------------------`
273			`Registered empty control:`
274	21	mihad	`registered empty is set on rising edge of rclock_in,`
275	2	mihad	`when only one location is used and read in/from fifo. It's kept high until something is written to FIFO, which is registered on`
276			`the next read clock.`
277			`--------------------------------------------------------------------------------------------------------------------------------*/`
278			`// combinatorial input for registered emty FlipFlop`
279			`wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) \|\| (rgrey_addr == wgrey_addr) ;`
280
281			`always@(posedge rclock_in or posedge clear)`
282			`begin`
283			`if (clear)`
284			empty <= #`FF_DELAY 1'b1 ;
285	58	mihad	`else if (flush_in)`
286			`empty <= #1 1'b1 ; // when flushed, set empty to active`
287	2	mihad	`else`
288			empty <= #`FF_DELAY reg_empty ;
289			`end`
290
291			`endmodule`

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