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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] [wbw_wbr_fifos.v] - Blame information for rev 63

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1 2 mihad
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  File name "wbw_wbr_fifos.v"                                 ////
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////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
6
////  http://www.opencores.org/cores/pci/                         ////
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////                                                              ////
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////  Author(s):                                                  ////
9
////      - Miha Dolenc (mihad@opencores.org)                     ////
10
////                                                              ////
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////  All additional information is avaliable in the README       ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
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////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
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////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 63 mihad
// Revision 1.6  2002/10/08 17:17:06  mihad
46
// Added BIST signals for RAMs.
47
//
48 62 mihad
// Revision 1.5  2002/09/30 16:03:04  mihad
49
// Added meta flop module for easier meta stable FF identification during synthesis
50
//
51 59 mihad
// Revision 1.4  2002/09/25 15:53:52  mihad
52
// Removed all logic from asynchronous reset network
53
//
54 58 mihad
// Revision 1.3  2002/02/01 15:25:14  mihad
55
// Repaired a few bugs, updated specification, added test bench files and design document
56
//
57 21 mihad
// Revision 1.2  2001/10/05 08:20:12  mihad
58
// Updated all files with inclusion of timescale file for simulation purposes.
59
//
60 7 mihad
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
61
// New project directory structure
62 2 mihad
//
63 7 mihad
//
64 2 mihad
 
65 21 mihad
`include "pci_constants.v"
66
 
67
// synopsys translate_off
68 7 mihad
`include "timescale.v"
69 21 mihad
// synopsys translate_on
70 2 mihad
 
71 62 mihad
module WBW_WBR_FIFOS
72
(
73
    wb_clock_in,
74
    pci_clock_in,
75
    reset_in,
76
    wbw_wenable_in,
77
    wbw_addr_data_in,
78
    wbw_cbe_in,
79
    wbw_control_in,
80
    wbw_renable_in,
81
    wbw_addr_data_out,
82
    wbw_cbe_out,
83
    wbw_control_out,
84
//    wbw_flush_in,         write fifo flush not used
85
    wbw_almost_full_out,
86
    wbw_full_out,
87
    wbw_empty_out,
88
    wbw_transaction_ready_out,
89
    wbr_wenable_in,
90
    wbr_data_in,
91
    wbr_be_in,
92
    wbr_control_in,
93
    wbr_renable_in,
94
    wbr_data_out,
95
    wbr_be_out,
96
    wbr_control_out,
97
    wbr_flush_in,
98
    wbr_empty_out
99
 
100
`ifdef PCI_BIST
101
    ,
102
    // debug chain signals
103 63 mihad
    trst       ,
104 62 mihad
    SO         ,
105
    SI         ,
106
    shift_DR   ,
107
    capture_DR ,
108
    extest     ,
109
    tck
110
`endif
111 2 mihad
) ;
112
 
113
/*-----------------------------------------------------------------------------------------------------------
114
System inputs:
115
wb_clock_in - WISHBONE bus clock
116
pci_clock_in - PCI bus clock
117
reset_in - reset from control logic
118
-------------------------------------------------------------------------------------------------------------*/
119
input wb_clock_in, pci_clock_in, reset_in ;
120
 
121
/*-----------------------------------------------------------------------------------------------------------
122
WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
123 21 mihad
WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
124 2 mihad
 
125
write enable signal:
126
wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
127
 
128
data input signals:
129
wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
130
wbw_cbe_in       = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
131
wbw_control_in   = control input - encoded control bus input
132
 
133
read enable signal:
134
wbw_renable_in = read enable input driven by PCI master interface
135
 
136
data output signals:
137
wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
138
wbw_cbe_out      = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
139
wbw_control_out = control input - encoded control bus input
140
 
141
status signals - monitored by various resources in the core
142
wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
143
wbw_almost_full_out = almost full output from WBW_FIFO
144
wbw_full_out = full output from WBW_FIFO
145
wbw_empty_out = empty output from WBW_FIFO
146
wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
147
-----------------------------------------------------------------------------------------------------------*/
148
// input control and data
149
input        wbw_wenable_in ;
150
input [31:0] wbw_addr_data_in ;
151
input [3:0]  wbw_cbe_in ;
152
input [3:0]  wbw_control_in ;
153
 
154
// output control and data
155
input         wbw_renable_in ;
156
output [31:0] wbw_addr_data_out ;
157
output [3:0]  wbw_cbe_out ;
158 21 mihad
output [3:0]  wbw_control_out ;
159 2 mihad
 
160
// flush input
161 58 mihad
// input wbw_flush_in ; // not used
162 2 mihad
 
163
// status outputs
164
output wbw_almost_full_out ;
165
output wbw_full_out ;
166
output wbw_empty_out ;
167
output wbw_transaction_ready_out ;
168
 
169
/*-----------------------------------------------------------------------------------------------------------
170 21 mihad
WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
171
initiated by master on WISHBONE bus and completed on PCI bus,
172 2 mihad
 
173
write enable signal:
174
wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
175
 
176
data input signals:
177
wbr_data_in      = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
178
wbr_be_in        = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
179
wbr_control_in   = control input - encoded control bus input
180
 
181
read enable signal:
182
wbr_renable_in = read enable input driven by WISHBONE slave interface
183
 
184
data output signals:
185
wbr_data_out = data output - data from PCI bus
186
wbr_be_out      = byte enable output(~#BE)
187
wbr_control_out = control output - encoded control bus output
188
 
189
status signals - monitored by various resources in the core
190
wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
191
wbr full_out = full output from WBR_FIFO
192
wbr_empty_out = empty output from WBR_FIFO
193
-----------------------------------------------------------------------------------------------------------*/
194
// input control and data
195
input        wbr_wenable_in ;
196
input [31:0] wbr_data_in ;
197
input [3:0]  wbr_be_in ;
198 21 mihad
input [3:0]  wbr_control_in ;
199 2 mihad
 
200
// output control and data
201
input         wbr_renable_in ;
202
output [31:0] wbr_data_out ;
203
output [3:0]  wbr_be_out ;
204 21 mihad
output [3:0]  wbr_control_out ;
205 2 mihad
 
206
// flush input
207 21 mihad
input wbr_flush_in ;
208 2 mihad
 
209
output wbr_empty_out ;
210
 
211 62 mihad
`ifdef PCI_BIST
212
/*-----------------------------------------------------
213
BIST debug chain port signals
214
-----------------------------------------------------*/
215 63 mihad
input   trst ;
216 62 mihad
output  SO ;
217
input   SI ;
218
input   shift_DR ;
219
input   capture_DR ;
220
input   extest ;
221
input   tck ;
222
`endif
223
 
224 2 mihad
/*-----------------------------------------------------------------------------------------------------------
225
FIFO depth parameters:
226
WBW_DEPTH = defines WBW_FIFO depth
227
WBR_DEPTH = defines WBR_FIFO depth
228
WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
229
WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
230
-----------------------------------------------------------------------------------------------------------*/
231
parameter WBW_DEPTH = `WBW_DEPTH ;
232
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
233
parameter WBR_DEPTH = `WBR_DEPTH ;
234
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
235
 
236
/*-----------------------------------------------------------------------------------------------------------
237
wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
238
wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
239
-----------------------------------------------------------------------------------------------------------*/
240
wire wbw_wallow ;
241
wire wbw_rallow ;
242
 
243
/*-----------------------------------------------------------------------------------------------------------
244
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
245
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
246
-----------------------------------------------------------------------------------------------------------*/
247
wire wbr_wallow ;
248
wire wbr_rallow ;
249
 
250
/*-----------------------------------------------------------------------------------------------------------
251
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
252
-----------------------------------------------------------------------------------------------------------*/
253
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
254
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
255
 
256
/*-----------------------------------------------------------------------------------------------------------
257
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
258
-----------------------------------------------------------------------------------------------------------*/
259
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
260
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
261
 
262
/*-----------------------------------------------------------------------------------------------------------
263
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
264
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
265
currently present in the FIFO.
266
-----------------------------------------------------------------------------------------------------------*/
267
reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
268
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
269
 
270
/*-----------------------------------------------------------------------------------------------------------
271
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
272
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
273
it means that there was one complete transaction taken out of FIFO.
274
-----------------------------------------------------------------------------------------------------------*/
275
wire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;
276
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
277
 
278
wire wbw_empty ;
279
wire wbr_empty ;
280
 
281
assign wbw_empty_out = wbw_empty ;
282
assign wbr_empty_out = wbr_empty ;
283
 
284
// clear wires for fifos
285 58 mihad
wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
286
wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous
287 2 mihad
 
288
/*-----------------------------------------------------------------------------------------------------------
289 21 mihad
Definitions of wires for connecting RAM instances
290 2 mihad
-----------------------------------------------------------------------------------------------------------*/
291 21 mihad
wire [39:0] dpram_portA_output ;
292
wire [39:0] dpram_portB_output ;
293 2 mihad
 
294 21 mihad
wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
295
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
296 2 mihad
 
297 21 mihad
/*-----------------------------------------------------------------------------------------------------------
298
Fifo output assignments - each ram port provides data for different fifo
299
-----------------------------------------------------------------------------------------------------------*/
300
assign wbw_control_out = dpram_portB_output[39:36] ;
301
assign wbr_control_out = dpram_portA_output[39:36] ;
302 2 mihad
 
303 21 mihad
assign wbw_cbe_out     = dpram_portB_output[35:32] ;
304
assign wbr_be_out      = dpram_portA_output[35:32] ;
305 2 mihad
 
306 21 mihad
assign wbw_addr_data_out = dpram_portB_output[31:0] ;
307
assign wbr_data_out      = dpram_portA_output[31:0] ;
308 2 mihad
 
309 21 mihad
`ifdef WB_RAM_DONT_SHARE
310 2 mihad
 
311 21 mihad
    /*-----------------------------------------------------------------------------------------------------------
312
    Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
313
    accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
314
    that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
315
    write port is always port a and read port is port b.
316
    -----------------------------------------------------------------------------------------------------------*/
317 2 mihad
 
318 21 mihad
    /*-----------------------------------------------------------------------------------------------------------
319
    Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
320
    -----------------------------------------------------------------------------------------------------------*/
321
    /*
322
    wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
323
    wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
324
    */
325 2 mihad
 
326 21 mihad
    // compose complete port addresses
327
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
328
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
329 2 mihad
 
330 21 mihad
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
331
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
332 2 mihad
 
333 21 mihad
    wire wbw_read_enable = 1'b1 ;
334
    wire wbr_read_enable = 1'b1 ;
335 2 mihad
 
336 62 mihad
    `ifdef PCI_BIST
337
    wire SO_internal ; // wires for connection of debug ports on two rams
338
    wire SI_internal = SO_internal ;
339
    `endif
340
 
341 21 mihad
    // instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
342
    WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
343
    (
344
        // Generic synchronous two-port RAM interface
345
        .clk_a(wb_clock_in),
346
        .rst_a(reset_in),
347
        .ce_a(1'b1),
348
        .we_a(wbw_wallow),
349
        .oe_a(1'b1),
350
        .addr_a(wbw_whole_waddr),
351
        .di_a(dpram_portA_input),
352
        .do_a(),
353 2 mihad
 
354 21 mihad
        .clk_b(pci_clock_in),
355
        .rst_b(reset_in),
356
        .ce_b(wbw_read_enable),
357
        .we_b(1'b0),
358
        .oe_b(1'b1),
359
        .addr_b(wbw_whole_raddr),
360
        .di_b(40'h00_0000_0000),
361
        .do_b(dpram_portB_output)
362 62 mihad
 
363
    `ifdef PCI_BIST
364
        ,
365 63 mihad
        .trst       (trst),
366 62 mihad
        .SO         (SO_internal),
367
        .SI         (SI),
368
        .shift_DR   (shift_DR),
369
        .capture_DR (capture_DR),
370
        .extest     (extest),
371
        .tck        (tck)
372
    `endif
373 21 mihad
    );
374 2 mihad
 
375 21 mihad
    WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
376
    (
377
        // Generic synchronous two-port RAM interface
378
        .clk_a(pci_clock_in),
379
        .rst_a(reset_in),
380
        .ce_a(1'b1),
381
        .we_a(wbr_wallow),
382
        .oe_a(1'b1),
383
        .addr_a(wbr_whole_waddr),
384
        .di_a(dpram_portB_input),
385
        .do_a(),
386 2 mihad
 
387 21 mihad
        .clk_b(wb_clock_in),
388
        .rst_b(reset_in),
389
        .ce_b(wbr_read_enable),
390
        .we_b(1'b0),
391
        .oe_b(1'b1),
392
        .addr_b(wbr_whole_raddr),
393
        .di_b(40'h00_0000_0000),
394
        .do_b(dpram_portA_output)
395 62 mihad
 
396
    `ifdef PCI_BIST
397
        ,
398 63 mihad
        .trst       (trst),
399 62 mihad
        .SO         (SO),
400
        .SI         (SI_internal),
401
        .shift_DR   (shift_DR),
402
        .capture_DR (capture_DR),
403
        .extest     (extest),
404
        .tck        (tck)
405
    `endif
406 21 mihad
    );
407 2 mihad
 
408 21 mihad
`else // RAM blocks sharing between two fifos
409 2 mihad
 
410 21 mihad
    /*-----------------------------------------------------------------------------------------------------------
411
    Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
412
    case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
413
    -----------------------------------------------------------------------------------------------------------*/
414
    /*-----------------------------------------------------------------------------------------------------------
415
    Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
416
    addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
417
    must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
418
    -----------------------------------------------------------------------------------------------------------*/
419
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
420
    wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
421 2 mihad
 
422
    /*-----------------------------------------------------------------------------------------------------------
423 21 mihad
    Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
424
    on both sides.
425
    Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
426
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
427 2 mihad
    -----------------------------------------------------------------------------------------------------------*/
428 21 mihad
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
429
 
430
    /*-----------------------------------------------------------------------------------------------------------
431
    Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
432
    Address is multiplexed so operation can be switched between fifos. Default is a read on port.
433
    -----------------------------------------------------------------------------------------------------------*/
434
    wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
435
 
436
    wire portA_enable      = 1'b1 ;
437
 
438
    wire portB_enable      = 1'b1 ;
439
 
440
    // instantiate RAM for these two fifos
441
    WB_TPRAM #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
442
    (
443
        // Generic synchronous two-port RAM interface
444
        .clk_a(wb_clock_in),
445
        .rst_a(reset_in),
446
        .ce_a(portA_enable),
447
        .we_a(wbw_wallow),
448
        .oe_a(1'b1),
449
        .addr_a(portA_addr),
450
        .di_a(dpram_portA_input),
451
        .do_a(dpram_portA_output),
452
        .clk_b(pci_clock_in),
453
        .rst_b(reset_in),
454
        .ce_b(portB_enable),
455
        .we_b(wbr_wallow),
456
        .oe_b(1'b1),
457
        .addr_b(portB_addr),
458
        .di_b(dpram_portB_input),
459
        .do_b(dpram_portB_output)
460 62 mihad
 
461
    `ifdef PCI_BIST
462
        ,
463 63 mihad
        .trst       (trst),
464 62 mihad
        .SO         (SO),
465
        .SI         (SI),
466
        .shift_DR   (shift_DR),
467
        .capture_DR (capture_DR),
468
        .extest     (extest),
469
        .tck        (tck)
470
    `endif
471 21 mihad
    );
472
 
473 2 mihad
`endif
474
 
475
/*-----------------------------------------------------------------------------------------------------------
476
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
477
-----------------------------------------------------------------------------------------------------------*/
478
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
479 21 mihad
(
480
    .rclock_in(pci_clock_in),
481
    .wclock_in(wb_clock_in),
482
    .renable_in(wbw_renable_in),
483
    .wenable_in(wbw_wenable_in),
484
    .reset_in(reset_in),
485 58 mihad
//    .flush_in(wbw_flush_in),
486 21 mihad
    .almost_full_out(wbw_almost_full_out),
487
    .full_out(wbw_full_out),
488
    .empty_out(wbw_empty),
489
    .waddr_out(wbw_waddr),
490
    .raddr_out(wbw_raddr),
491
    .rallow_out(wbw_rallow),
492
    .wallow_out(wbw_wallow)
493
);
494 2 mihad
 
495
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
496 21 mihad
(   .rclock_in(wb_clock_in),
497
    .wclock_in(pci_clock_in),
498
    .renable_in(wbr_renable_in),
499
    .wenable_in(wbr_wenable_in),
500
    .reset_in(reset_in),
501
    .flush_in(wbr_flush_in),
502
    .empty_out(wbr_empty),
503
    .waddr_out(wbr_waddr),
504
    .raddr_out(wbr_raddr),
505
    .rallow_out(wbr_rallow),
506
    .wallow_out(wbr_wallow)
507
);
508 2 mihad
 
509
 
510
// in and out transaction counters and grey codes
511
reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
512
reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
513
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
514
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
515
 
516 21 mihad
// input transaction counter increment - when last data of transaction is written to fifo
517 2 mihad
wire in_count_en  = wbw_wallow && wbw_last_in ;
518 21 mihad
 
519
// output transaction counter increment - when last data is on top of fifo and read from it
520 2 mihad
wire out_count_en = wbw_renable_in && wbw_last_out ;
521
 
522 21 mihad
// register holding grey coded count of incoming transactions
523 2 mihad
always@(posedge wb_clock_in or posedge wbw_clear)
524
begin
525
    if (wbw_clear)
526
    begin
527
        inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
528
        inGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
529
    end
530
    else
531
    if (in_count_en)
532
        inGreyCount <= #`FF_DELAY inNextGreyCount ;
533
end
534
 
535 21 mihad
// register holding grey coded count of outgoing transactions
536 2 mihad
always@(posedge pci_clock_in or posedge wbw_clear)
537
begin
538
    if (wbw_clear)
539
    begin
540
        outGreyCount[(WBW_ADDR_LENGTH-2)]   <= #`FF_DELAY 1'b1 ;
541
        outGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
542
    end
543
    else
544
    if (out_count_en)
545
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
546
end
547
 
548 21 mihad
// incoming transactions counter
549 2 mihad
always@(posedge wb_clock_in or posedge wbw_clear)
550
begin
551
    if (wbw_clear)
552
        wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
553
    else
554
    if (in_count_en)
555
        wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
556
end
557
 
558 21 mihad
// outgoing transactions counter
559 2 mihad
always@(posedge pci_clock_in or posedge wbw_clear)
560
begin
561
    if (wbw_clear)
562
        wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
563
    else
564
    if (out_count_en)
565
        wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
566
end
567
 
568
// synchronize transaction ready output to reading clock
569 21 mihad
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
570
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
571 59 mihad
wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
572 2 mihad
 
573 59 mihad
meta_flop #(0) i_meta_flop_wbw_transaction_ready
574
(
575
    .rst_i      (wbw_clear),
576
    .clk_i      (pci_clock_in),
577
    .ld_i       (out_count_en),
578
    .ld_val_i   (1'b0),
579
    .en_i       (1'b1),
580
    .d_i        (wbw_transaction_ready_flop_i),
581
    .meta_q_o   (wbw_transaction_ready_out)
582
) ;
583
 
584 2 mihad
endmodule
585
 

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