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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wbw_wbr_fifos.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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mihad |
//
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mihad |
//
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mihad |
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`include "constants.v"
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mihad |
`include "timescale.v"
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mihad |
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module WBW_WBR_FIFOS(
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wb_clock_in,
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pci_clock_in,
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reset_in,
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wbw_wenable_in,
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wbw_addr_data_in,
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wbw_cbe_in,
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wbw_control_in,
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wbw_renable_in,
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wbw_addr_data_out,
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wbw_cbe_out,
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wbw_control_out,
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wbw_flush_in,
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wbw_almost_full_out,
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wbw_full_out,
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wbw_empty_out,
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wbw_transaction_ready_out,
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wbr_wenable_in,
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wbr_data_in,
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wbr_be_in,
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wbr_control_in,
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wbr_renable_in,
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wbr_data_out,
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wbr_be_out,
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wbr_control_out,
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wbr_flush_in,
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wbr_empty_out
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) ;
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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wb_clock_in - WISHBONE bus clock
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pci_clock_in - PCI bus clock
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reset_in - reset from control logic
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-------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, pci_clock_in, reset_in ;
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/*-----------------------------------------------------------------------------------------------------------
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WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
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WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
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write enable signal:
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wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
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data input signals:
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wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
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wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
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wbw_control_in = control input - encoded control bus input
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read enable signal:
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wbw_renable_in = read enable input driven by PCI master interface
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data output signals:
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wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
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wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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wbw_control_out = control input - encoded control bus input
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status signals - monitored by various resources in the core
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wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
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wbw_almost_full_out = almost full output from WBW_FIFO
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wbw_full_out = full output from WBW_FIFO
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wbw_empty_out = empty output from WBW_FIFO
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wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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input wbw_wenable_in ;
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input [31:0] wbw_addr_data_in ;
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input [3:0] wbw_cbe_in ;
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input [3:0] wbw_control_in ;
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// output control and data
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input wbw_renable_in ;
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output [31:0] wbw_addr_data_out ;
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output [3:0] wbw_cbe_out ;
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output [3:0] wbw_control_out ;
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// flush input
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input wbw_flush_in ;
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// status outputs
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output wbw_almost_full_out ;
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output wbw_full_out ;
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output wbw_empty_out ;
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output wbw_transaction_ready_out ;
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/*-----------------------------------------------------------------------------------------------------------
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WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
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initiated by master on WISHBONE bus and completed on PCI bus,
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write enable signal:
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wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
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data input signals:
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wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
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wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
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wbr_control_in = control input - encoded control bus input
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read enable signal:
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wbr_renable_in = read enable input driven by WISHBONE slave interface
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data output signals:
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wbr_data_out = data output - data from PCI bus
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wbr_be_out = byte enable output(~#BE)
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wbr_control_out = control output - encoded control bus output
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status signals - monitored by various resources in the core
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wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
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wbr full_out = full output from WBR_FIFO
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wbr_empty_out = empty output from WBR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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input wbr_wenable_in ;
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input [31:0] wbr_data_in ;
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input [3:0] wbr_be_in ;
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input [3:0] wbr_control_in ;
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// output control and data
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input wbr_renable_in ;
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output [31:0] wbr_data_out ;
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output [3:0] wbr_be_out ;
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output [3:0] wbr_control_out ;
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// flush input
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input wbr_flush_in ;
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output wbr_empty_out ;
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/*-----------------------------------------------------------------------------------------------------------
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FIFO depth parameters:
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WBW_DEPTH = defines WBW_FIFO depth
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WBR_DEPTH = defines WBR_FIFO depth
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WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
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WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
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-----------------------------------------------------------------------------------------------------------*/
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parameter WBW_DEPTH = `WBW_DEPTH ;
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parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
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parameter WBR_DEPTH = `WBR_DEPTH ;
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parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
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// obvious
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wire vcc = 1'b1 ;
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wire gnd = 1'b0 ;
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/*-----------------------------------------------------------------------------------------------------------
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wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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-----------------------------------------------------------------------------------------------------------*/
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wire wbw_wallow ;
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wire wbw_rallow ;
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/*-----------------------------------------------------------------------------------------------------------
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wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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-----------------------------------------------------------------------------------------------------------*/
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wire wbr_wallow ;
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wire wbr_rallow ;
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/*-----------------------------------------------------------------------------------------------------------
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wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
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wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
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/*-----------------------------------------------------------------------------------------------------------
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wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
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wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
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/*-----------------------------------------------------------------------------------------------------------
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WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
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input transactions is equal to number of output transactions, it means that there isn't any complete transaction
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currently present in the FIFO.
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-----------------------------------------------------------------------------------------------------------*/
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reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
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reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
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/*-----------------------------------------------------------------------------------------------------------
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FlipFlops for indicating if complete delayed read completion is present in the FIFO
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-----------------------------------------------------------------------------------------------------------*/
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/*reg wbr_inTransactionCount ;
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reg wbr_outTransactionCount ;*/
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/*-----------------------------------------------------------------------------------------------------------
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wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
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complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
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it means that there was one complete transaction taken out of FIFO.
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-----------------------------------------------------------------------------------------------------------*/
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wire wbw_last_in = wbw_control_in[`LAST_CTRL_BIT] ;
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wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
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/*wire wbr_last_in = wbr_wallow && wbr_control_in[`LAST_CTRL_BIT] ;
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wire wbr_last_out = wbr_rallow && wbr_control_out[`LAST_CTRL_BIT] ;*/
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wire wbw_empty ;
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wire wbr_empty ;
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assign wbw_empty_out = wbw_empty ;
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assign wbr_empty_out = wbr_empty ;
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// clear wires for fifos
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wire wbw_clear = reset_in || wbw_flush_in ; // WBW_FIFO clear
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wire wbr_clear = reset_in || wbr_flush_in ; // WBR_FIFO clear
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`ifdef FPGA
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/*-----------------------------------------------------------------------------------------------------------
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this code is included only for FPGA core usage - somewhat different logic because of sharing
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one block selectRAM+ between two FIFOs
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-----------------------------------------------------------------------------------------------------------*/
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`ifdef BIG
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/*-----------------------------------------------------------------------------------------------------------
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Big FPGAs
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WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
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FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
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-----------------------------------------------------------------------------------------------------------*/
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wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
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wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b0}} ;
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// compose addresses
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wire [7:0] wbw_whole_waddr = {wbw_addr_prefix, wbw_waddr} ;
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wire [7:0] wbw_whole_raddr = {wbw_addr_prefix, wbw_raddr} ;
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wire [7:0] wbr_whole_waddr = {wbr_addr_prefix, wbr_waddr} ;
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wire [7:0] wbr_whole_raddr = {wbr_addr_prefix, wbr_raddr} ;
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/*-----------------------------------------------------------------------------------------------------------
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Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
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-----------------------------------------------------------------------------------------------------------*/
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wire [15:0] dpram3_portB_output ;
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wire [15:0] dpram6_portA_output ;
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283 |
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/*-----------------------------------------------------------------------------------------------------------
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284 |
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Control out assignements from ram3 output
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285 |
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-----------------------------------------------------------------------------------------------------------*/
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assign wbw_control_out = dpram3_portB_output[15:12] ;
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assign wbr_control_out = dpram6_portA_output[15:12] ;
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288 |
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289 |
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assign wbw_cbe_out = dpram3_portB_output[3:0] ;
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assign wbr_be_out = dpram6_portA_output[3:0] ;
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291 |
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wire wbw_read_enable = 1'b1 ;
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wire wbr_read_enable = 1'b1 ;
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294 |
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295 |
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// Block SelectRAM+ cells instantiation
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296 |
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RAMB4_S16_S16 dpram16_1 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[15:0]),
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.ENA(vcc), .RSTA(reset_in),
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.CLKA(wb_clock_in), .WEA(wbw_wallow),
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.DOA(),
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.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
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.ENB(wbw_read_enable), .RSTB(reset_in),
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.CLKB(pci_clock_in), .WEB(gnd),
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.DOB(wbw_addr_data_out[15:0])) ;
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RAMB4_S16_S16 dpram16_2 (.ADDRA(wbw_whole_waddr), .DIA(wbw_addr_data_in[31:16]),
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.ENA(vcc), .RSTA(reset_in),
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.CLKA(wb_clock_in), .WEA(wbw_wallow),
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.DOA(),
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.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
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.ENB(wbw_read_enable), .RSTB(reset_in),
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.CLKB(pci_clock_in), .WEB(gnd),
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.DOB(wbw_addr_data_out[31:16])) ;
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RAMB4_S16_S16 dpram16_3 (.ADDRA(wbw_whole_waddr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
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.ENA(vcc), .RSTA(reset_in),
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.CLKA(wb_clock_in), .WEA(wbw_wallow),
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317 |
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.DOA(),
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.ADDRB(wbw_whole_raddr), .DIB(16'h0000),
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319 |
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.ENB(wbw_read_enable), .RSTB(reset_in),
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|
|
.CLKB(pci_clock_in), .WEB(gnd),
|
321 |
|
|
.DOB(dpram3_portB_output)) ;
|
322 |
|
|
|
323 |
|
|
RAMB4_S16_S16 dpram16_4 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
324 |
|
|
.ENA(1'b1), .RSTA(reset_in),
|
325 |
|
|
.CLKA(wb_clock_in), .WEA(gnd),
|
326 |
|
|
.DOA(wbr_data_out[15:0]),
|
327 |
|
|
.ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[15:0]),
|
328 |
|
|
.ENB(wbr_read_enable), .RSTB(reset_in),
|
329 |
|
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
330 |
|
|
.DOB()) ;
|
331 |
|
|
|
332 |
|
|
RAMB4_S16_S16 dpram16_5 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
333 |
|
|
.ENA(1'b1), .RSTA(reset_in),
|
334 |
|
|
.CLKA(wb_clock_in), .WEA(gnd),
|
335 |
|
|
.DOA(wbr_data_out[31:16]),
|
336 |
|
|
.ADDRB(wbr_whole_waddr), .DIB(wbr_data_in[31:16]),
|
337 |
|
|
.ENB(wbr_read_enable), .RSTB(reset_in),
|
338 |
|
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
339 |
|
|
.DOB()) ;
|
340 |
|
|
|
341 |
|
|
RAMB4_S16_S16 dpram16_6 (.ADDRA(wbr_whole_raddr), .DIA(16'h0000),
|
342 |
|
|
.ENA(1'b1), .RSTA(reset_in),
|
343 |
|
|
.CLKA(wb_clock_in), .WEA(gnd),
|
344 |
|
|
.DOA(dpram6_portA_output),
|
345 |
|
|
.ADDRB(wbr_whole_waddr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
|
346 |
|
|
.ENB(wbr_read_enable), .RSTB(reset_in),
|
347 |
|
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
348 |
|
|
.DOB()) ;
|
349 |
|
|
|
350 |
|
|
`else // SMALL FPGAs
|
351 |
|
|
|
352 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
353 |
|
|
Small FPGAs
|
354 |
|
|
WBW_FIFO and WBR_FIFO address prefixes - used for extending read and write addresses because of varible
|
355 |
|
|
FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
|
356 |
|
|
WBW addresses are zero padded on the left, WBR addresses are padded
|
357 |
|
|
with ones on the left
|
358 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
359 |
|
|
wire [(7 - WBW_ADDR_LENGTH):0] wbw_addr_prefix = {( 8 - WBW_ADDR_LENGTH){1'b0}} ;
|
360 |
|
|
wire [(7 - WBR_ADDR_LENGTH):0] wbr_addr_prefix = {( 8 - WBR_ADDR_LENGTH){1'b1}} ;
|
361 |
|
|
|
362 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
363 |
|
|
Only 8 bits out of 16 are used in ram3 - wires for referencing them
|
364 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
365 |
|
|
wire [15:0] dpram3_portA_output ;
|
366 |
|
|
wire [15:0] dpram3_portB_output ;
|
367 |
|
|
|
368 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
369 |
|
|
Control out assignements from ram3 output
|
370 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
371 |
|
|
assign wbw_control_out = dpram3_portB_output[15:12] ;
|
372 |
|
|
assign wbr_control_out = dpram3_portA_output[15:12] ;
|
373 |
|
|
|
374 |
|
|
assign wbw_cbe_out = dpram3_portB_output[3:0] ;
|
375 |
|
|
assign wbr_be_out = dpram3_portA_output[3:0] ;
|
376 |
|
|
|
377 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
378 |
|
|
Port A address generation for block SelectRam+ in SpartanII or Virtex
|
379 |
|
|
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo. Address is multiplexed
|
380 |
|
|
between two values.
|
381 |
|
|
Address multiplexing:
|
382 |
|
|
wbw_wenable == 1 => ADDRA = wbw_waddr (write pointer of WBW_FIFO)
|
383 |
|
|
else ADDRA = wbr_raddr (read pointer of WBR_FIFO)
|
384 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
385 |
|
|
wire [7:0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
|
386 |
|
|
|
387 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
388 |
|
|
Port B address generation for block SelectRam+ in SpartanII or Virtex
|
389 |
|
|
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo. Address is multiplexed
|
390 |
|
|
between two values.
|
391 |
|
|
Address multiplexing:
|
392 |
|
|
wbr_wenable == 1 => ADDRB = wbr_waddr (write pointer of WBR_FIFO)
|
393 |
|
|
else ADDRB = wbw_raddr (read pointer of WBW_FIFO)
|
394 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
395 |
|
|
wire [7:0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
|
396 |
|
|
|
397 |
|
|
wire portA_enable = 1'b1 ;
|
398 |
|
|
|
399 |
|
|
wire portB_enable = 1'b1 ;
|
400 |
|
|
|
401 |
|
|
// Block SelectRAM+ cells instantiation
|
402 |
|
|
RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[15:0]),
|
403 |
|
|
.ENA(portA_enable), .RSTA(reset_in),
|
404 |
|
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
405 |
|
|
.DOA(wbr_data_out[15:0]),
|
406 |
|
|
.ADDRB(portB_addr), .DIB(wbr_data_in[15:0]),
|
407 |
|
|
.ENB(portB_enable), .RSTB(reset_in),
|
408 |
|
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
409 |
|
|
.DOB(wbw_addr_data_out[15:0])) ;
|
410 |
|
|
|
411 |
|
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(wbw_addr_data_in[31:16]),
|
412 |
|
|
.ENA(portA_enable), .RSTA(reset_in),
|
413 |
|
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
414 |
|
|
.DOA(wbr_data_out[31:16]),
|
415 |
|
|
.ADDRB(portB_addr), .DIB(wbr_data_in[31:16]),
|
416 |
|
|
.ENB(portB_enable), .RSTB(reset_in),
|
417 |
|
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
418 |
|
|
.DOB(wbw_addr_data_out[31:16])) ;
|
419 |
|
|
|
420 |
|
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({wbw_control_in, 8'h00, wbw_cbe_in}),
|
421 |
|
|
.ENA(portA_enable), .RSTA(reset_in),
|
422 |
|
|
.CLKA(wb_clock_in), .WEA(wbw_wallow),
|
423 |
|
|
.DOA(dpram3_portA_output),
|
424 |
|
|
.ADDRB(portB_addr), .DIB({wbr_control_in, 8'h00, wbr_be_in}),
|
425 |
|
|
.ENB(portB_enable), .RSTB(reset_in),
|
426 |
|
|
.CLKB(pci_clock_in), .WEB(wbr_wallow),
|
427 |
|
|
.DOB(dpram3_portB_output)) ;
|
428 |
|
|
`endif
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
`else
|
435 |
|
|
wire [39:0] wbw_ram_data_out ;
|
436 |
|
|
wire [39:0] wbw_ram_data_in = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
|
437 |
|
|
wire [39:0] wbr_ram_data_in = {wbr_control_in, wbr_be_in, wbr_data_in} ;
|
438 |
|
|
wire [39:0] wbr_ram_data_out ;
|
439 |
|
|
assign wbw_control_out = wbw_ram_data_out[39:36] ;
|
440 |
|
|
assign wbw_cbe_out = wbw_ram_data_out[35:32] ;
|
441 |
|
|
assign wbw_addr_data_out = wbw_ram_data_out [31:0] ;
|
442 |
|
|
|
443 |
|
|
assign wbr_control_out = wbr_ram_data_out[39:36] ;
|
444 |
|
|
assign wbr_be_out = wbr_ram_data_out[35:32] ;
|
445 |
|
|
assign wbr_data_out = wbr_ram_data_out [31:0] ;
|
446 |
|
|
|
447 |
|
|
`ifdef SYNCHRONOUS
|
448 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
449 |
|
|
ASIC memory primitives will be added here in the near future - currently there is only some generic,
|
450 |
|
|
behavioral dual port ram here
|
451 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
452 |
|
|
DP_SRAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(wbw_ram_data_in),
|
453 |
|
|
.raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .renable_in(1'b1), .wenable_in(wbw_wallow));
|
454 |
|
|
|
455 |
|
|
DP_SRAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(wbr_ram_data_in),
|
456 |
|
|
.raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .renable_in(1'b1), .wenable_in(wbr_wallow));
|
457 |
|
|
|
458 |
|
|
`else //ASYNCHRONOUS RAM
|
459 |
|
|
DP_ASYNC_RAM #(WBW_ADDR_LENGTH, WBW_DEPTH) wbw_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(wbw_ram_data_in),
|
460 |
|
|
.raddr_in(wbw_raddr), .waddr_in(wbw_waddr), .data_out(wbw_ram_data_out), .wenable_in(wbw_wallow));
|
461 |
|
|
|
462 |
|
|
DP_ASYNC_RAM #(WBR_ADDR_LENGTH, WBR_DEPTH) wbr_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(wbr_ram_data_in),
|
463 |
|
|
.raddr_in(wbr_raddr), .waddr_in(wbr_waddr), .data_out(wbr_ram_data_out), .wenable_in(wbr_wallow));
|
464 |
|
|
`endif
|
465 |
|
|
`endif
|
466 |
|
|
|
467 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
468 |
|
|
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
|
469 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
470 |
|
|
WBW_FIFO_CONTROL #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
|
471 |
|
|
(.rclock_in(pci_clock_in), .wclock_in(wb_clock_in), .renable_in(wbw_renable_in),
|
472 |
|
|
.wenable_in(wbw_wenable_in), .reset_in(reset_in), .flush_in(wbw_flush_in),
|
473 |
|
|
.almost_full_out(wbw_almost_full_out), .full_out(wbw_full_out),
|
474 |
|
|
.empty_out(wbw_empty),
|
475 |
|
|
.waddr_out(wbw_waddr), .raddr_out(wbw_raddr),
|
476 |
|
|
.rallow_out(wbw_rallow), .wallow_out(wbw_wallow));
|
477 |
|
|
|
478 |
|
|
WBR_FIFO_CONTROL #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
|
479 |
|
|
(.rclock_in(wb_clock_in), .wclock_in(pci_clock_in), .renable_in(wbr_renable_in),
|
480 |
|
|
.wenable_in(wbr_wenable_in), .reset_in(reset_in), .flush_in(wbr_flush_in),
|
481 |
|
|
.empty_out(wbr_empty),
|
482 |
|
|
.waddr_out(wbr_waddr), .raddr_out(wbr_raddr),
|
483 |
|
|
.rallow_out(wbr_rallow), .wallow_out(wbr_wallow));
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
// in and out transaction counters and grey codes
|
487 |
|
|
reg [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
|
488 |
|
|
reg [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
|
489 |
|
|
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
490 |
|
|
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
|
491 |
|
|
|
492 |
|
|
wire in_count_en = wbw_wallow && wbw_last_in ;
|
493 |
|
|
wire out_count_en = wbw_renable_in && wbw_last_out ;
|
494 |
|
|
|
495 |
|
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
496 |
|
|
begin
|
497 |
|
|
if (wbw_clear)
|
498 |
|
|
begin
|
499 |
|
|
inGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
500 |
|
|
inGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
501 |
|
|
end
|
502 |
|
|
else
|
503 |
|
|
if (in_count_en)
|
504 |
|
|
inGreyCount <= #`FF_DELAY inNextGreyCount ;
|
505 |
|
|
end
|
506 |
|
|
|
507 |
|
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
508 |
|
|
begin
|
509 |
|
|
if (wbw_clear)
|
510 |
|
|
begin
|
511 |
|
|
outGreyCount[(WBW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
512 |
|
|
outGreyCount[(WBW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(WBW_ADDR_LENGTH-2),1'b0} ;
|
513 |
|
|
end
|
514 |
|
|
else
|
515 |
|
|
if (out_count_en)
|
516 |
|
|
outGreyCount <= #`FF_DELAY outNextGreyCount ;
|
517 |
|
|
end
|
518 |
|
|
|
519 |
|
|
always@(posedge wb_clock_in or posedge wbw_clear)
|
520 |
|
|
begin
|
521 |
|
|
if (wbw_clear)
|
522 |
|
|
wbw_inTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
523 |
|
|
else
|
524 |
|
|
if (in_count_en)
|
525 |
|
|
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
|
526 |
|
|
end
|
527 |
|
|
|
528 |
|
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
529 |
|
|
begin
|
530 |
|
|
if (wbw_clear)
|
531 |
|
|
wbw_outTransactionCount <= #`FF_DELAY {(WBW_ADDR_LENGTH-1){1'b0}} ;
|
532 |
|
|
else
|
533 |
|
|
if (out_count_en)
|
534 |
|
|
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
|
535 |
|
|
end
|
536 |
|
|
|
537 |
|
|
/*always@(posedge pci_clock_in or posedge wbr_clear)
|
538 |
|
|
begin
|
539 |
|
|
if (wbr_clear)
|
540 |
|
|
wbr_inTransactionCount <= #`FF_DELAY 1'b0 ;
|
541 |
|
|
else
|
542 |
|
|
if (wbr_last_in && wbr_wallow)
|
543 |
|
|
wbr_inTransactionCount <= #`FF_DELAY ~wbr_inTransactionCount ;
|
544 |
|
|
end
|
545 |
|
|
|
546 |
|
|
always@(posedge wb_clock_in or posedge wbr_clear)
|
547 |
|
|
begin
|
548 |
|
|
if (wbr_clear)
|
549 |
|
|
wbr_outTransactionCount <= #`FF_DELAY 1'b0 ;
|
550 |
|
|
else
|
551 |
|
|
if (wbr_last_out)
|
552 |
|
|
wbr_outTransactionCount <= #`FF_DELAY ~wbr_outTransactionCount ;
|
553 |
|
|
end
|
554 |
|
|
*/
|
555 |
|
|
|
556 |
|
|
// synchronize transaction ready output to reading clock
|
557 |
|
|
reg wbw_transaction_ready_out ;
|
558 |
|
|
always@(posedge pci_clock_in or posedge wbw_clear)
|
559 |
|
|
begin
|
560 |
|
|
if (wbw_clear)
|
561 |
|
|
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
562 |
|
|
else
|
563 |
|
|
if ( out_count_en )
|
564 |
|
|
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
565 |
|
|
else
|
566 |
|
|
wbw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
|
567 |
|
|
end
|
568 |
|
|
|
569 |
|
|
endmodule
|
570 |
|
|
|