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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_bus_monitor.v] - Blame information for rev 35

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1 15 mihad 
//===========================================================================
2 35 mihad 
// $Id: pci_bus_monitor.v,v 1.2 2002-03-21 07:35:50 mihad Exp $
3 15 mihad 
//
4 
// Copyright 2001 Blue Beaver.  All Rights Reserved.
5 
//
6 
// Summary:  Watch the PCI Bus Wires to try to see Protocol Errors.
7 
//           This module also has access to the individual PCI Bus OE
8 
//           signals for each interface (either through extra output
9 
//           ports or through "." notation), and it can see when more
10 
//           than one interface is driving the bus, even if the values
11 
//           are the same.
12 
//           A future version of this module should write out a transcript
13 
//           of the activity seen on the PCI Bus.
14 
//
15 
// This library is free software; you can distribute it and/or modify it
16 
// under the terms of the GNU Lesser General Public License as published
17 
// by the Free Software Foundation; either version 2.1 of the License, or
18 
// (at your option) any later version.
19 
//
20 
// This library is distributed in the hope that it will be useful, but
21 
// WITHOUT ANY WARRANTY; without even the implied warranty of
22 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
23 
// See the GNU Lesser General Public License for more details.
24 
//
25 
// You should have received a copy of the GNU Lesser General Public License
26 
// along with this library.  If not, write to
27 
// Free Software Foundation, Inc.
28 
// 59 Temple Place, Suite 330
29 
// Boston, MA 02111-1307 USA
30 
//
31 
// Author's note about this license:  The intention of the Author and of
32 
// the Gnu Lesser General Public License is that users should be able to
33 
// use this code for any purpose, including combining it with other source
34 
// code, combining it with other logic, translated it into a gate-level
35 
// representation, or projected it into gates in a programmable or
36 
// hardwired chip, as long as the users of the resulting source, compiled
37 
// source, or chip are given the means to get a copy of this source code
38 
// with no new restrictions on redistribution of this source.
39 
//
40 
// If you make changes, even substantial changes, to this code, or use
41 
// substantial parts of this code as an inseparable part of another work
42 
// of authorship, the users of the resulting IP must be given the means
43 
// to get a copy of the modified or combined source code, with no new
44 
// restrictions on redistribution of the resulting source.
45 
//
46 
// Separate parts of the combined source code, compiled code, or chip,
47 
// which are NOT derived from this source code do NOT need to be offered
48 
// to the final user of the chip merely because they are used in
49 
// combination with this code.  Other code is not forced to fall under
50 
// the GNU Lesser General Public License when it is linked to this code.
51 
// The license terms of other source code linked to this code might require
52 
// that it NOT be made available to users.  The GNU Lesser General Public
53 
// License does not prevent this code from being used in such a situation,
54 
// as long as the user of the resulting IP is given the means to get a
55 
// copy of this component of the IP with no new restrictions on
56 
// redistribution of this source.
57 
//
58 
// This code was developed using VeriLogger Pro, by Synapticad.
59 
// Their support is greatly appreciated.
60 
//
61 
// NOTE:  This module watches the PCI bus and gives commentary about what
62 
//        it sees.
63 
//        I hope that this can get a parameter which says whether to put
64 
//        its log in a file, on the terminal, or both.
65 
//
66 
// TO DO: create code to act on MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
67 
//
68 
//===========================================================================
69 
 
70 
// Note that master aborts are the norm on Special Cycles!
71 
 
72 35 mihad 
// synopsys translate_off
73 
`include "timescale.v"
74 
// synopsys translate_on
75 
//`timescale 1ns/10ps
76 15 mihad 
 
77 
module pci_bus_monitor (
78 
  pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
79 
  pci_ext_frame_l, pci_ext_irdy_l,
80 
  pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
81 
  pci_ext_perr_l, pci_ext_serr_l,
82 
  pci_real_req_l, pci_real_gnt_l,
83 
  pci_ext_req_l, pci_ext_gnt_l,
84 
  test_error_event, test_observe_r_oe_sigs,
85 
  test_observe_0_oe_sigs, test_observe_1_oe_sigs,
86 
  test_observe_2_oe_sigs, test_observe_3_oe_sigs,
87 
  pci_ext_reset_l, pci_ext_clk,
88 
  log_file_desc
89 
);
90 
 
91 
`include "pci_blue_options.vh"
92 
`include "pci_blue_constants.vh"
93 
 
94 
  input  [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
95 
  input  [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
96 
  input   pci_ext_par;
97 
  input   pci_ext_frame_l, pci_ext_irdy_l;
98 
  input   pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
99 
  input   pci_ext_perr_l, pci_ext_serr_l;
100 
  input   pci_real_req_l, pci_real_gnt_l;
101 
  input  [3:0] pci_ext_req_l;
102 
  input  [3:0] pci_ext_gnt_l;
103 
  output  test_error_event;
104 
  input  [5:0] test_observe_r_oe_sigs;
105 
  input  [5:0] test_observe_0_oe_sigs;
106 
  input  [5:0] test_observe_1_oe_sigs;
107 
  input  [5:0] test_observe_2_oe_sigs;
108 
  input  [5:0] test_observe_3_oe_sigs;
109 
 
110 
  input   pci_ext_reset_l, pci_ext_clk;
111 
 
112 
  input [31:0] log_file_desc ;
113 
// Make temporary Bip every time an error is detected
114 
  reg     test_error_event;
115 
  initial test_error_event <= 1'bZ;
116 
  reg     error_detected;
117 
  initial error_detected <= 1'b0;
118 
  always @(error_detected)
119 
  begin
120 
    test_error_event <= 1'b0;
121 
    #2;
122 
    test_error_event <= 1'bZ;
123 
  end
124 
 
125 
// watch for the PCI Clock going X
126 
  always @(pci_ext_clk)
127 
  begin
128 
    if (($time > 0) && ((pci_ext_clk ^ pci_ext_clk) === 1'bx))
129 
    begin
130 
      $display ("*** monitor - PCI External Clock invalid 'h%x, at %t",
131 
                  pci_ext_clk, $time);
132 
      $fdisplay (log_file_desc, "*** monitor - PCI External Clock invalid 'h%x, at %t",
133 
                  pci_ext_clk, $time);
134 
      error_detected <= ~error_detected;
135 
    end
136 
    `NO_ELSE;
137 
  end
138 
 
139 
// watch for the Reset signal going X
140 
  always @(pci_ext_reset_l)
141 
  begin
142 
    if (($time > 0) & ((pci_ext_reset_l ^ pci_ext_reset_l) === 1'bx))
143 
    begin
144 
      $display ("*** monitor - PCI External RESET_L invalid 'h%x, at %t",
145 
                  pci_ext_reset_l, $time);
146 
      $fdisplay (log_file_desc, "*** monitor - PCI External RESET_L invalid 'h%x, at %t",
147 
                  pci_ext_reset_l, $time);
148 
      error_detected <= ~error_detected;
149 
    end
150 
    `NO_ELSE;
151 
  end
152 
 
153 
// Make sure all PCI signals are HIGH-Z or Deasserted HIGH as needed
154 
//   when the external PCI bus leaves reset.
155 
// The values of some signals are set by pullups on the PC board
156 
  always @(posedge pci_ext_reset_l)
157 
  begin
158 
  if ($time > 0)
159 
    begin
160 
      if (pci_ext_ad[PCI_BUS_DATA_RANGE:0] !== `PCI_BUS_DATA_Z)
161 
      begin
162 
        $display ("*** monitor - PCI External AD not high-Z 'h%x, at %t",
163 
                    pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
164 
        $fdisplay (log_file_desc, "*** monitor - PCI External AD not high-Z 'h%x, at %t",
165 
                    pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
166 
        error_detected <= ~error_detected;
167 
      end
168 
      `NO_ELSE;
169 
      if (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] !== `PCI_BUS_CBE_Z)
170 
      begin
171 
        $display ("*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
172 
                    pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
173 
        $fdisplay (log_file_desc, "*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
174 
                    pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
175 
        error_detected <= ~error_detected;
176 
      end
177 
      `NO_ELSE;
178 
      if (pci_ext_par !== 1'bz)
179 
      begin
180 
        $display ("*** monitor - PCI External PAR not high-Z 'h%x, at %t",
181 
                    pci_ext_par, $time);
182 
        $fdisplay (log_file_desc, "*** monitor - PCI External PAR not high-Z 'h%x, at %t",
183 
                    pci_ext_par, $time);
184 
        error_detected <= ~error_detected;
185 
      end
186 
      `NO_ELSE;
187 
      if (pci_ext_frame_l !== 1'b1)
188 
      begin
189 
        $display ("*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
190 
                    pci_ext_frame_l, $time);
191 
        $fdisplay (log_file_desc, "*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
192 
                    pci_ext_frame_l, $time);
193 
        error_detected <= ~error_detected;
194 
      end
195 
      `NO_ELSE;
196 
      if (pci_ext_irdy_l !== 1'b1)
197 
      begin
198 
        $display ("*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
199 
                    pci_ext_irdy_l, $time);
200 
        $fdisplay (log_file_desc, "*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
201 
                    pci_ext_irdy_l, $time);
202 
        error_detected <= ~error_detected;
203 
      end
204 
      `NO_ELSE;
205 
      if (pci_ext_devsel_l !== 1'b1)
206 
      begin
207 
        $display ("*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
208 
                    pci_ext_devsel_l, $time);
209 
        $fdisplay (log_file_desc, "*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
210 
                    pci_ext_devsel_l, $time);
211 
        error_detected <= ~error_detected;
212 
      end
213 
      `NO_ELSE;
214 
      if (pci_ext_trdy_l !== 1'b1)
215 
      begin
216 
        $display ("*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
217 
                    pci_ext_trdy_l, $time);
218 
        $fdisplay (log_file_desc, "*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
219 
                    pci_ext_trdy_l, $time);
220 
        error_detected <= ~error_detected;
221 
      end
222 
      `NO_ELSE;
223 
      if (pci_ext_stop_l !== 1'b1)
224 
      begin
225 
        $display ("*** monitor - PCI External STOP_L invalid 'h%x, at %t",
226 
                    pci_ext_stop_l, $time);
227 
        $fdisplay (log_file_desc, "*** monitor - PCI External STOP_L invalid 'h%x, at %t",
228 
                    pci_ext_stop_l, $time);
229 
        error_detected <= ~error_detected;
230 
      end
231 
      `NO_ELSE;
232 
      if (pci_ext_perr_l !== 1'b1)
233 
      begin
234 
        $display ("*** monitor - PCI External PERR_L invalid 'h%x, at %t",
235 
                    pci_ext_perr_l, $time);
236 
        $fdisplay (log_file_desc, "*** monitor - PCI External PERR_L invalid 'h%x, at %t",
237 
                    pci_ext_perr_l, $time);
238 
        error_detected <= ~error_detected;
239 
      end
240 
      `NO_ELSE;
241 
      if (pci_ext_serr_l !== 1'b1)
242 
      begin
243 
        $display ("*** monitor - PCI External SERR_L invalid 'h%x, at %t",
244 
                    pci_ext_serr_l, $time);
245 
        $fdisplay (log_file_desc, "*** monitor - PCI External SERR_L invalid 'h%x, at %t",
246 
                    pci_ext_serr_l, $time);
247 
        error_detected <= ~error_detected;
248 
      end
249 
      `NO_ELSE;
250 
      if (pci_real_req_l !== 1'b1)
251 
      begin
252 
        $display ("*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
253 
                    pci_real_req_l, $time);
254 
        $fdisplay (log_file_desc, "*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
255 
                    pci_real_req_l, $time);
256 
        error_detected <= ~error_detected;
257 
      end
258 
      `NO_ELSE;
259 
      if (pci_real_gnt_l !== 1'b1)
260 
      begin
261 
        $display ("*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
262 
                    pci_real_gnt_l, $time);
263 
        $fdisplay (log_file_desc, "*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
264 
                    pci_real_gnt_l, $time);
265 
        error_detected <= ~error_detected;
266 
      end
267 
      `NO_ELSE;
268 
      if (pci_ext_req_l[3:0] !== 4'hF)
269 
      begin
270 
        $display ("*** monitor - PCI External REQ_L invalid 'h%x, at %t",
271 
                    pci_ext_req_l[3:0], $time);
272 
        $fdisplay (log_file_desc, "*** monitor - PCI External REQ_L invalid 'h%x, at %t",
273 
                    pci_ext_req_l[3:0], $time);
274 
        error_detected <= ~error_detected;
275 
      end
276 
      `NO_ELSE;
277 
      if (pci_ext_gnt_l[3:0] !== 4'hF)
278 
      begin
279 
        $display ("*** monitor - PCI External GNT_L invalid 'h%x, at %t",
280 
                    pci_ext_gnt_l[3:0], $time);
281 
        $fdisplay (log_file_desc, "*** monitor - PCI External GNT_L invalid 'h%x, at %t",
282 
                    pci_ext_gnt_l[3:0], $time);
283 
        error_detected <= ~error_detected;
284 
      end
285 
      `NO_ELSE;
286 
    end
287 
    `NO_ELSE;
288 
  end
289 
 
290 
task Watch_For_X_On_OE_Sigs;
291 
  input  [2:0] signal_source;
292 
  input  [5:0] oe_signals;
293 
  begin
294 
    if ((^oe_signals[5:0]) === 1'bX)
295 
    begin
296 
      if (signal_source[2:0] == `Test_Master_Real)
297 
      begin
298 
        $display ("*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
299 
                    oe_signals[5:0], $time);
300 
        $fdisplay (log_file_desc, "*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
301 
                    oe_signals[5:0], $time);
302 
      end
303 
      else
304 
      begin
305 
        $display ("*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
306 
                    signal_source[2:0], oe_signals[5:0], $time);
307 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
308 
                    signal_source[2:0], oe_signals[5:0], $time);
309 
        error_detected <= ~error_detected;
310 
      end
311 
    end
312 
    `NO_ELSE;
313 
  end
314 
endtask
315 
 
316 
task Watch_For_Simultaneous_Drive_Of_OE_Sigs;
317 
  input  [2:0] signal_source_0;
318 
  input  [2:0] signal_source_1;
319 
  input  [5:0] oe_signals_0;
320 
  input  [5:0] oe_signals_1;
321 
  begin
322 
    if ((oe_signals_0 & oe_signals_1) !== 6'h00)
323 
    begin
324 
      if (signal_source_0[2:0] == `Test_Master_Real)
325 
      begin
326 
        $display ("*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
327 
                    signal_source_1[2:0], oe_signals_0[5:0],
328 
                    oe_signals_1[5:0], $time);
329 
        $fdisplay (log_file_desc, "*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
330 
                    signal_source_1[2:0], oe_signals_0[5:0],
331 
                    oe_signals_1[5:0], $time);
332 
      end
333 
      else if (signal_source_1[2:0] == `Test_Master_Real)
334 
      begin
335 
        $display ("*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
336 
                    signal_source_0[2:0], oe_signals_0[5:0],
337 
                    oe_signals_1[5:0], $time);
338 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
339 
                    signal_source_0[2:0], oe_signals_0[5:0],
340 
                    oe_signals_1[5:0], $time);
341 
      end
342 
      else
343 
      begin
344 
        $display ("*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
345 
                    signal_source_0[2:0], signal_source_1[1:0],
346 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
347 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
348 
                    signal_source_0[2:0], signal_source_1[1:0],
349 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
350 
      end
351 
      error_detected <= ~error_detected;
352 
    end
353 
    `NO_ELSE;
354 
  end
355 
endtask
356 
 
357 
task Watch_For_Deassert_Before_Tristate ;
358 
    input [2:0] signal_source ;
359 
    input [5:0] prev_oe_sigs ;
360 
    input [5:0] current_oe_sigs ;
361 
    input       prev_perr ;
362 
    input       prev_frame ;
363 
    input       prev_irdy ;
364 
    input       prev_trdy ;
365 
    input       prev_stop ;
366 
    input       prev_devsel ;
367 
    reg         do_error ;
368 
begin
369 
    do_error = 0 ;
370 
    if ( prev_oe_sigs[0] && !current_oe_sigs[0] && prev_perr )
371 
    begin
372 
        do_error = 1 ;
373 
        if ( signal_source == `Test_Master_Real )
374 
        begin
375 
            $display("*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
376 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
377 
        end
378 
        else
379 
        begin
380 
            $display("*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
381 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
382 
        end
383 
    end
384 
 
385 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_stop )
386 
    begin
387 
        do_error = 1 ;
388 
        if ( signal_source == `Test_Master_Real )
389 
        begin
390 
            $display("*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
391 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
392 
        end
393 
        else
394 
        begin
395 
            $display("*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
396 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
397 
        end
398 
    end
399 
 
400 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_trdy )
401 
    begin
402 
        do_error = 1 ;
403 
        if ( signal_source == `Test_Master_Real )
404 
        begin
405 
            $display("*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
406 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
407 
        end
408 
        else
409 
        begin
410 
            $display("*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
411 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
412 
        end
413 
    end
414 
 
415 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_devsel )
416 
    begin
417 
        do_error = 1 ;
418 
        if ( signal_source == `Test_Master_Real )
419 
        begin
420 
            $display("*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
421 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
422 
        end
423 
        else
424 
        begin
425 
            $display("*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
426 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
427 
        end
428 
    end
429 
 
430 
    if ( prev_oe_sigs[4] && !current_oe_sigs[4] && prev_irdy )
431 
    begin
432 
        do_error = 1 ;
433 
        if ( signal_source == `Test_Master_Real )
434 
        begin
435 
            $display("*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
436 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
437 
        end
438 
        else
439 
        begin
440 
            $display("*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
441 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
442 
        end
443 
    end
444 
 
445 
    if ( prev_oe_sigs[5] && !current_oe_sigs[5] && prev_frame )
446 
    begin
447 
        do_error = 1 ;
448 
        if ( signal_source == `Test_Master_Real )
449 
        begin
450 
            $display("*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
451 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
452 
        end
453 
        else
454 
        begin
455 
            $display("*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
456 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
457 
        end
458 
    end
459 
 
460 
    if ( do_error )
461 
        error_detected <= ~error_detected ;
462 
end
463 
endtask
464 
 
465 
task Watch_For_Back_To_Back_Drive_Of_OE_Sigs;
466 
  input  [2:0] signal_source_0;
467 
  input  [2:0] signal_source_1;
468 
  input  [5:0] oe_signals_0;
469 
  input  [5:0] oe_signals_1;
470 
  begin
471 
    if ((oe_signals_0 & oe_signals_1) !== 6'h00)
472 
    begin
473 
      if (signal_source_0[2:0] == `Test_Master_Real)
474 
      begin
475 
        $display ("*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
476 
                    signal_source_1[2:0], oe_signals_0[5:0],
477 
                    oe_signals_1[5:0], $time);
478 
        $fdisplay (log_file_desc, "*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
479 
                    signal_source_1[2:0], oe_signals_0[5:0],
480 
                    oe_signals_1[5:0], $time);
481 
      end
482 
      else if (signal_source_1[2:0] == `Test_Master_Real)
483 
      begin
484 
        $display ("*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
485 
                    signal_source_0[2:0], oe_signals_0[5:0],
486 
                    oe_signals_1[5:0], $time);
487 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
488 
                    signal_source_0[2:0], oe_signals_0[5:0],
489 
                    oe_signals_1[5:0], $time);
490 
      end
491 
      else
492 
      begin
493 
        $display ("*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
494 
                    signal_source_0[2:0], signal_source_1[1:0],
495 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
496 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
497 
                    signal_source_0[2:0], signal_source_1[1:0],
498 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
499 
      end
500 
      error_detected <= ~error_detected;
501 
    end
502 
    `NO_ELSE;
503 
  end
504 
endtask
505 
 
506 
// watch for PCI devices simultaneously driving PCI wires
507 
// OE Observation signals are
508 
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
509 
// Unused ports should be wired to 0
510 
  reg    [5:0] prev_real_oe_sigs;
511 
  reg    [5:0] prev_test_0_oe_sigs;
512 
  reg    [5:0] prev_test_1_oe_sigs;
513 
  reg    [5:0] prev_test_2_oe_sigs;
514 
  reg    [5:0] prev_test_3_oe_sigs;
515 
 
516 
  // Make Asserted HIGH signals to prevent (cause?) confusion
517 
  wire    frame_now =  ~pci_ext_frame_l;
518 
  wire    irdy_now =   ~pci_ext_irdy_l;
519 
  wire    devsel_now = ~pci_ext_devsel_l;
520 
  wire    trdy_now =   ~pci_ext_trdy_l;
521 
  wire    stop_now =   ~pci_ext_stop_l;
522 
  wire    perr_now =   ~pci_ext_perr_l;
523 
// Delay PCI bus signals, used by several tests below.
524 
// Detect Address Phases on the bus.
525 
// Ignore Dual Access Cycle, as mentioned in the PCI Local Bus Spec
526 
// Revision 2.2 section 3.1.1.
527 
  reg    [4:0] grant_prev;
528 
  reg    [PCI_BUS_DATA_RANGE:0] ad_prev;
529 
  reg    [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
530 
  reg     frame_prev, irdy_prev, devsel_prev, trdy_prev, stop_prev, perr_prev;
531 
  reg     address_phase_prev, read_operation_prev;
532 
 
533 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
534 
  begin
535 
    if (pci_ext_reset_l == 1'b0)
536 
    begin
537 
      prev_real_oe_sigs <= 6'h00;
538 
      prev_test_0_oe_sigs <= 6'h00;
539 
      prev_test_1_oe_sigs <= 6'h00;
540 
      prev_test_2_oe_sigs <= 6'h00;
541 
      prev_test_3_oe_sigs <= 6'h00;
542 
    end
543 
    else
544 
    begin
545 
      prev_real_oe_sigs <= test_observe_r_oe_sigs[5:0];
546 
      prev_test_0_oe_sigs <= test_observe_0_oe_sigs[5:0];
547 
      prev_test_1_oe_sigs <= test_observe_1_oe_sigs[5:0];
548 
      prev_test_2_oe_sigs <= test_observe_2_oe_sigs[5:0];
549 
      prev_test_3_oe_sigs <= test_observe_3_oe_sigs[5:0];
550 
    end
551 
  end
552 
 
553 
  always @(posedge pci_ext_clk)
554 
  begin
555 
    if (($time > 0) & (pci_ext_reset_l == 1'b1))
556 
    begin
557 
      Watch_For_X_On_OE_Sigs (`Test_Master_Real, test_observe_r_oe_sigs[5:0]);
558 
      Watch_For_X_On_OE_Sigs (3'h0, test_observe_0_oe_sigs[5:0]);
559 
      Watch_For_X_On_OE_Sigs (3'h1, test_observe_1_oe_sigs[5:0]);
560 
      Watch_For_X_On_OE_Sigs (3'h2, test_observe_2_oe_sigs[5:0]);
561 
      Watch_For_X_On_OE_Sigs (3'h3, test_observe_3_oe_sigs[5:0]);
562 
 
563 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
564 
                     test_observe_r_oe_sigs[5:0], test_observe_0_oe_sigs[5:0]);
565 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
566 
                     test_observe_r_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
567 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
568 
                     test_observe_r_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
569 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
570 
                     test_observe_r_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
571 
 
572 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h1,
573 
                     test_observe_0_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
574 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h2,
575 
                     test_observe_0_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
576 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h3,
577 
                     test_observe_0_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
578 
 
579 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h2,
580 
                     test_observe_1_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
581 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h3,
582 
                     test_observe_1_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
583 
 
584 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h2, 3'h3,
585 
                     test_observe_2_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
586 
 
587 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
588 
                     test_observe_r_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
589 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
590 
                     test_observe_r_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
591 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
592 
                     test_observe_r_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
593 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
594 
                     test_observe_r_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
595 
 
596 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, `Test_Master_Real,
597 
                     test_observe_0_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
598 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h1,
599 
                     test_observe_0_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
600 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h2,
601 
                     test_observe_0_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
602 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h3,
603 
                     test_observe_0_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
604 
 
605 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h0,
606 
                     test_observe_1_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
607 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, `Test_Master_Real,
608 
                     test_observe_1_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
609 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h2,
610 
                     test_observe_1_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
611 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h3,
612 
                     test_observe_1_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
613 
 
614 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h0,
615 
                     test_observe_2_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
616 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h1,
617 
                     test_observe_2_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
618 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, `Test_Master_Real,
619 
                     test_observe_2_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
620 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h3,
621 
                     test_observe_2_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
622 
 
623 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h0,
624 
                     test_observe_3_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
625 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h1,
626 
                     test_observe_3_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
627 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h2,
628 
                     test_observe_3_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
629 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, `Test_Master_Real,
630 
                     test_observe_3_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
631 
 
632 
      Watch_For_Deassert_Before_Tristate(`Test_Master_Real, prev_real_oe_sigs, test_observe_r_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
633 
      Watch_For_Deassert_Before_Tristate(3'h0, prev_test_0_oe_sigs, test_observe_0_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
634 
      Watch_For_Deassert_Before_Tristate(3'h1, prev_test_1_oe_sigs, test_observe_1_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
635 
      Watch_For_Deassert_Before_Tristate(3'h2, prev_test_2_oe_sigs, test_observe_2_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
636 
      Watch_For_Deassert_Before_Tristate(3'h3, prev_test_3_oe_sigs, test_observe_3_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
637 
 
638 
    end
639 
    `NO_ELSE;
640 
  end
641 
 
642 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
643 
  begin
644 
    if (pci_ext_reset_l == 1'b0)
645 
    begin
646 
      grant_prev <= 5'h00;
647 
      ad_prev[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_X;
648 
      cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_X;
649 
      frame_prev <= 1'b0;
650 
      irdy_prev <= 1'b0;
651 
      devsel_prev <= 1'b0;
652 
      trdy_prev <= 1'b0;
653 
      stop_prev <= 1'b0;
654 
      address_phase_prev <= 1'b0;
655 
      read_operation_prev <= 1'b0;
656 
    end
657 
    else
658 
    begin
659 
      grant_prev <= {pci_ext_gnt_l[3:0], pci_real_gnt_l};
660 
      ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
661 
      cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
662 
      frame_prev <= frame_now;
663 
      irdy_prev <= irdy_now;
664 
      devsel_prev <= devsel_now;
665 
      trdy_prev <= trdy_now;
666 
      stop_prev <= stop_now;
667 
      perr_prev <= perr_now ;
668 
 
669 
      if (frame_now & ~frame_prev
670 
                && (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] != PCI_COMMAND_DUAL_ADDRESS_CYCLE))
671 
      begin
672 
        address_phase_prev <= 1'b1;
673 
        read_operation_prev <= ~pci_ext_cbe_l[0];  // reads have LSB == 0;
674 
      end
675 
      else
676 
      begin
677 
        address_phase_prev <= 1'b0;
678 
        read_operation_prev <= read_operation_prev;
679 
      end
680 
    end
681 
  end
682 
 
683 
// Track the behavior of the PCI Arbiter.  Rules:
684 
// 1) No grant during reset
685 
// 2) At most 1 grant at any time
686 
// 3) One non-grant cycle on any grant transition when the bus is idle
687 
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
688 
  always @(posedge pci_ext_clk)
689 
  begin
690 
    if ($time > 0)
691 
    begin
692 
      if ((^{pci_ext_gnt_l[3:0], pci_real_gnt_l}) === 1'bX)
693 
      begin
694 
        $display ("*** monitor - PCI GNT_L unknown 'h%x, at %t",
695 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
696 
        $fdisplay (log_file_desc, "*** monitor - PCI GNT_L unknown 'h%x, at %t",
697 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
698 
        error_detected <= ~error_detected;
699 
      end
700 
      `NO_ELSE;
701 
      if ((pci_ext_reset_l == 1'b0)
702 
           && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F))
703 
      begin
704 
        $display ("*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
705 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
706 
        $fdisplay (log_file_desc, "*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
707 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
708 
        error_detected <= ~error_detected;
709 
      end
710 
      `NO_ELSE;
711 
      if (   (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[2])
712 
          || (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[1])
713 
          || (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[0])
714 
          || (~pci_ext_gnt_l[3] & ~pci_real_gnt_l)
715 
          || (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[1])
716 
          || (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[0])
717 
          || (~pci_ext_gnt_l[2] & ~pci_real_gnt_l)
718 
          || (~pci_ext_gnt_l[1] & ~pci_ext_gnt_l[0])
719 
          || (~pci_ext_gnt_l[1] & ~pci_real_gnt_l)
720 
          || (~pci_ext_gnt_l[0] & ~pci_real_gnt_l) )
721 
      begin
722 
        $display ("*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
723 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
724 
        $fdisplay (log_file_desc, "*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
725 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
726 
        error_detected <= ~error_detected;
727 
      end
728 
      `NO_ELSE;
729 
      if  (  (pci_ext_reset_l == 1'b1)
730 
          && (~frame_prev & ~irdy_prev)  // bus idle
731 
          && (grant_prev != 5'h1F) && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F)
732 
          && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != grant_prev))
733 
      begin
734 
        $display ("*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
735 
                    grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
736 
        $fdisplay (log_file_desc, "*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
737 
                    grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
738 
        error_detected <= ~error_detected;
739 
      end
740 
      `NO_ELSE;
741 
    end
742 
    `NO_ELSE;
743 
  end
744 
 
745 
// Classify bus activity and notice slow or dead devices.
746 
// See the PCI Local Bus Spec Revision 2.2 section 3.5
747 
  reg     master_activity_seen, target_activity_seen, target_subsequently_seen;
748 
  reg    [2:0] master_initial_latency_counter;
749 
  reg    [3:0] target_initial_latency_counter;
750 
  reg    [2:0] target_subsequent_latency_counter;
751 
  reg    [3:0] master_abort_timer;
752 
  reg     master_abort;
753 
 
754 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
755 
  begin
756 
    if (pci_ext_reset_l == 1'b0)
757 
    begin
758 
      master_activity_seen <= 1'b0;
759 
      master_initial_latency_counter <= 3'h0;
760 
      target_activity_seen <= 1'b0;
761 
      target_initial_latency_counter <= 4'h0;
762 
      target_subsequently_seen <= 1'b0;
763 
      target_subsequent_latency_counter <= 3'h0;
764 
      master_abort_timer <= 4'h0;
765 
      master_abort <= 1'b0;
766 
    end
767 
    else
768 
    begin
769 
      if ((address_phase_prev) | (~frame_prev & ~irdy_prev))  // address or idle
770 
      begin
771 
        master_abort_timer <= 4'h0;
772 
        master_abort <= 1'b0;
773 
        master_activity_seen <= 1'b0;
774 
        master_initial_latency_counter <= 3'h0;
775 
        target_activity_seen <= 1'b0;
776 
        target_initial_latency_counter <= 4'h0;
777 
        target_subsequently_seen <= 1'b0;
778 
        target_subsequent_latency_counter <= 3'h0;
779 
      end
780 
      else
781 
      begin
782 
// NOTE WORKING not debugged yet.
783 
        master_initial_latency_counter <= master_initial_latency_counter + 3'h1;
784 
        master_activity_seen <= master_activity_seen | irdy_now;
785 
        if ((master_initial_latency_counter == 3'h7) & ~master_activity_seen)
786 
        begin
787 
          $display ("*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
788 
                    $time);
789 
          $fdisplay (log_file_desc, "*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
790 
                    $time);
791 
          error_detected <= ~error_detected;
792 
          master_activity_seen <= 1'b1;
793 
        end
794 
        `NO_ELSE;
795 
 
796 
        target_initial_latency_counter <= target_initial_latency_counter
797 
                              + (devsel_now ? 4'h1 : 4'h0);
798 
        target_activity_seen <= target_activity_seen | trdy_now;
799 
        if ((target_initial_latency_counter == 4'hF) & ~target_activity_seen)
800 
        begin
801 
          $display ("*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
802 
                    $time);
803 
          $fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
804 
                    $time);
805 
          error_detected <= ~error_detected;
806 
          target_activity_seen <= 1'b1;
807 
        end
808 
        `NO_ELSE;
809 
 
810 
// NOTE This only detects Target misbehavior on the FIRST subsequent transfer!!!
811 
        target_subsequent_latency_counter <= target_subsequent_latency_counter
812 
                              + (target_activity_seen ? 3'h1 : 3'h0);
813 
        target_subsequently_seen <= target_subsequently_seen
814 
                                  | (target_activity_seen & trdy_now);
815 
        if ((target_subsequent_latency_counter == 3'h7) & ~target_subsequently_seen)
816 
        begin
817 
          $display ("*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
818 
                    $time);
819 
          $fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
820 
                    $time);
821 
          error_detected <= ~error_detected;
822 
          target_subsequently_seen <= 1'b1;
823 
        end
824 
        `NO_ELSE;
825 
 
826 
        master_abort_timer <= master_abort_timer + 4'h1;
827 
        master_abort <= (master_abort_timer >= 4'h2) ? 1'b1 : master_abort;
828 
      end
829 
    end
830 
  end
831 
 
832 
// Track the parity bit status on the bus.  The rules are:
833 
// 1) parity has to be correct whenever FRAME is asserted to be a valid address
834 
// 2) parity has to be correct whenever IRDY is asserted on writes
835 
// 3) parity has to be correct whenever TRDY is asserted on reads
836 
// parity covers the ad bus, and the cbe wires.  The PCI bus is even parity.
837 
// The number of bits set to 1 in AD plus CBE plus PAR is an EVEN number.
838 
// This code will notice an error, but will only complain if the PERR and SERR
839 
// bits don't match,
840 
  reg     prev_calculated_ad_cbe_parity;
841 
  reg     prev_prev_calculated_ad_cbe_parity, read_operation_prev_prev;
842 
  reg     prev_prev_devsel, prev_prev_trdy, prev_prev_irdy, prev_pci_ext_par;
843 
  reg     ad_prev_address_phase;
844 
  reg    [PCI_BUS_DATA_RANGE:0] ad_prev_prev;
845 
  reg    [PCI_BUS_CBE_RANGE:0] cbe_l_prev_prev;
846 
  always @(posedge pci_ext_clk)
847 
  begin
848 
// calculate 1 if an odd number of bits is set, 0 if an even number is set
849 
    prev_calculated_ad_cbe_parity <= (^pci_ext_ad[PCI_BUS_DATA_RANGE:0])
850 
                                   ^ (^pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0]);
851 
    prev_prev_calculated_ad_cbe_parity <= prev_calculated_ad_cbe_parity;
852 
    read_operation_prev_prev <= read_operation_prev;
853 
    ad_prev_address_phase <= address_phase_prev;
854 
    prev_prev_devsel <= devsel_prev;
855 
    prev_prev_trdy <= trdy_prev;
856 
    prev_prev_irdy <= irdy_prev;
857 
    prev_pci_ext_par <= pci_ext_par;
858 
    ad_prev_prev[PCI_BUS_DATA_RANGE:0] <= ad_prev[PCI_BUS_DATA_RANGE:0];
859 
    cbe_l_prev_prev[PCI_BUS_CBE_RANGE:0] <= cbe_l_prev[PCI_BUS_CBE_RANGE:0];
860 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
861 
    begin
862 
      if (ad_prev_address_phase)
863 
      begin
864 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
865 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
866 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_serr_l))
867 
        begin
868 
          $display ("*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
869 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
870 
          $fdisplay (log_file_desc, "*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
871 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
872 
          error_detected <= ~error_detected;
873 
        end
874 
        `NO_ELSE;
875 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
876 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
877 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_serr_l))
878 
        begin
879 
          $display ("*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
880 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
881 
          $fdisplay (log_file_desc, "*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
882 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
883 
          error_detected <= ~error_detected;
884 
        end
885 
        `NO_ELSE;
886 
      end
887 
      `NO_ELSE;
888 
      if (read_operation_prev_prev & prev_prev_trdy)
889 
      begin
890 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
891 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
892 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
893 
        begin
894 
          $display ("*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
895 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
896 
          $fdisplay (log_file_desc, "*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
897 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
898 
          error_detected <= ~error_detected;
899 
        end
900 
        `NO_ELSE;
901 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
902 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
903 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
904 
        begin
905 
          $display ("*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
906 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
907 
          $fdisplay (log_file_desc, "*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
908 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
909 
          error_detected <= ~error_detected;
910 
        end
911 
        `NO_ELSE;
912 
      end
913 
      `NO_ELSE;
914 
      if (~read_operation_prev_prev & prev_prev_irdy & prev_prev_devsel)
915 
      begin
916 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
917 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
918 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
919 
        begin
920 
          $display ("*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
921 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
922 
          $fdisplay (log_file_desc, "*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
923 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
924 
          error_detected <= ~error_detected;
925 
        end
926 
        `NO_ELSE;
927 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
928 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
929 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
930 
        begin
931 
          $display ("*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
932 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
933 
          $fdisplay (log_file_desc, "*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
934 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
935 
          error_detected <= ~error_detected;
936 
        end
937 
        `NO_ELSE;
938 
      end
939 
      `NO_ELSE;
940 
    end
941 
  end
942 
 
943 
// Verify some of the state transitions observed on the bus.
944 
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
945 
// In general, transition tests should look at one present signal, and
946 
//   a bunch of previous signals.
947 
// In general, simultaneous transition tests should look at two present
948 
//   signals, and a bunch of previous signals.
949 
  always @(posedge pci_ext_clk)
950 
  begin
951 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
952 
    begin
953 
      if (irdy_prev & ~read_operation_prev & ~(trdy_prev | stop_prev) & (pci_ext_ad != ad_prev))
954 
      begin  // Appendix C line 2C
955 
        $display ("*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
956 
                    $time);
957 
        $fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
958 
                    $time);
959 
        error_detected <= ~error_detected;
960 
      end
961 
      `NO_ELSE;
962 
      if (trdy_prev & read_operation_prev & ~irdy_prev & (pci_ext_ad != ad_prev))
963 
      begin  // Appendix C line 2C
964 
        $display ("*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
965 
                    $time);
966 
        $fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
967 
                    $time);
968 
        error_detected <= ~error_detected;
969 
      end
970 
      `NO_ELSE;
971 
      if (frame_prev & (frame_now | irdy_now) & ~address_phase_prev & ~trdy_now
972 
                                                 & (pci_ext_cbe_l != cbe_l_prev))
973 
      begin  // Appendix C line 3B
974 
        $display ("*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
975 
                    $time);
976 
        $fdisplay (log_file_desc, "*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
977 
                    $time);
978 
        error_detected <= ~error_detected;
979 
      end
980 
      `NO_ELSE;
981 
      if (~frame_prev & frame_now & irdy_now)
982 
      begin  // Section 3.3.3.1 rule 2, Appendix C line 7B
983 
        $display ("*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
984 
                    $time);
985 
        $fdisplay (log_file_desc, "*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
986 
                    $time);
987 
        error_detected <= ~error_detected;
988 
      end
989 
      `NO_ELSE;
990 
      if (~irdy_prev & irdy_now & ~frame_prev)
991 
      begin  // Appendix C line ?  not in there!
992 
        $display ("*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
993 
                    $time);
994 
        $fdisplay (log_file_desc, "*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
995 
                    $time);
996 
        error_detected <= ~error_detected;
997 
      end
998 
      `NO_ELSE;
999 
      if (frame_prev & ~frame_now & ~irdy_now)
1000 
      begin  // Section 3.3.3.1 rule 3, Appendix C line 7C
1001 
        $display ("*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
1002 
                    $time);
1003 
        $fdisplay (log_file_desc, "*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
1004 
                    $time);
1005 
        error_detected <= ~error_detected;
1006 
      end
1007 
      `NO_ELSE;
1008 
      if (irdy_prev & ~(trdy_prev | stop_prev | master_abort)
1009 
                                             & (frame_now != frame_prev))
1010 
      begin  // Section 3.3.3.1 rule 4, Appendix C line 7D
1011 
        $display ("*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
1012 
                    $time);
1013 
        $fdisplay (log_file_desc, "*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
1014 
                    $time);
1015 
        error_detected <= ~error_detected;
1016 
      end
1017 
      `NO_ELSE;
1018 
      if (irdy_prev & ~(trdy_prev | stop_prev | master_abort) & ~irdy_now)
1019 
      begin  // Section 3.3.3.1 rule 5, Appendix C line 7E
1020 
        $display ("*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
1021 
                    $time);
1022 
        $fdisplay (log_file_desc, "*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
1023 
                    $time);
1024 
        error_detected <= ~error_detected;
1025 
      end
1026 
      `NO_ELSE;
1027 
// NOTE WORKING section 3.3.3.2.2, Appendix C line 10, REQ must be removed for
1028 
// NOTE WORKING IDLE and one clock on either side of IDLE upon retry or disconnect
1029 
      if (stop_prev & frame_prev & frame_now & ~stop_now)
1030 
      begin  // Section 3.3.3.2.1 rule 3, Appendix C line 12C
1031 
        $display ("*** monitor - STOP Deasserted while FRAME Asserted, at %t",
1032 
                    $time);
1033 
        $fdisplay (log_file_desc, "*** monitor - STOP Deasserted while FRAME Asserted, at %t",
1034 
                    $time);
1035 
        error_detected <= ~error_detected;
1036 
      end
1037 
      `NO_ELSE;
1038 
      if (stop_prev & ~frame_prev & frame_now & stop_now)
1039 
      begin  // Section 3.3.3.2.1 rule 3, Appendix C line 12C, author addition
1040 
        $display ("*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
1041 
                    $time);
1042 
        $fdisplay (log_file_desc, "*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
1043 
                    $time);
1044 
        error_detected <= ~error_detected;
1045 
      end
1046 
      `NO_ELSE;
1047 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (devsel_prev != devsel_now))
1048 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1049 
        $display ("*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
1050 
                    $time);
1051 
        $fdisplay (log_file_desc, "*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
1052 
                    $time);
1053 
        error_detected <= ~error_detected;
1054 
      end
1055 
      `NO_ELSE;
1056 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (trdy_prev != trdy_now))
1057 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1058 
        $display ("*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
1059 
                    $time);
1060 
        $fdisplay (log_file_desc, "*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
1061 
                    $time);
1062 
        error_detected <= ~error_detected;
1063 
      end
1064 
      `NO_ELSE;
1065 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (stop_prev != stop_now))
1066 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1067 
        $display ("*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
1068 
                    $time);
1069 
        $fdisplay (log_file_desc, "*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
1070 
                    $time);
1071 
        error_detected <= ~error_detected;
1072 
      end
1073 
      `NO_ELSE;
1074 
      if (~trdy_prev & trdy_now & ~devsel_now)
1075 
      begin  // Appendix C line 14
1076 
        $display ("*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
1077 
                    $time);
1078 
        $fdisplay (log_file_desc, "*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
1079 
                    $time);
1080 
        error_detected <= ~error_detected;
1081 
      end
1082 
      `NO_ELSE;
1083 
      if (~stop_prev & stop_now & ~(devsel_prev | devsel_now))
1084 
      begin  // Appendix C line 14
1085 
        $display ("*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
1086 
                    $time);
1087 
        $fdisplay (log_file_desc, "*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
1088 
                    $time);
1089 
        error_detected <= ~error_detected;
1090 
      end
1091 
      `NO_ELSE;
1092 
      if (~frame_prev & frame_now & (grant_prev == 5'h1F))
1093 
      begin  // Appendix C line 21
1094 
        $display ("*** monitor - FRAME Asserted when no GNT Asserted, at %t",
1095 
                    $time);
1096 
        $fdisplay (log_file_desc, "*** monitor - FRAME Asserted when no GNT Asserted, at %t",
1097 
                    $time);
1098 
        error_detected <= ~error_detected;
1099 
      end
1100 
      `NO_ELSE;
1101 
      if (devsel_prev & ~devsel_now & frame_prev & ~(stop_now & ~trdy_now))
1102 
      begin  // Appendix C line 30
1103 
        $display ("*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
1104 
                    $time);
1105 
        $fdisplay (log_file_desc, "*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
1106 
                    $time);
1107 
        error_detected <= ~error_detected;
1108 
      end
1109 
      `NO_ELSE;
1110 
    end
1111 
    `NO_ELSE;
1112 
  end
1113 
 
1114 
// Verify some of the state transitions observed on the bus. See the
1115 
// PCI Local Bus Spec Revision 2.2 section 3.2.1, plus Appendix C.
1116 
`ifdef VERBOSE_MONITOR_DEVICE
1117 
  reg     prev_pci_ext_reset_l;
1118 
  always @(pci_ext_reset_l)
1119 
  begin
1120 
    prev_pci_ext_reset_l <= pci_ext_reset_l;
1121 
 
1122 
    if (($time > 0) && (pci_ext_reset_l !== prev_pci_ext_reset_l))
1123 
    begin
1124 
      if (pci_ext_reset_l == 1'b0)
1125 
      begin
1126 
        $display (" monitor - PCI External RESET_L asserted LOW at %t", $time);
1127 
      end
1128 
      `NO_ELSE;
1129 
 
1130 
      if (pci_ext_reset_l == 1'b1)
1131 
      begin
1132 
        $display (" monitor - PCI External RESET_L deasserted HIGH at %t", $time);
1133 
      end
1134 
      `NO_ELSE;
1135 
    end
1136 
  end
1137 
 
1138 
  always @(posedge pci_ext_clk)
1139 
  begin
1140 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
1141 
    begin
1142 
// report a Master Abort, which is not an error
1143 
      if ((irdy_prev & ~irdy_now) & (~trdy_prev & ~stop_prev & master_abort))
1144 
      begin
1145 
        $display (" monitor - IRDY Deasserted due to Master Abort, at %t", $time);
1146 
      end
1147 
      `NO_ELSE;
1148 
 
1149 
      if (~frame_prev & frame_now & irdy_prev & ~irdy_now)
1150 
      begin
1151 
        $display (" Fast Back-to-Back reference with no Idle cycle started at %t",
1152 
                  $time);
1153 
      end
1154 
      `NO_ELSE;
1155 
    end
1156 
    `NO_ELSE;
1157 
  end
1158 
`endif // VERBOSE_MONITOR_DEVICE
1159 
 
1160 
`ifdef VERBOSE_MONITOR_DEVICE
1161 
  always @(posedge pci_ext_clk)
1162 
  begin
1163 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0) && address_phase_prev)
1164 
    begin
1165 
// command list taken from PCI Local Bus Spec Revision 2.2 section 3.1.1.
1166 
      case (cbe_l_prev[PCI_BUS_CBE_RANGE:0])
1167 
      PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
1168 
        $display (" monitor - Interrupt Acknowledge started, AD: 'h%x, CBE: 'h%x, at time %t",
1169 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);,
1170 
      PCI_COMMAND_SPECIAL_CYCLE:
1171 
        $display (" monitor - Special Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
1172 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1173 
      PCI_COMMAND_IO_READ:
1174 
        $display (" monitor - IO Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1175 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1176 
      PCI_COMMAND_IO_WRITE:
1177 
        $display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1178 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1179 
      PCI_COMMAND_RESERVED_READ_4:
1180 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1181 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1182 
      PCI_COMMAND_RESERVED_WRITE_5:
1183 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1184 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1185 
      PCI_COMMAND_MEMORY_READ:
1186 
        $display (" monitor - Memory Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1187 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1188 
      PCI_COMMAND_MEMORY_WRITE:
1189 
        $display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1190 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1191 
      PCI_COMMAND_RESERVED_READ_8:
1192 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1193 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1194 
      PCI_COMMAND_RESERVED_WRITE_9:
1195 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1196 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1197 
      PCI_COMMAND_CONFIG_READ:
1198 
        $display (" monitor - Configuration Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1199 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1200 
      PCI_COMMAND_CONFIG_WRITE:
1201 
        $display (" monitor - Configuration Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1202 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1203 
      PCI_COMMAND_MEMORY_READ_MULTIPLE:
1204 
        $display (" monitor - Memory Read Multiple started, AD: 'h%x, CBE: 'h%x, at time %t",
1205 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1206 
      PCI_COMMAND_DUAL_ADDRESS_CYCLE:
1207 
        $display (" monitor - Dual Address Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
1208 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1209 
      PCI_COMMAND_MEMORY_READ_LINE:
1210 
        $display (" monitor - Memory Read Line started, AD: 'h%x, CBE: 'h%x, at time %t",
1211 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1212 
      PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
1213 
        $display (" monitor - Memory Write and Invalidate started, AD: 'h%x, CBE: 'h%x, at time %t",
1214 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1215 
      default:
1216 
        begin
1217 
          $display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
1218 
                      ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1219 
          $fdisplay (log_file_desc,
1220 
          error_detected <= ~error_detected;
1221 
        end
1222 
      endcase
1223 
    end
1224 
    `NO_ELSE;
1225 
  end
1226 
`endif // VERBOSE_MONITOR_DEVICE
1227 
endmodule
1228 
 

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