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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [pci_bus_monitor.v] - Blame information for rev 82

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1 15 mihad 
//===========================================================================
2 45 mihad 
// $Id: pci_bus_monitor.v,v 1.3 2002-08-13 11:03:51 mihad Exp $
3 15 mihad 
//
4 
// Copyright 2001 Blue Beaver.  All Rights Reserved.
5 
//
6 
// Summary:  Watch the PCI Bus Wires to try to see Protocol Errors.
7 
//           This module also has access to the individual PCI Bus OE
8 
//           signals for each interface (either through extra output
9 
//           ports or through "." notation), and it can see when more
10 
//           than one interface is driving the bus, even if the values
11 
//           are the same.
12 
//           A future version of this module should write out a transcript
13 
//           of the activity seen on the PCI Bus.
14 
//
15 
// This library is free software; you can distribute it and/or modify it
16 
// under the terms of the GNU Lesser General Public License as published
17 
// by the Free Software Foundation; either version 2.1 of the License, or
18 
// (at your option) any later version.
19 
//
20 
// This library is distributed in the hope that it will be useful, but
21 
// WITHOUT ANY WARRANTY; without even the implied warranty of
22 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
23 
// See the GNU Lesser General Public License for more details.
24 
//
25 
// You should have received a copy of the GNU Lesser General Public License
26 
// along with this library.  If not, write to
27 
// Free Software Foundation, Inc.
28 
// 59 Temple Place, Suite 330
29 
// Boston, MA 02111-1307 USA
30 
//
31 
// Author's note about this license:  The intention of the Author and of
32 
// the Gnu Lesser General Public License is that users should be able to
33 
// use this code for any purpose, including combining it with other source
34 
// code, combining it with other logic, translated it into a gate-level
35 
// representation, or projected it into gates in a programmable or
36 
// hardwired chip, as long as the users of the resulting source, compiled
37 
// source, or chip are given the means to get a copy of this source code
38 
// with no new restrictions on redistribution of this source.
39 
//
40 
// If you make changes, even substantial changes, to this code, or use
41 
// substantial parts of this code as an inseparable part of another work
42 
// of authorship, the users of the resulting IP must be given the means
43 
// to get a copy of the modified or combined source code, with no new
44 
// restrictions on redistribution of the resulting source.
45 
//
46 
// Separate parts of the combined source code, compiled code, or chip,
47 
// which are NOT derived from this source code do NOT need to be offered
48 
// to the final user of the chip merely because they are used in
49 
// combination with this code.  Other code is not forced to fall under
50 
// the GNU Lesser General Public License when it is linked to this code.
51 
// The license terms of other source code linked to this code might require
52 
// that it NOT be made available to users.  The GNU Lesser General Public
53 
// License does not prevent this code from being used in such a situation,
54 
// as long as the user of the resulting IP is given the means to get a
55 
// copy of this component of the IP with no new restrictions on
56 
// redistribution of this source.
57 
//
58 
// This code was developed using VeriLogger Pro, by Synapticad.
59 
// Their support is greatly appreciated.
60 
//
61 
// NOTE:  This module watches the PCI bus and gives commentary about what
62 
//        it sees.
63 
//        I hope that this can get a parameter which says whether to put
64 
//        its log in a file, on the terminal, or both.
65 
//
66 
// TO DO: create code to act on MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
67 
//
68 
//===========================================================================
69 
 
70 
// Note that master aborts are the norm on Special Cycles!
71 
 
72 35 mihad 
// synopsys translate_off
73 
`include "timescale.v"
74 
// synopsys translate_on
75 
//`timescale 1ns/10ps
76 15 mihad 
 
77 
module pci_bus_monitor (
78 
  pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
79 
  pci_ext_frame_l, pci_ext_irdy_l,
80 
  pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
81 
  pci_ext_perr_l, pci_ext_serr_l,
82 
  pci_real_req_l, pci_real_gnt_l,
83 
  pci_ext_req_l, pci_ext_gnt_l,
84 
  test_error_event, test_observe_r_oe_sigs,
85 
  test_observe_0_oe_sigs, test_observe_1_oe_sigs,
86 
  test_observe_2_oe_sigs, test_observe_3_oe_sigs,
87 
  pci_ext_reset_l, pci_ext_clk,
88 
  log_file_desc
89 
);
90 
 
91 
`include "pci_blue_options.vh"
92 
`include "pci_blue_constants.vh"
93 
 
94 
  input  [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
95 
  input  [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
96 
  input   pci_ext_par;
97 
  input   pci_ext_frame_l, pci_ext_irdy_l;
98 
  input   pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
99 
  input   pci_ext_perr_l, pci_ext_serr_l;
100 
  input   pci_real_req_l, pci_real_gnt_l;
101 
  input  [3:0] pci_ext_req_l;
102 
  input  [3:0] pci_ext_gnt_l;
103 
  output  test_error_event;
104 
  input  [5:0] test_observe_r_oe_sigs;
105 
  input  [5:0] test_observe_0_oe_sigs;
106 
  input  [5:0] test_observe_1_oe_sigs;
107 
  input  [5:0] test_observe_2_oe_sigs;
108 
  input  [5:0] test_observe_3_oe_sigs;
109 
 
110 
  input   pci_ext_reset_l, pci_ext_clk;
111 
 
112 
  input [31:0] log_file_desc ;
113 
// Make temporary Bip every time an error is detected
114 
  reg     test_error_event;
115 
  initial test_error_event <= 1'bZ;
116 
  reg     error_detected;
117 
  initial error_detected <= 1'b0;
118 
  always @(error_detected)
119 
  begin
120 
    test_error_event <= 1'b0;
121 
    #2;
122 
    test_error_event <= 1'bZ;
123 
  end
124 
 
125 
// watch for the PCI Clock going X
126 
  always @(pci_ext_clk)
127 
  begin
128 
    if (($time > 0) && ((pci_ext_clk ^ pci_ext_clk) === 1'bx))
129 
    begin
130 
      $display ("*** monitor - PCI External Clock invalid 'h%x, at %t",
131 
                  pci_ext_clk, $time);
132 
      $fdisplay (log_file_desc, "*** monitor - PCI External Clock invalid 'h%x, at %t",
133 
                  pci_ext_clk, $time);
134 
      error_detected <= ~error_detected;
135 
    end
136 
    `NO_ELSE;
137 
  end
138 
 
139 
// watch for the Reset signal going X
140 
  always @(pci_ext_reset_l)
141 
  begin
142 
    if (($time > 0) & ((pci_ext_reset_l ^ pci_ext_reset_l) === 1'bx))
143 
    begin
144 
      $display ("*** monitor - PCI External RESET_L invalid 'h%x, at %t",
145 
                  pci_ext_reset_l, $time);
146 
      $fdisplay (log_file_desc, "*** monitor - PCI External RESET_L invalid 'h%x, at %t",
147 
                  pci_ext_reset_l, $time);
148 
      error_detected <= ~error_detected;
149 
    end
150 
    `NO_ELSE;
151 
  end
152 
 
153 
// Make sure all PCI signals are HIGH-Z or Deasserted HIGH as needed
154 
//   when the external PCI bus leaves reset.
155 
// The values of some signals are set by pullups on the PC board
156 
  always @(posedge pci_ext_reset_l)
157 
  begin
158 
  if ($time > 0)
159 
    begin
160 
      if (pci_ext_ad[PCI_BUS_DATA_RANGE:0] !== `PCI_BUS_DATA_Z)
161 
      begin
162 
        $display ("*** monitor - PCI External AD not high-Z 'h%x, at %t",
163 
                    pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
164 
        $fdisplay (log_file_desc, "*** monitor - PCI External AD not high-Z 'h%x, at %t",
165 
                    pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
166 
        error_detected <= ~error_detected;
167 
      end
168 
      `NO_ELSE;
169 
      if (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] !== `PCI_BUS_CBE_Z)
170 
      begin
171 
        $display ("*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
172 
                    pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
173 
        $fdisplay (log_file_desc, "*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
174 
                    pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
175 
        error_detected <= ~error_detected;
176 
      end
177 
      `NO_ELSE;
178 
      if (pci_ext_par !== 1'bz)
179 
      begin
180 
        $display ("*** monitor - PCI External PAR not high-Z 'h%x, at %t",
181 
                    pci_ext_par, $time);
182 
        $fdisplay (log_file_desc, "*** monitor - PCI External PAR not high-Z 'h%x, at %t",
183 
                    pci_ext_par, $time);
184 
        error_detected <= ~error_detected;
185 
      end
186 
      `NO_ELSE;
187 
      if (pci_ext_frame_l !== 1'b1)
188 
      begin
189 
        $display ("*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
190 
                    pci_ext_frame_l, $time);
191 
        $fdisplay (log_file_desc, "*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
192 
                    pci_ext_frame_l, $time);
193 
        error_detected <= ~error_detected;
194 
      end
195 
      `NO_ELSE;
196 
      if (pci_ext_irdy_l !== 1'b1)
197 
      begin
198 
        $display ("*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
199 
                    pci_ext_irdy_l, $time);
200 
        $fdisplay (log_file_desc, "*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
201 
                    pci_ext_irdy_l, $time);
202 
        error_detected <= ~error_detected;
203 
      end
204 
      `NO_ELSE;
205 
      if (pci_ext_devsel_l !== 1'b1)
206 
      begin
207 
        $display ("*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
208 
                    pci_ext_devsel_l, $time);
209 
        $fdisplay (log_file_desc, "*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
210 
                    pci_ext_devsel_l, $time);
211 
        error_detected <= ~error_detected;
212 
      end
213 
      `NO_ELSE;
214 
      if (pci_ext_trdy_l !== 1'b1)
215 
      begin
216 
        $display ("*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
217 
                    pci_ext_trdy_l, $time);
218 
        $fdisplay (log_file_desc, "*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
219 
                    pci_ext_trdy_l, $time);
220 
        error_detected <= ~error_detected;
221 
      end
222 
      `NO_ELSE;
223 
      if (pci_ext_stop_l !== 1'b1)
224 
      begin
225 
        $display ("*** monitor - PCI External STOP_L invalid 'h%x, at %t",
226 
                    pci_ext_stop_l, $time);
227 
        $fdisplay (log_file_desc, "*** monitor - PCI External STOP_L invalid 'h%x, at %t",
228 
                    pci_ext_stop_l, $time);
229 
        error_detected <= ~error_detected;
230 
      end
231 
      `NO_ELSE;
232 
      if (pci_ext_perr_l !== 1'b1)
233 
      begin
234 
        $display ("*** monitor - PCI External PERR_L invalid 'h%x, at %t",
235 
                    pci_ext_perr_l, $time);
236 
        $fdisplay (log_file_desc, "*** monitor - PCI External PERR_L invalid 'h%x, at %t",
237 
                    pci_ext_perr_l, $time);
238 
        error_detected <= ~error_detected;
239 
      end
240 
      `NO_ELSE;
241 
      if (pci_ext_serr_l !== 1'b1)
242 
      begin
243 
        $display ("*** monitor - PCI External SERR_L invalid 'h%x, at %t",
244 
                    pci_ext_serr_l, $time);
245 
        $fdisplay (log_file_desc, "*** monitor - PCI External SERR_L invalid 'h%x, at %t",
246 
                    pci_ext_serr_l, $time);
247 
        error_detected <= ~error_detected;
248 
      end
249 
      `NO_ELSE;
250 
      if (pci_real_req_l !== 1'b1)
251 
      begin
252 
        $display ("*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
253 
                    pci_real_req_l, $time);
254 
        $fdisplay (log_file_desc, "*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
255 
                    pci_real_req_l, $time);
256 
        error_detected <= ~error_detected;
257 
      end
258 
      `NO_ELSE;
259 
      if (pci_real_gnt_l !== 1'b1)
260 
      begin
261 
        $display ("*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
262 
                    pci_real_gnt_l, $time);
263 
        $fdisplay (log_file_desc, "*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
264 
                    pci_real_gnt_l, $time);
265 
        error_detected <= ~error_detected;
266 
      end
267 
      `NO_ELSE;
268 
      if (pci_ext_req_l[3:0] !== 4'hF)
269 
      begin
270 
        $display ("*** monitor - PCI External REQ_L invalid 'h%x, at %t",
271 
                    pci_ext_req_l[3:0], $time);
272 
        $fdisplay (log_file_desc, "*** monitor - PCI External REQ_L invalid 'h%x, at %t",
273 
                    pci_ext_req_l[3:0], $time);
274 
        error_detected <= ~error_detected;
275 
      end
276 
      `NO_ELSE;
277 
      if (pci_ext_gnt_l[3:0] !== 4'hF)
278 
      begin
279 
        $display ("*** monitor - PCI External GNT_L invalid 'h%x, at %t",
280 
                    pci_ext_gnt_l[3:0], $time);
281 
        $fdisplay (log_file_desc, "*** monitor - PCI External GNT_L invalid 'h%x, at %t",
282 
                    pci_ext_gnt_l[3:0], $time);
283 
        error_detected <= ~error_detected;
284 
      end
285 
      `NO_ELSE;
286 
    end
287 
    `NO_ELSE;
288 
  end
289 
 
290 
task Watch_For_X_On_OE_Sigs;
291 
  input  [2:0] signal_source;
292 
  input  [5:0] oe_signals;
293 
  begin
294 
    if ((^oe_signals[5:0]) === 1'bX)
295 
    begin
296 
      if (signal_source[2:0] == `Test_Master_Real)
297 
      begin
298 
        $display ("*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
299 
                    oe_signals[5:0], $time);
300 
        $fdisplay (log_file_desc, "*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
301 
                    oe_signals[5:0], $time);
302 
      end
303 
      else
304 
      begin
305 
        $display ("*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
306 
                    signal_source[2:0], oe_signals[5:0], $time);
307 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
308 
                    signal_source[2:0], oe_signals[5:0], $time);
309 
        error_detected <= ~error_detected;
310 
      end
311 
    end
312 
    `NO_ELSE;
313 
  end
314 
endtask
315 
 
316 
task Watch_For_Simultaneous_Drive_Of_OE_Sigs;
317 
  input  [2:0] signal_source_0;
318 
  input  [2:0] signal_source_1;
319 
  input  [5:0] oe_signals_0;
320 
  input  [5:0] oe_signals_1;
321 
  begin
322 
    if ((oe_signals_0 & oe_signals_1) !== 6'h00)
323 
    begin
324 
      if (signal_source_0[2:0] == `Test_Master_Real)
325 
      begin
326 
        $display ("*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
327 
                    signal_source_1[2:0], oe_signals_0[5:0],
328 
                    oe_signals_1[5:0], $time);
329 
        $fdisplay (log_file_desc, "*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
330 
                    signal_source_1[2:0], oe_signals_0[5:0],
331 
                    oe_signals_1[5:0], $time);
332 
      end
333 
      else if (signal_source_1[2:0] == `Test_Master_Real)
334 
      begin
335 
        $display ("*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
336 
                    signal_source_0[2:0], oe_signals_0[5:0],
337 
                    oe_signals_1[5:0], $time);
338 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
339 
                    signal_source_0[2:0], oe_signals_0[5:0],
340 
                    oe_signals_1[5:0], $time);
341 
      end
342 
      else
343 
      begin
344 
        $display ("*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
345 
                    signal_source_0[2:0], signal_source_1[1:0],
346 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
347 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
348 
                    signal_source_0[2:0], signal_source_1[1:0],
349 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
350 
      end
351 
      error_detected <= ~error_detected;
352 
    end
353 
    `NO_ELSE;
354 
  end
355 
endtask
356 
 
357 
task Watch_For_Deassert_Before_Tristate ;
358 
    input [2:0] signal_source ;
359 
    input [5:0] prev_oe_sigs ;
360 
    input [5:0] current_oe_sigs ;
361 
    input       prev_perr ;
362 
    input       prev_frame ;
363 
    input       prev_irdy ;
364 
    input       prev_trdy ;
365 
    input       prev_stop ;
366 
    input       prev_devsel ;
367 
    reg         do_error ;
368 
begin
369 
    do_error = 0 ;
370 
    if ( prev_oe_sigs[0] && !current_oe_sigs[0] && prev_perr )
371 
    begin
372 
        do_error = 1 ;
373 
        if ( signal_source == `Test_Master_Real )
374 
        begin
375 
            $display("*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
376 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
377 
        end
378 
        else
379 
        begin
380 
            $display("*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
381 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
382 
        end
383 
    end
384 
 
385 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_stop )
386 
    begin
387 
        do_error = 1 ;
388 
        if ( signal_source == `Test_Master_Real )
389 
        begin
390 
            $display("*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
391 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
392 
        end
393 
        else
394 
        begin
395 
            $display("*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
396 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
397 
        end
398 
    end
399 
 
400 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_trdy )
401 
    begin
402 
        do_error = 1 ;
403 
        if ( signal_source == `Test_Master_Real )
404 
        begin
405 
            $display("*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
406 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
407 
        end
408 
        else
409 
        begin
410 
            $display("*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
411 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
412 
        end
413 
    end
414 
 
415 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_devsel )
416 
    begin
417 
        do_error = 1 ;
418 
        if ( signal_source == `Test_Master_Real )
419 
        begin
420 
            $display("*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
421 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
422 
        end
423 
        else
424 
        begin
425 
            $display("*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
426 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
427 
        end
428 
    end
429 
 
430 
    if ( prev_oe_sigs[4] && !current_oe_sigs[4] && prev_irdy )
431 
    begin
432 
        do_error = 1 ;
433 
        if ( signal_source == `Test_Master_Real )
434 
        begin
435 
            $display("*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
436 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
437 
        end
438 
        else
439 
        begin
440 
            $display("*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
441 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
442 
        end
443 
    end
444 
 
445 
    if ( prev_oe_sigs[5] && !current_oe_sigs[5] && prev_frame )
446 
    begin
447 
        do_error = 1 ;
448 
        if ( signal_source == `Test_Master_Real )
449 
        begin
450 
            $display("*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
451 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
452 
        end
453 
        else
454 
        begin
455 
            $display("*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
456 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
457 
        end
458 
    end
459 
 
460 
    if ( do_error )
461 
        error_detected <= ~error_detected ;
462 
end
463 
endtask
464 
 
465 
task Watch_For_Back_To_Back_Drive_Of_OE_Sigs;
466 
  input  [2:0] signal_source_0;
467 
  input  [2:0] signal_source_1;
468 
  input  [5:0] oe_signals_0;
469 
  input  [5:0] oe_signals_1;
470 
  begin
471 
    if ((oe_signals_0 & oe_signals_1) !== 6'h00)
472 
    begin
473 
      if (signal_source_0[2:0] == `Test_Master_Real)
474 
      begin
475 
        $display ("*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
476 
                    signal_source_1[2:0], oe_signals_0[5:0],
477 
                    oe_signals_1[5:0], $time);
478 
        $fdisplay (log_file_desc, "*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
479 
                    signal_source_1[2:0], oe_signals_0[5:0],
480 
                    oe_signals_1[5:0], $time);
481 
      end
482 
      else if (signal_source_1[2:0] == `Test_Master_Real)
483 
      begin
484 
        $display ("*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
485 
                    signal_source_0[2:0], oe_signals_0[5:0],
486 
                    oe_signals_1[5:0], $time);
487 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
488 
                    signal_source_0[2:0], oe_signals_0[5:0],
489 
                    oe_signals_1[5:0], $time);
490 
      end
491 
      else
492 
      begin
493 
        $display ("*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
494 
                    signal_source_0[2:0], signal_source_1[1:0],
495 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
496 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
497 
                    signal_source_0[2:0], signal_source_1[1:0],
498 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
499 
      end
500 
      error_detected <= ~error_detected;
501 
    end
502 
    `NO_ELSE;
503 
  end
504 
endtask
505 
 
506 
// watch for PCI devices simultaneously driving PCI wires
507 
// OE Observation signals are
508 
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
509 
// Unused ports should be wired to 0
510 
  reg    [5:0] prev_real_oe_sigs;
511 
  reg    [5:0] prev_test_0_oe_sigs;
512 
  reg    [5:0] prev_test_1_oe_sigs;
513 
  reg    [5:0] prev_test_2_oe_sigs;
514 
  reg    [5:0] prev_test_3_oe_sigs;
515 
 
516 
  // Make Asserted HIGH signals to prevent (cause?) confusion
517 
  wire    frame_now =  ~pci_ext_frame_l;
518 
  wire    irdy_now =   ~pci_ext_irdy_l;
519 
  wire    devsel_now = ~pci_ext_devsel_l;
520 
  wire    trdy_now =   ~pci_ext_trdy_l;
521 
  wire    stop_now =   ~pci_ext_stop_l;
522 
  wire    perr_now =   ~pci_ext_perr_l;
523 
// Delay PCI bus signals, used by several tests below.
524 
// Detect Address Phases on the bus.
525 
// Ignore Dual Access Cycle, as mentioned in the PCI Local Bus Spec
526 
// Revision 2.2 section 3.1.1.
527 
  reg    [4:0] grant_prev;
528 
  reg    [PCI_BUS_DATA_RANGE:0] ad_prev;
529 
  reg    [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
530 
  reg     frame_prev, irdy_prev, devsel_prev, trdy_prev, stop_prev, perr_prev;
531 
  reg     address_phase_prev, read_operation_prev;
532 
 
533 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
534 
  begin
535 
    if (pci_ext_reset_l == 1'b0)
536 
    begin
537 
      prev_real_oe_sigs <= 6'h00;
538 
      prev_test_0_oe_sigs <= 6'h00;
539 
      prev_test_1_oe_sigs <= 6'h00;
540 
      prev_test_2_oe_sigs <= 6'h00;
541 
      prev_test_3_oe_sigs <= 6'h00;
542 
    end
543 
    else
544 
    begin
545 
      prev_real_oe_sigs <= test_observe_r_oe_sigs[5:0];
546 
      prev_test_0_oe_sigs <= test_observe_0_oe_sigs[5:0];
547 
      prev_test_1_oe_sigs <= test_observe_1_oe_sigs[5:0];
548 
      prev_test_2_oe_sigs <= test_observe_2_oe_sigs[5:0];
549 
      prev_test_3_oe_sigs <= test_observe_3_oe_sigs[5:0];
550 
    end
551 
  end
552 
 
553 
  always @(posedge pci_ext_clk)
554 
  begin
555 
    if (($time > 0) & (pci_ext_reset_l == 1'b1))
556 
    begin
557 
      Watch_For_X_On_OE_Sigs (`Test_Master_Real, test_observe_r_oe_sigs[5:0]);
558 
      Watch_For_X_On_OE_Sigs (3'h0, test_observe_0_oe_sigs[5:0]);
559 
      Watch_For_X_On_OE_Sigs (3'h1, test_observe_1_oe_sigs[5:0]);
560 
      Watch_For_X_On_OE_Sigs (3'h2, test_observe_2_oe_sigs[5:0]);
561 
      Watch_For_X_On_OE_Sigs (3'h3, test_observe_3_oe_sigs[5:0]);
562 
 
563 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
564 
                     test_observe_r_oe_sigs[5:0], test_observe_0_oe_sigs[5:0]);
565 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
566 
                     test_observe_r_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
567 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
568 
                     test_observe_r_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
569 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
570 
                     test_observe_r_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
571 
 
572 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h1,
573 
                     test_observe_0_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
574 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h2,
575 
                     test_observe_0_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
576 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h3,
577 
                     test_observe_0_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
578 
 
579 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h2,
580 
                     test_observe_1_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
581 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h3,
582 
                     test_observe_1_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
583 
 
584 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h2, 3'h3,
585 
                     test_observe_2_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
586 
 
587 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
588 
                     test_observe_r_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
589 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
590 
                     test_observe_r_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
591 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
592 
                     test_observe_r_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
593 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
594 
                     test_observe_r_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
595 
 
596 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, `Test_Master_Real,
597 
                     test_observe_0_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
598 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h1,
599 
                     test_observe_0_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
600 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h2,
601 
                     test_observe_0_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
602 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h3,
603 
                     test_observe_0_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
604 
 
605 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h0,
606 
                     test_observe_1_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
607 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, `Test_Master_Real,
608 
                     test_observe_1_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
609 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h2,
610 
                     test_observe_1_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
611 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h3,
612 
                     test_observe_1_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
613 
 
614 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h0,
615 
                     test_observe_2_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
616 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h1,
617 
                     test_observe_2_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
618 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, `Test_Master_Real,
619 
                     test_observe_2_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
620 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h3,
621 
                     test_observe_2_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
622 
 
623 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h0,
624 
                     test_observe_3_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
625 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h1,
626 
                     test_observe_3_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
627 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h2,
628 
                     test_observe_3_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
629 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, `Test_Master_Real,
630 
                     test_observe_3_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
631 
 
632 
      Watch_For_Deassert_Before_Tristate(`Test_Master_Real, prev_real_oe_sigs, test_observe_r_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
633 
      Watch_For_Deassert_Before_Tristate(3'h0, prev_test_0_oe_sigs, test_observe_0_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
634 
      Watch_For_Deassert_Before_Tristate(3'h1, prev_test_1_oe_sigs, test_observe_1_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
635 
      Watch_For_Deassert_Before_Tristate(3'h2, prev_test_2_oe_sigs, test_observe_2_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
636 
      Watch_For_Deassert_Before_Tristate(3'h3, prev_test_3_oe_sigs, test_observe_3_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
637 
 
638 
    end
639 
    `NO_ELSE;
640 
  end
641 
 
642 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
643 
  begin
644 
    if (pci_ext_reset_l == 1'b0)
645 
    begin
646 
      grant_prev <= 5'h00;
647 
      ad_prev[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_X;
648 
      cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_X;
649 
      frame_prev <= 1'b0;
650 
      irdy_prev <= 1'b0;
651 
      devsel_prev <= 1'b0;
652 
      trdy_prev <= 1'b0;
653 
      stop_prev <= 1'b0;
654 
      address_phase_prev <= 1'b0;
655 
      read_operation_prev <= 1'b0;
656 
    end
657 
    else
658 
    begin
659 
      grant_prev <= {pci_ext_gnt_l[3:0], pci_real_gnt_l};
660 
      ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
661 
      cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
662 
      frame_prev <= frame_now;
663 
      irdy_prev <= irdy_now;
664 
      devsel_prev <= devsel_now;
665 
      trdy_prev <= trdy_now;
666 
      stop_prev <= stop_now;
667 
      perr_prev <= perr_now ;
668 
 
669 45 mihad 
      if (frame_now & ~frame_prev)
670 15 mihad 
      begin
671 
        address_phase_prev <= 1'b1;
672 
        read_operation_prev <= ~pci_ext_cbe_l[0];  // reads have LSB == 0;
673 
      end
674 45 mihad 
      else if(address_phase_prev && (cbe_l_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_DUAL_ADDRESS_CYCLE))
675 
      begin
676 
        address_phase_prev <= 1'b1;
677 
        read_operation_prev <= ~pci_ext_cbe_l[0];  // reads have LSB == 0;
678 
      end
679 15 mihad 
      else
680 
      begin
681 
        address_phase_prev <= 1'b0;
682 
        read_operation_prev <= read_operation_prev;
683 
      end
684 
    end
685 
  end
686 
 
687 
// Track the behavior of the PCI Arbiter.  Rules:
688 
// 1) No grant during reset
689 
// 2) At most 1 grant at any time
690 
// 3) One non-grant cycle on any grant transition when the bus is idle
691 
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
692 
  always @(posedge pci_ext_clk)
693 
  begin
694 
    if ($time > 0)
695 
    begin
696 
      if ((^{pci_ext_gnt_l[3:0], pci_real_gnt_l}) === 1'bX)
697 
      begin
698 
        $display ("*** monitor - PCI GNT_L unknown 'h%x, at %t",
699 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
700 
        $fdisplay (log_file_desc, "*** monitor - PCI GNT_L unknown 'h%x, at %t",
701 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
702 
        error_detected <= ~error_detected;
703 
      end
704 
      `NO_ELSE;
705 
      if ((pci_ext_reset_l == 1'b0)
706 
           && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F))
707 
      begin
708 
        $display ("*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
709 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
710 
        $fdisplay (log_file_desc, "*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
711 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
712 
        error_detected <= ~error_detected;
713 
      end
714 
      `NO_ELSE;
715 
      if (   (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[2])
716 
          || (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[1])
717 
          || (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[0])
718 
          || (~pci_ext_gnt_l[3] & ~pci_real_gnt_l)
719 
          || (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[1])
720 
          || (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[0])
721 
          || (~pci_ext_gnt_l[2] & ~pci_real_gnt_l)
722 
          || (~pci_ext_gnt_l[1] & ~pci_ext_gnt_l[0])
723 
          || (~pci_ext_gnt_l[1] & ~pci_real_gnt_l)
724 
          || (~pci_ext_gnt_l[0] & ~pci_real_gnt_l) )
725 
      begin
726 
        $display ("*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
727 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
728 
        $fdisplay (log_file_desc, "*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
729 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
730 
        error_detected <= ~error_detected;
731 
      end
732 
      `NO_ELSE;
733 
      if  (  (pci_ext_reset_l == 1'b1)
734 
          && (~frame_prev & ~irdy_prev)  // bus idle
735 
          && (grant_prev != 5'h1F) && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F)
736 
          && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != grant_prev))
737 
      begin
738 
        $display ("*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
739 
                    grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
740 
        $fdisplay (log_file_desc, "*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
741 
                    grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
742 
        error_detected <= ~error_detected;
743 
      end
744 
      `NO_ELSE;
745 
    end
746 
    `NO_ELSE;
747 
  end
748 
 
749 
// Classify bus activity and notice slow or dead devices.
750 
// See the PCI Local Bus Spec Revision 2.2 section 3.5
751 
  reg     master_activity_seen, target_activity_seen, target_subsequently_seen;
752 
  reg    [2:0] master_initial_latency_counter;
753 
  reg    [3:0] target_initial_latency_counter;
754 
  reg    [2:0] target_subsequent_latency_counter;
755 
  reg    [3:0] master_abort_timer;
756 
  reg     master_abort;
757 
 
758 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
759 
  begin
760 
    if (pci_ext_reset_l == 1'b0)
761 
    begin
762 
      master_activity_seen <= 1'b0;
763 
      master_initial_latency_counter <= 3'h0;
764 
      target_activity_seen <= 1'b0;
765 
      target_initial_latency_counter <= 4'h0;
766 
      target_subsequently_seen <= 1'b0;
767 
      target_subsequent_latency_counter <= 3'h0;
768 
      master_abort_timer <= 4'h0;
769 
      master_abort <= 1'b0;
770 
    end
771 
    else
772 
    begin
773 
      if ((address_phase_prev) | (~frame_prev & ~irdy_prev))  // address or idle
774 
      begin
775 
        master_abort_timer <= 4'h0;
776 
        master_abort <= 1'b0;
777 
        master_activity_seen <= 1'b0;
778 
        master_initial_latency_counter <= 3'h0;
779 
        target_activity_seen <= 1'b0;
780 
        target_initial_latency_counter <= 4'h0;
781 
        target_subsequently_seen <= 1'b0;
782 
        target_subsequent_latency_counter <= 3'h0;
783 
      end
784 
      else
785 
      begin
786 
// NOTE WORKING not debugged yet.
787 
        master_initial_latency_counter <= master_initial_latency_counter + 3'h1;
788 
        master_activity_seen <= master_activity_seen | irdy_now;
789 
        if ((master_initial_latency_counter == 3'h7) & ~master_activity_seen)
790 
        begin
791 
          $display ("*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
792 
                    $time);
793 
          $fdisplay (log_file_desc, "*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
794 
                    $time);
795 
          error_detected <= ~error_detected;
796 
          master_activity_seen <= 1'b1;
797 
        end
798 
        `NO_ELSE;
799 
 
800 
        target_initial_latency_counter <= target_initial_latency_counter
801 
                              + (devsel_now ? 4'h1 : 4'h0);
802 
        target_activity_seen <= target_activity_seen | trdy_now;
803 
        if ((target_initial_latency_counter == 4'hF) & ~target_activity_seen)
804 
        begin
805 
          $display ("*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
806 
                    $time);
807 
          $fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
808 
                    $time);
809 
          error_detected <= ~error_detected;
810 
          target_activity_seen <= 1'b1;
811 
        end
812 
        `NO_ELSE;
813 
 
814 
// NOTE This only detects Target misbehavior on the FIRST subsequent transfer!!!
815 
        target_subsequent_latency_counter <= target_subsequent_latency_counter
816 
                              + (target_activity_seen ? 3'h1 : 3'h0);
817 
        target_subsequently_seen <= target_subsequently_seen
818 
                                  | (target_activity_seen & trdy_now);
819 
        if ((target_subsequent_latency_counter == 3'h7) & ~target_subsequently_seen)
820 
        begin
821 
          $display ("*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
822 
                    $time);
823 
          $fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
824 
                    $time);
825 
          error_detected <= ~error_detected;
826 
          target_subsequently_seen <= 1'b1;
827 
        end
828 
        `NO_ELSE;
829 
 
830 
        master_abort_timer <= master_abort_timer + 4'h1;
831 
        master_abort <= (master_abort_timer >= 4'h2) ? 1'b1 : master_abort;
832 
      end
833 
    end
834 
  end
835 
 
836 
// Track the parity bit status on the bus.  The rules are:
837 
// 1) parity has to be correct whenever FRAME is asserted to be a valid address
838 
// 2) parity has to be correct whenever IRDY is asserted on writes
839 
// 3) parity has to be correct whenever TRDY is asserted on reads
840 
// parity covers the ad bus, and the cbe wires.  The PCI bus is even parity.
841 
// The number of bits set to 1 in AD plus CBE plus PAR is an EVEN number.
842 
// This code will notice an error, but will only complain if the PERR and SERR
843 
// bits don't match,
844 
  reg     prev_calculated_ad_cbe_parity;
845 
  reg     prev_prev_calculated_ad_cbe_parity, read_operation_prev_prev;
846 
  reg     prev_prev_devsel, prev_prev_trdy, prev_prev_irdy, prev_pci_ext_par;
847 
  reg     ad_prev_address_phase;
848 
  reg    [PCI_BUS_DATA_RANGE:0] ad_prev_prev;
849 
  reg    [PCI_BUS_CBE_RANGE:0] cbe_l_prev_prev;
850 
  always @(posedge pci_ext_clk)
851 
  begin
852 
// calculate 1 if an odd number of bits is set, 0 if an even number is set
853 
    prev_calculated_ad_cbe_parity <= (^pci_ext_ad[PCI_BUS_DATA_RANGE:0])
854 
                                   ^ (^pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0]);
855 
    prev_prev_calculated_ad_cbe_parity <= prev_calculated_ad_cbe_parity;
856 
    read_operation_prev_prev <= read_operation_prev;
857 
    ad_prev_address_phase <= address_phase_prev;
858 
    prev_prev_devsel <= devsel_prev;
859 
    prev_prev_trdy <= trdy_prev;
860 
    prev_prev_irdy <= irdy_prev;
861 
    prev_pci_ext_par <= pci_ext_par;
862 
    ad_prev_prev[PCI_BUS_DATA_RANGE:0] <= ad_prev[PCI_BUS_DATA_RANGE:0];
863 
    cbe_l_prev_prev[PCI_BUS_CBE_RANGE:0] <= cbe_l_prev[PCI_BUS_CBE_RANGE:0];
864 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
865 
    begin
866 
      if (ad_prev_address_phase)
867 
      begin
868 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
869 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
870 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_serr_l))
871 
        begin
872 
          $display ("*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
873 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
874 
          $fdisplay (log_file_desc, "*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
875 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
876 
          error_detected <= ~error_detected;
877 
        end
878 
        `NO_ELSE;
879 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
880 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
881 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_serr_l))
882 
        begin
883 
          $display ("*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
884 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
885 
          $fdisplay (log_file_desc, "*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
886 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
887 
          error_detected <= ~error_detected;
888 
        end
889 
        `NO_ELSE;
890 
      end
891 
      `NO_ELSE;
892 
      if (read_operation_prev_prev & prev_prev_trdy)
893 
      begin
894 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
895 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
896 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
897 
        begin
898 
          $display ("*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
899 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
900 
          $fdisplay (log_file_desc, "*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
901 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
902 
          error_detected <= ~error_detected;
903 
        end
904 
        `NO_ELSE;
905 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
906 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
907 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
908 
        begin
909 
          $display ("*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
910 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
911 
          $fdisplay (log_file_desc, "*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
912 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
913 
          error_detected <= ~error_detected;
914 
        end
915 
        `NO_ELSE;
916 
      end
917 
      `NO_ELSE;
918 
      if (~read_operation_prev_prev & prev_prev_irdy & prev_prev_devsel)
919 
      begin
920 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
921 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
922 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
923 
        begin
924 
          $display ("*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
925 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
926 
          $fdisplay (log_file_desc, "*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
927 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
928 
          error_detected <= ~error_detected;
929 
        end
930 
        `NO_ELSE;
931 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
932 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
933 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
934 
        begin
935 
          $display ("*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
936 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
937 
          $fdisplay (log_file_desc, "*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
938 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
939 
          error_detected <= ~error_detected;
940 
        end
941 
        `NO_ELSE;
942 
      end
943 
      `NO_ELSE;
944 
    end
945 
  end
946 
 
947 
// Verify some of the state transitions observed on the bus.
948 
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
949 
// In general, transition tests should look at one present signal, and
950 
//   a bunch of previous signals.
951 
// In general, simultaneous transition tests should look at two present
952 
//   signals, and a bunch of previous signals.
953 
  always @(posedge pci_ext_clk)
954 
  begin
955 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
956 
    begin
957 
      if (irdy_prev & ~read_operation_prev & ~(trdy_prev | stop_prev) & (pci_ext_ad != ad_prev))
958 
      begin  // Appendix C line 2C
959 
        $display ("*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
960 
                    $time);
961 
        $fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
962 
                    $time);
963 
        error_detected <= ~error_detected;
964 
      end
965 
      `NO_ELSE;
966 
      if (trdy_prev & read_operation_prev & ~irdy_prev & (pci_ext_ad != ad_prev))
967 
      begin  // Appendix C line 2C
968 
        $display ("*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
969 
                    $time);
970 
        $fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
971 
                    $time);
972 
        error_detected <= ~error_detected;
973 
      end
974 
      `NO_ELSE;
975 
      if (frame_prev & (frame_now | irdy_now) & ~address_phase_prev & ~trdy_now
976 
                                                 & (pci_ext_cbe_l != cbe_l_prev))
977 
      begin  // Appendix C line 3B
978 
        $display ("*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
979 
                    $time);
980 
        $fdisplay (log_file_desc, "*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
981 
                    $time);
982 
        error_detected <= ~error_detected;
983 
      end
984 
      `NO_ELSE;
985 
      if (~frame_prev & frame_now & irdy_now)
986 
      begin  // Section 3.3.3.1 rule 2, Appendix C line 7B
987 
        $display ("*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
988 
                    $time);
989 
        $fdisplay (log_file_desc, "*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
990 
                    $time);
991 
        error_detected <= ~error_detected;
992 
      end
993 
      `NO_ELSE;
994 
      if (~irdy_prev & irdy_now & ~frame_prev)
995 
      begin  // Appendix C line ?  not in there!
996 
        $display ("*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
997 
                    $time);
998 
        $fdisplay (log_file_desc, "*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
999 
                    $time);
1000 
        error_detected <= ~error_detected;
1001 
      end
1002 
      `NO_ELSE;
1003 
      if (frame_prev & ~frame_now & ~irdy_now)
1004 
      begin  // Section 3.3.3.1 rule 3, Appendix C line 7C
1005 
        $display ("*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
1006 
                    $time);
1007 
        $fdisplay (log_file_desc, "*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
1008 
                    $time);
1009 
        error_detected <= ~error_detected;
1010 
      end
1011 
      `NO_ELSE;
1012 
      if (irdy_prev & ~(trdy_prev | stop_prev | master_abort)
1013 
                                             & (frame_now != frame_prev))
1014 
      begin  // Section 3.3.3.1 rule 4, Appendix C line 7D
1015 
        $display ("*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
1016 
                    $time);
1017 
        $fdisplay (log_file_desc, "*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
1018 
                    $time);
1019 
        error_detected <= ~error_detected;
1020 
      end
1021 
      `NO_ELSE;
1022 
      if (irdy_prev & ~(trdy_prev | stop_prev | master_abort) & ~irdy_now)
1023 
      begin  // Section 3.3.3.1 rule 5, Appendix C line 7E
1024 
        $display ("*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
1025 
                    $time);
1026 
        $fdisplay (log_file_desc, "*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
1027 
                    $time);
1028 
        error_detected <= ~error_detected;
1029 
      end
1030 
      `NO_ELSE;
1031 
// NOTE WORKING section 3.3.3.2.2, Appendix C line 10, REQ must be removed for
1032 
// NOTE WORKING IDLE and one clock on either side of IDLE upon retry or disconnect
1033 
      if (stop_prev & frame_prev & frame_now & ~stop_now)
1034 
      begin  // Section 3.3.3.2.1 rule 3, Appendix C line 12C
1035 
        $display ("*** monitor - STOP Deasserted while FRAME Asserted, at %t",
1036 
                    $time);
1037 
        $fdisplay (log_file_desc, "*** monitor - STOP Deasserted while FRAME Asserted, at %t",
1038 
                    $time);
1039 
        error_detected <= ~error_detected;
1040 
      end
1041 
      `NO_ELSE;
1042 
      if (stop_prev & ~frame_prev & frame_now & stop_now)
1043 
      begin  // Section 3.3.3.2.1 rule 3, Appendix C line 12C, author addition
1044 
        $display ("*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
1045 
                    $time);
1046 
        $fdisplay (log_file_desc, "*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
1047 
                    $time);
1048 
        error_detected <= ~error_detected;
1049 
      end
1050 
      `NO_ELSE;
1051 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (devsel_prev != devsel_now))
1052 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1053 
        $display ("*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
1054 
                    $time);
1055 
        $fdisplay (log_file_desc, "*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
1056 
                    $time);
1057 
        error_detected <= ~error_detected;
1058 
      end
1059 
      `NO_ELSE;
1060 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (trdy_prev != trdy_now))
1061 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1062 
        $display ("*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
1063 
                    $time);
1064 
        $fdisplay (log_file_desc, "*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
1065 
                    $time);
1066 
        error_detected <= ~error_detected;
1067 
      end
1068 
      `NO_ELSE;
1069 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (stop_prev != stop_now))
1070 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1071 
        $display ("*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
1072 
                    $time);
1073 
        $fdisplay (log_file_desc, "*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
1074 
                    $time);
1075 
        error_detected <= ~error_detected;
1076 
      end
1077 
      `NO_ELSE;
1078 
      if (~trdy_prev & trdy_now & ~devsel_now)
1079 
      begin  // Appendix C line 14
1080 
        $display ("*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
1081 
                    $time);
1082 
        $fdisplay (log_file_desc, "*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
1083 
                    $time);
1084 
        error_detected <= ~error_detected;
1085 
      end
1086 
      `NO_ELSE;
1087 
      if (~stop_prev & stop_now & ~(devsel_prev | devsel_now))
1088 
      begin  // Appendix C line 14
1089 
        $display ("*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
1090 
                    $time);
1091 
        $fdisplay (log_file_desc, "*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
1092 
                    $time);
1093 
        error_detected <= ~error_detected;
1094 
      end
1095 
      `NO_ELSE;
1096 
      if (~frame_prev & frame_now & (grant_prev == 5'h1F))
1097 
      begin  // Appendix C line 21
1098 
        $display ("*** monitor - FRAME Asserted when no GNT Asserted, at %t",
1099 
                    $time);
1100 
        $fdisplay (log_file_desc, "*** monitor - FRAME Asserted when no GNT Asserted, at %t",
1101 
                    $time);
1102 
        error_detected <= ~error_detected;
1103 
      end
1104 
      `NO_ELSE;
1105 
      if (devsel_prev & ~devsel_now & frame_prev & ~(stop_now & ~trdy_now))
1106 
      begin  // Appendix C line 30
1107 
        $display ("*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
1108 
                    $time);
1109 
        $fdisplay (log_file_desc, "*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
1110 
                    $time);
1111 
        error_detected <= ~error_detected;
1112 
      end
1113 
      `NO_ELSE;
1114 
    end
1115 
    `NO_ELSE;
1116 
  end
1117 
 
1118 
// Verify some of the state transitions observed on the bus. See the
1119 
// PCI Local Bus Spec Revision 2.2 section 3.2.1, plus Appendix C.
1120 
`ifdef VERBOSE_MONITOR_DEVICE
1121 
  reg     prev_pci_ext_reset_l;
1122 
  always @(pci_ext_reset_l)
1123 
  begin
1124 
    prev_pci_ext_reset_l <= pci_ext_reset_l;
1125 
 
1126 
    if (($time > 0) && (pci_ext_reset_l !== prev_pci_ext_reset_l))
1127 
    begin
1128 
      if (pci_ext_reset_l == 1'b0)
1129 
      begin
1130 
        $display (" monitor - PCI External RESET_L asserted LOW at %t", $time);
1131 
      end
1132 
      `NO_ELSE;
1133 
 
1134 
      if (pci_ext_reset_l == 1'b1)
1135 
      begin
1136 
        $display (" monitor - PCI External RESET_L deasserted HIGH at %t", $time);
1137 
      end
1138 
      `NO_ELSE;
1139 
    end
1140 
  end
1141 
 
1142 
  always @(posedge pci_ext_clk)
1143 
  begin
1144 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
1145 
    begin
1146 
// report a Master Abort, which is not an error
1147 
      if ((irdy_prev & ~irdy_now) & (~trdy_prev & ~stop_prev & master_abort))
1148 
      begin
1149 
        $display (" monitor - IRDY Deasserted due to Master Abort, at %t", $time);
1150 
      end
1151 
      `NO_ELSE;
1152 
 
1153 
      if (~frame_prev & frame_now & irdy_prev & ~irdy_now)
1154 
      begin
1155 
        $display (" Fast Back-to-Back reference with no Idle cycle started at %t",
1156 
                  $time);
1157 
      end
1158 
      `NO_ELSE;
1159 
    end
1160 
    `NO_ELSE;
1161 
  end
1162 
`endif // VERBOSE_MONITOR_DEVICE
1163 
 
1164 
`ifdef VERBOSE_MONITOR_DEVICE
1165 
  always @(posedge pci_ext_clk)
1166 
  begin
1167 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0) && address_phase_prev)
1168 
    begin
1169 
// command list taken from PCI Local Bus Spec Revision 2.2 section 3.1.1.
1170 
      case (cbe_l_prev[PCI_BUS_CBE_RANGE:0])
1171 
      PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
1172 
        $display (" monitor - Interrupt Acknowledge started, AD: 'h%x, CBE: 'h%x, at time %t",
1173 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);,
1174 
      PCI_COMMAND_SPECIAL_CYCLE:
1175 
        $display (" monitor - Special Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
1176 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1177 
      PCI_COMMAND_IO_READ:
1178 
        $display (" monitor - IO Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1179 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1180 
      PCI_COMMAND_IO_WRITE:
1181 
        $display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1182 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1183 
      PCI_COMMAND_RESERVED_READ_4:
1184 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1185 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1186 
      PCI_COMMAND_RESERVED_WRITE_5:
1187 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1188 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1189 
      PCI_COMMAND_MEMORY_READ:
1190 
        $display (" monitor - Memory Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1191 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1192 
      PCI_COMMAND_MEMORY_WRITE:
1193 
        $display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1194 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1195 
      PCI_COMMAND_RESERVED_READ_8:
1196 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1197 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1198 
      PCI_COMMAND_RESERVED_WRITE_9:
1199 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1200 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1201 
      PCI_COMMAND_CONFIG_READ:
1202 
        $display (" monitor - Configuration Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1203 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1204 
      PCI_COMMAND_CONFIG_WRITE:
1205 
        $display (" monitor - Configuration Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1206 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1207 
      PCI_COMMAND_MEMORY_READ_MULTIPLE:
1208 
        $display (" monitor - Memory Read Multiple started, AD: 'h%x, CBE: 'h%x, at time %t",
1209 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1210 
      PCI_COMMAND_DUAL_ADDRESS_CYCLE:
1211 
        $display (" monitor - Dual Address Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
1212 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1213 
      PCI_COMMAND_MEMORY_READ_LINE:
1214 
        $display (" monitor - Memory Read Line started, AD: 'h%x, CBE: 'h%x, at time %t",
1215 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1216 
      PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
1217 
        $display (" monitor - Memory Write and Invalidate started, AD: 'h%x, CBE: 'h%x, at time %t",
1218 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1219 
      default:
1220 
        begin
1221 
          $display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
1222 
                      ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1223 
          $fdisplay (log_file_desc,
1224 
          error_detected <= ~error_detected;
1225 
        end
1226 
      endcase
1227 
    end
1228 
    `NO_ELSE;
1229 
  end
1230 
`endif // VERBOSE_MONITOR_DEVICE
1231 
endmodule
1232 
 

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