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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "pci_regression_constants.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Tadej Markovic (tadej@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.2 2002/02/19 16:32:29 mihad
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// Modified testbench and fixed some bugs
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//
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mihad |
// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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mihad |
//
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mihad |
//
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mihad |
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///////////////////////////////////////////////////////////////////////////////
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//// ===================================================================== ////
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//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////
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//// (script for running regression is prepared for NC-Sim) ////
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//// ////
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//// For description of defines see pci_user_constants.v file ! ////
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//// ===================================================================== ////
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///////////////////////////////////////////////////////////////////////////////
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// Fifo implementation defines:
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// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
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// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
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// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
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// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
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// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
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// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
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// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
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// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
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// WB_FIFO_RAM_ADDR_LENGTH.
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`ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only
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`define WBW_ADDR_LENGTH 3
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`define WBR_ADDR_LENGTH 4
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`define PCIW_ADDR_LENGTH 4
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`define PCIR_ADDR_LENGTH 3
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`define FPGA
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`define XILINX
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`define WB_RAM_DONT_SHARE
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`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition
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//`define PCI_XILINX_RAMB4
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//`define WB_XILINX_RAMB4
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`define PCI_XILINX_DIST_RAM
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`define WB_XILINX_DIST_RAM
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`endif
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_ARTISAN_SDP
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`define PCI_ARTISAN_SDP
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`endif
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`else
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`ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only
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`define WBW_ADDR_LENGTH 7
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`define WBR_ADDR_LENGTH 6
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`define PCIW_ADDR_LENGTH 7
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`define PCIR_ADDR_LENGTH 8
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//`define FPGA
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//`define XILINX
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//`define WB_RAM_DONT_SHARE
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`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define PCI_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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`define WB_ARTISAN_SDP
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`define PCI_ARTISAN_SDP
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`endif
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`else
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`ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic)
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`define WBW_ADDR_LENGTH 3
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`define WBR_ADDR_LENGTH 4
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`define PCIW_ADDR_LENGTH 4
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`define PCIR_ADDR_LENGTH 3
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//`define FPGA
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//`define XILINX
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`define WB_RAM_DONT_SHARE
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//`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define PCI_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 5 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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//`define WB_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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`endif
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`else
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`ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic)
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`define WBW_ADDR_LENGTH 7
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`define WBR_ADDR_LENGTH 6
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`define PCIW_ADDR_LENGTH 7
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`define PCIR_ADDR_LENGTH 8
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//`define FPGA
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//`define XILINX
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//`define WB_RAM_DONT_SHARE
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`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define PCI_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`else
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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//`define WB_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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`endif
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`else
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`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
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`define WBW_ADDR_LENGTH 9
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`define WBR_ADDR_LENGTH 9
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`define PCIW_ADDR_LENGTH 9
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`define PCIR_ADDR_LENGTH 9
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//`define FPGA
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//`define XILINX
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//`define WB_RAM_DONT_SHARE
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//`define PCI_RAM_DONT_SHARE
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`ifdef FPGA
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`ifdef XILINX
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`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
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`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
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`define PCI_XILINX_RAMB4
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`define WB_XILINX_RAMB4
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//`define PCI_XILINX_DIST_RAM
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//`define WB_XILINX_DIST_RAM
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`endif
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`else
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mihad |
`define PCI_FIFO_RAM_ADDR_LENGTH 10 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
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`define WB_FIFO_RAM_ADDR_LENGTH 10 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
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mihad |
//`define WB_ARTISAN_SDP
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//`define PCI_ARTISAN_SDP
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`endif
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`else
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`endif
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`endif
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`endif
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`endif
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`endif
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// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
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// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
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// smaller the number here, faster the decoder operation
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mihad |
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// initial value for PCI image address masks. Address masks can be defined in enabled state,
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// to allow device independent software to detect size of image and map base addresses to
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// memory space. If initial mask for an image is defined as 0, then device independent software
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// won't detect base address implemented and device dependent software will have to configure
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// address masks as well as base addresses!
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// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
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// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
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// Device independent software sets the base addresses acording to MEMORY or IO maping!
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mihad |
`ifdef PCI_DECODE_MIN
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`define PCI_NUM_OF_DEC_ADDR_LINES 3
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mihad |
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// don't disable AM0 if GUEST bridge, otherwise there is no other way of accesing configuration space
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`ifdef HOST
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`define PCI_AM0 20'h0000_0
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`else
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`define PCI_AM0 20'hE000_0
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`endif
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`define PCI_AM1 20'hE000_0
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`define PCI_AM2 20'h0000_0
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`define PCI_AM3 20'hE000_0
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`define PCI_AM4 20'h0000_0
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`define PCI_AM5 20'hE000_0
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`define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
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`define PCI_BA1_MEM_IO 1'b0
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`define PCI_BA2_MEM_IO 1'b1
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`define PCI_BA3_MEM_IO 1'b0
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`define PCI_BA4_MEM_IO 1'b1
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`define PCI_BA5_MEM_IO 1'b0
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mihad |
`else
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`ifdef PCI_DECODE_MED
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`define PCI_NUM_OF_DEC_ADDR_LINES 12
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`define PCI_AM0 20'hfff0_0
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`define PCI_AM1 20'h0000_0
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`define PCI_AM2 20'hfff0_0
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`define PCI_AM3 20'h0000_0
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`define PCI_AM4 20'hfff0_0
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`define PCI_AM5 20'h0000_0
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`define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
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`define PCI_BA1_MEM_IO 1'b0
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`define PCI_BA2_MEM_IO 1'b1
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`define PCI_BA3_MEM_IO 1'b0
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`define PCI_BA4_MEM_IO 1'b1
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`define PCI_BA5_MEM_IO 1'b0
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`else
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`ifdef PCI_DECODE_MAX
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`define PCI_NUM_OF_DEC_ADDR_LINES 20
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mihad |
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`define PCI_AM0 20'hffff_e
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`define PCI_AM1 20'hffff_c
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`define PCI_AM2 20'hffff_8
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`define PCI_AM3 20'hfffe_0
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`define PCI_AM4 20'hfffc_0
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`define PCI_AM5 20'hfff8_0
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`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
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`define PCI_BA1_MEM_IO 1'b0
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`define PCI_BA2_MEM_IO 1'b1
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`define PCI_BA3_MEM_IO 1'b1
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`define PCI_BA4_MEM_IO 1'b0
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`define PCI_BA5_MEM_IO 1'b0
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mihad |
`endif
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`endif
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| 297 |
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`endif
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| 298 |
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| 299 |
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| 300 |
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| 301 |
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// number defined here specifies how many MS bits in WB address are compared with base address, to decode
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// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
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| 303 |
|
|
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
|
| 304 |
|
|
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
|
| 305 |
|
|
// smaller the number here, faster the decoder operation
|
| 306 |
|
|
`ifdef WB_DECODE_MIN
|
| 307 |
26 |
mihad |
`define WB_NUM_OF_DEC_ADDR_LINES 4
|
| 308 |
15 |
mihad |
`else
|
| 309 |
|
|
`ifdef WB_DECODE_MED
|
| 310 |
|
|
`define WB_NUM_OF_DEC_ADDR_LINES 12
|
| 311 |
|
|
`else
|
| 312 |
|
|
`ifdef WB_DECODE_MAX
|
| 313 |
|
|
`define WB_NUM_OF_DEC_ADDR_LINES 20
|
| 314 |
|
|
`endif
|
| 315 |
|
|
`endif
|
| 316 |
|
|
`endif
|
| 317 |
|
|
|
| 318 |
|
|
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
|
| 319 |
|
|
`ifdef WB_CNF_BASE_ZERO
|
| 320 |
|
|
`define WB_CONFIGURATION_BASE 20'h0000_0
|
| 321 |
|
|
`else
|
| 322 |
26 |
mihad |
`define WB_CONFIGURATION_BASE 20'hB000_0
|
| 323 |
15 |
mihad |
`endif
|
| 324 |
|
|
|
| 325 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
| 326 |
|
|
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
|
| 327 |
|
|
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
|
| 328 |
|
|
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
|
| 329 |
|
|
together by application.
|
| 330 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
| 331 |
|
|
`define HEADER_VENDOR_ID 16'h2321
|
| 332 |
|
|
`define HEADER_DEVICE_ID 16'h0001
|
| 333 |
|
|
`define HEADER_REVISION_ID 8'h01
|
| 334 |
|
|
|
| 335 |
|
|
// MAX Retry counter value for WISHBONE Master state-machine
|
| 336 |
|
|
// This value is 8-bit because of 8-bit retry counter !!!
|
| 337 |
26 |
mihad |
`define WB_RTY_CNT_MAX 8'hff
|
| 338 |
15 |
mihad |
|
| 339 |
|
|
/////////////////////////////////////////////////////////////////////////////////
|
| 340 |
|
|
//// ======================================================================= ////
|
| 341 |
|
|
//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////
|
| 342 |
|
|
//// (script for running regression is prepared for NC-Sim) ////
|
| 343 |
|
|
//// ////
|
| 344 |
|
|
//// For description of defines see pci_testbench_defines.v file ! ////
|
| 345 |
|
|
//// ======================================================================= ////
|
| 346 |
|
|
/////////////////////////////////////////////////////////////////////////////////
|
| 347 |
|
|
|
| 348 |
|
|
// wishbone frequncy in GHz
|
| 349 |
|
|
`ifdef WB_CLK10
|
| 350 |
|
|
`define WB_FREQ 0.01
|
| 351 |
|
|
`else
|
| 352 |
|
|
`ifdef WB_CLK66
|
| 353 |
|
|
`define WB_FREQ 0.066
|
| 354 |
|
|
`else
|
| 355 |
26 |
mihad |
`ifdef WB_CLK220
|
| 356 |
|
|
`define WB_FREQ 0.22
|
| 357 |
15 |
mihad |
`endif
|
| 358 |
|
|
`endif
|
| 359 |
|
|
`endif
|
| 360 |
|
|
|
| 361 |
|
|
// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
|
| 362 |
|
|
`define TAR0_BASE_ADDR_0 32'h1000_0000
|
| 363 |
|
|
`define TAR0_BASE_ADDR_1 32'h2000_0000
|
| 364 |
26 |
mihad |
`define TAR0_BASE_ADDR_2 32'h4000_0000
|
| 365 |
|
|
`define TAR0_BASE_ADDR_3 32'h6000_0000
|
| 366 |
|
|
`define TAR0_BASE_ADDR_4 32'h8000_0000
|
| 367 |
|
|
`define TAR0_BASE_ADDR_5 32'hA000_0000
|
| 368 |
15 |
mihad |
|
| 369 |
|
|
`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
|
| 370 |
|
|
`define TAR0_ADDR_MASK_1 32'hFFFF_F000
|
| 371 |
|
|
`define TAR0_ADDR_MASK_2 32'hFFFF_F000
|
| 372 |
|
|
`define TAR0_ADDR_MASK_3 32'hFFFF_F000
|
| 373 |
|
|
`define TAR0_ADDR_MASK_4 32'hFFFF_F000
|
| 374 |
|
|
`define TAR0_ADDR_MASK_5 32'hFFFF_F000
|
| 375 |
|
|
|
| 376 |
26 |
mihad |
`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
|
| 377 |
|
|
`define TAR0_TRAN_ADDR_1 32'hA000_0000
|
| 378 |
|
|
`define TAR0_TRAN_ADDR_2 32'h8000_0000
|
| 379 |
|
|
`define TAR0_TRAN_ADDR_3 32'h6000_0000
|
| 380 |
|
|
`define TAR0_TRAN_ADDR_4 32'h4000_0000
|
| 381 |
|
|
`define TAR0_TRAN_ADDR_5 32'h2000_0000
|
| 382 |
15 |
mihad |
|
| 383 |
|
|
// values of image registers of PCI behavioral target devices !
|
| 384 |
26 |
mihad |
`define BEH_TAR1_MEM_START 32'hC000_0000
|
| 385 |
|
|
`define BEH_TAR1_MEM_END 32'hC000_0FFF
|
| 386 |
|
|
`define BEH_TAR1_IO_START 32'hD000_0001
|
| 387 |
|
|
`define BEH_TAR1_IO_END 32'hD000_0FFF
|
| 388 |
15 |
mihad |
|
| 389 |
26 |
mihad |
`define BEH_TAR2_MEM_START 32'hE000_0000
|
| 390 |
|
|
`define BEH_TAR2_MEM_END 32'hE000_0FFF
|
| 391 |
|
|
`define BEH_TAR2_IO_START 32'hF000_0001
|
| 392 |
|
|
`define BEH_TAR2_IO_END 32'hF000_0FFF
|
| 393 |
15 |
mihad |
|
| 394 |
45 |
mihad |
// IDSEL lines of each individual Target is connected to one address line
|
| 395 |
|
|
// following defines set the address line IDSEL is connected to
|
| 396 |
|
|
// TAR0 = DUT - bridge
|
| 397 |
|
|
// TAR1 = behavioral target 1
|
| 398 |
|
|
// TAR2 = behavioral target 2
|
| 399 |
|
|
|
| 400 |
|
|
`define TAR0_IDSEL_INDEX 31
|
| 401 |
|
|
`define TAR1_IDSEL_INDEX 29
|
| 402 |
|
|
`define TAR2_IDSEL_INDEX 30
|
| 403 |
|
|
|
| 404 |
|
|
// next 3 defines are derived from previous three defines
|
| 405 |
|
|
`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
|
| 406 |
|
|
`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
|
| 407 |
|
|
`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
|
| 408 |
15 |
mihad |
/*=======================================================================================
|
| 409 |
|
|
Following defines are used in a script file for regression testing !!!
|
| 410 |
|
|
=========================================================================================
|
| 411 |
|
|
|
| 412 |
|
|
REGRESSION
|
| 413 |
|
|
HOST GUEST
|
| 414 |
|
|
REGR_FIFO_SMALL_XILINX REGR_FIFO_MEDIUM_ARTISAN REGR_FIFO_LARGE_GENERIC
|
| 415 |
|
|
(REGR_FIFO_SMALL_GENERIC) (REGR_FIFO_MEDIUM_GENERIC)
|
| 416 |
|
|
ADDR_TRAN_IMPL
|
| 417 |
|
|
WB_RETRY_MAX
|
| 418 |
|
|
WB_CNF_BASE_ZERO
|
| 419 |
|
|
NO_CNF_IMAGE
|
| 420 |
|
|
PCI_IMAGE0 // `ifdef HOST `ifdef NO_CNF_IMAGE `define PCI_IMAGE0
|
| 421 |
|
|
PCI_IMAGE2
|
| 422 |
|
|
PCI_IMAGE3
|
| 423 |
|
|
PCI_IMAGE4
|
| 424 |
|
|
PCI_IMAGE5
|
| 425 |
|
|
WB_IMAGE2
|
| 426 |
|
|
WB_IMAGE3
|
| 427 |
|
|
WB_IMAGE4
|
| 428 |
|
|
WB_IMAGE5
|
| 429 |
|
|
WB_DECODE_FAST WB_DECODE_MEDIUM WB_DECODE_SLOW
|
| 430 |
|
|
REGISTER_WBM_OUTPUTS
|
| 431 |
|
|
REGISTER_WBS_OUTPUTS
|
| 432 |
|
|
PCI_DECODE_MIN PCI_DECODE_MED PCI_DECODE_MAX
|
| 433 |
|
|
WB_DECODE_MIN WB_DECODE_MED WB_DECODE_MAX
|
| 434 |
|
|
PCI33 PCI66
|
| 435 |
|
|
WB_CLK10 WB_CLK66 WB_CLK100
|
| 436 |
|
|
ACTIVE_LOW_OE ACTIVE_HIGH_OE
|
| 437 |
|
|
|
| 438 |
|
|
-----------------------------------------------------------------------------------------
|
| 439 |
|
|
Follows combinations of defines used in a script file for regression testing !!!
|
| 440 |
|
|
-----------------------------------------------------------------------------------------
|
| 441 |
|
|
|
| 442 |
|
|
"REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI33+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2"
|
| 443 |
|
|
"REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI33+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE5"
|
| 444 |
|
|
"REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_IMAGE5"
|
| 445 |
|
|
"REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE5+WB_IMAGE4"
|
| 446 |
|
|
"REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+PCI_IMAGE0+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4"
|
| 447 |
|
|
"REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL"
|
| 448 |
|
|
"REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE4"
|
| 449 |
|
|
"REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"
|
| 450 |
|
|
"REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE3"
|
| 451 |
|
|
"REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI33+WB_CLK66+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE3"
|
| 452 |
|
|
"REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2"
|
| 453 |
|
|
"REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI33+WB_CLK10+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"
|
| 454 |
|
|
""
|
| 455 |
|
|
|
| 456 |
|
|
=========================================================================================
|
| 457 |
|
|
*/
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
|
