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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  File name "system.v"                                        ////

////                                                              ////

////  This file is part of the "PCI bridge" project               ////

////  http://www.opencores.org/cores/pci/                         ////

////                                                              ////

////  Author(s):                                                  ////

////      - Miha Dolenc (mihad@opencores.org)                     ////

////      - Tadej Markovic (tadej@opencores.org)                  ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

//

`include "pci_constants.v"

`include "bus_commands.v"

`include "pci_testbench_defines.v"

`include "timescale.v"

`ifdef HOST

    `ifdef NO_CNF_IMAGE

    `else

        `define TEST_CONF_CYCLE_TYPE1_REFERENCE

    `endif

`else

    `define TEST_CONF_CYCLE_TYPE1_REFERENCE

`endif

module SYSTEM ;

`include "pci_blue_constants.vh"

`include "pci_blue_options.vh"

integer tests_successfull ;

integer tests_failed ;

integer tb_log_file ;

reg [799:0] test_name ;

reg pci_clock ;

reg wb_clock ;

reg reset ;

wire [4:0] arb_grant_out ;

wire [31:0] AD ;

wire [3:0]  CBE ;

pullup(INTA) ;

pullup(MAS0_REQ) ;

pullup(MAS1_REQ) ;

pullup(MAS2_REQ) ;

pullup(MAS3_REQ) ;

wire MAS0_GNT = ~arb_grant_out[0];

wire MAS1_GNT = ~arb_grant_out[1] ;

wire MAS2_GNT = ~arb_grant_out[2] ;

wire MAS3_GNT = ~arb_grant_out[3] ;

pullup(FRAME) ;

pullup(IRDY) ;

wire        TAR0_IDSEL = AD[`TAR0_IDSEL_INDEX] ;

pullup(DEVSEL) ;

pullup(TRDY) ;

pullup(STOP) ;

wire   PAR ;

pullup(PERR) ;

pullup(SERR) ;

wire [3:0] MAS1_IDSEL ;

pullup lockpu ( LOCK ) ;

wire        RST_O ;

wire        INT_O ;

reg         INT_I ;

wire [31:0] ADR_I ;

wire [31:0] SDAT_I ;

wire [31:0] SDAT_O ;

wire [3:0]  SEL_I ;

wire        CYC_I ;

wire        STB_I ;

wire        WE_I ;

wire        CAB_I ;

wire        ACK_O ;

wire        RTY_O ;

wire        ERR_O ;

wire [31:0] ADR_O ;

wire [31:0] MDAT_I ;

wire [31:0] MDAT_O ;

wire [3:0]  SEL_O ;

wire        CYC_O ;

wire        STB_O ;

wire        WE_O ;

wire        CAB_O ;

wire        ACK_I ;

wire        RTY_I ;

wire        ERR_I ;

wire        TAR1_IDSEL = AD[`TAR1_IDSEL_INDEX] ;

wire        TAR2_IDSEL = AD[`TAR2_IDSEL_INDEX] ;

wire        reset_wb ; // reset to Wb devices

`ifdef GUEST

    wire    RST = ~reset ;

    assign  reset_wb = RST_O ;

`else

    pullup(RST) ;

    assign  reset_wb = reset ;

`endif

`define PCI_BRIDGE_INSTANCE bridge32_top

TOP `PCI_BRIDGE_INSTANCE

(

    .CLK    ( pci_clock),

    .AD     ( AD ),

    .CBE    ( CBE ),

    .RST    ( RST ),

    .INTA   ( INTA ),

    .REQ    ( MAS0_REQ ),

    .GNT    ( MAS0_GNT ),

    .FRAME  ( FRAME ),

    .IRDY   ( IRDY ),

    .IDSEL  ( TAR0_IDSEL),

    .DEVSEL ( DEVSEL ),

    .TRDY   ( TRDY ),

    .STOP   ( STOP ),

    .PAR    ( PAR ),

    .PERR   ( PERR ),

    .SERR   ( SERR ),

    .CLK_I  ( wb_clock ),

    .RST_I  ( reset ),

    .RST_O  ( RST_O ),

    .INT_I  ( INT_I ),

    .INT_O  ( INT_O ),

    // WISHBONE slave interface

    .ADR_I  ( ADR_I ),

    .SDAT_I ( SDAT_I ),

    .SDAT_O ( SDAT_O ),

    .SEL_I  ( SEL_I ),

    .CYC_I  ( CYC_I ),

    .STB_I  ( STB_I ),

    .WE_I   ( WE_I ),

    .CAB_I  ( CAB_I),

    .ACK_O  ( ACK_O ),

    .RTY_O  ( RTY_O ),

    .ERR_O  ( ERR_O ),

    // WISHBONE master interface

    .ADR_O  ( ADR_O ),

    .MDAT_I ( MDAT_I ),

    .MDAT_O ( MDAT_O ),

    .SEL_O  ( SEL_O ),

    .CYC_O  ( CYC_O ),

    .STB_O  ( STB_O ),

    .WE_O   ( WE_O ),

    .CAB_O  ( CAB_O ),

    .ACK_I  ( ACK_I ),

    .RTY_I  ( RTY_I ),

    .ERR_I  ( ERR_I )

) ;

WB_MASTER_BEHAVIORAL wishbone_master

(

    .CLK_I(wb_clock),

    .RST_I(reset_wb),

    .TAG_I(4'b0000),

    .TAG_O(),

    .ACK_I(ACK_O),

    .ADR_O(ADR_I),

    .CYC_O(CYC_I),

    .DAT_I(SDAT_O),

    .DAT_O(SDAT_I),

    .ERR_I(ERR_O),

    .RTY_I(RTY_O),

    .SEL_O(SEL_I),

    .STB_O(STB_I),

    .WE_O (WE_I),

    .CAB_O(CAB_I)

);

WB_SLAVE_BEHAVIORAL wishbone_slave

(

    .CLK_I              (wb_clock),

    .RST_I              (reset_wb),

    .ACK_O              (ACK_I),

    .ADR_I              (ADR_O),

    .CYC_I              (CYC_O),

    .DAT_O              (MDAT_I),

    .DAT_I              (MDAT_O),

    .ERR_O              (ERR_I),

    .RTY_O              (RTY_I),

    .SEL_I              (SEL_O),

    .STB_I              (STB_O),

    .WE_I               (WE_O),

    .CAB_I              (CAB_O)

);

integer wbu_mon_log_file_desc ;

integer pciu_mon_log_file_desc ;

WB_BUS_MON wbu_wb_mon(

                    .CLK_I(wb_clock),

                    .RST_I(reset_wb),

                    .ACK_I(ACK_O),

                    .ADDR_O(ADR_I),

                    .CYC_O(CYC_I),

                    .DAT_I(SDAT_O),

                    .DAT_O(SDAT_I),

                    .ERR_I(ERR_O),

                    .RTY_I(RTY_O),

                    .SEL_O(SEL_I),

                    .STB_O(STB_I),

                    .WE_O (WE_I),

                    .TAG_I({`WB_TAG_WIDTH{1'b0}}),

                    .TAG_O(),

                    .CAB_O(CAB_I),

                    .log_file_desc ( wbu_mon_log_file_desc )

                  ) ;

WB_BUS_MON pciu_wb_mon(

                    .CLK_I(wb_clock),

                    .RST_I(reset_wb),

                    .ACK_I(ACK_I),

                    .ADDR_O(ADR_O),

                    .CYC_O(CYC_O),

                    .DAT_I(MDAT_I),

                    .DAT_O(MDAT_O),

                    .ERR_I(ERR_I),

                    .RTY_I(RTY_I),

                    .SEL_O(SEL_O),

                    .STB_O(STB_O),

                    .WE_O (WE_O),

                    .TAG_I({`WB_TAG_WIDTH{1'b0}}),

                    .TAG_O(),

                    .CAB_O(CAB_O),

                    .log_file_desc( pciu_mon_log_file_desc )

                  ) ;

// some aditional signals are needed here because of the arbiter

reg [3:0] pci_ext_req_prev ;

always@(posedge pci_clock)

begin

    pci_ext_req_prev <= {~MAS3_REQ, ~MAS2_REQ, ~MAS1_REQ, ~MAS0_REQ} ;

end

reg pci_frame_prev ;

always@(posedge pci_clock)

begin

    pci_frame_prev <= FRAME ;

end

reg pci_irdy_prev ;

always@(posedge pci_clock)

begin

    pci_irdy_prev <= IRDY ;

end

pci_blue_arbiter pci_arbiter

(

  .pci_int_req_direct(1'b0),

  .pci_ext_req_prev(pci_ext_req_prev),

  .pci_int_gnt_direct_out(arb_grant_out[4]),

  .pci_ext_gnt_direct_out(arb_grant_out[3:0]),

  .pci_frame_prev(~pci_frame_prev),

  .pci_irdy_prev(~pci_irdy_prev),

  .pci_irdy_now(~IRDY),

  .arbitration_enable(1'b1),

  .pci_clk(pci_clock),

  .pci_reset_comb(~RST)

);

reg [31:0] target_message ;

// define output enable signals for monitor inputs

// real output enable signals

//{frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}

`ifdef ACTIVE_LOW_OE

wire devsel_t_s_oe = `PCI_BRIDGE_INSTANCE.DEVSEL_en && `PCI_BRIDGE_INSTANCE.TRDY_en && `PCI_BRIDGE_INSTANCE.STOP_en ;

wire ad_oe         = &(`PCI_BRIDGE_INSTANCE.AD_en) ;

wire cbe_oe        = &(`PCI_BRIDGE_INSTANCE.CBE_en) ;

wire [5:0] r_oe_sigs = {!`PCI_BRIDGE_INSTANCE.FRAME_en,

                        !`PCI_BRIDGE_INSTANCE.IRDY_en,

                        !devsel_t_s_oe,

                        !ad_oe,

                        !cbe_oe,

                        !`PCI_BRIDGE_INSTANCE.PERR_en}

                        ;

`else

`ifdef ACTIVE_HIGH_OE

wire devsel_t_s_oe = `PCI_BRIDGE_INSTANCE.DEVSEL_en || `PCI_BRIDGE_INSTANCE.TRDY_en || `PCI_BRIDGE_INSTANCE.STOP_en ;

wire ad_oe         = |(`PCI_BRIDGE_INSTANCE.AD_en) ;

wire cbe_oe        = |(`PCI_BRIDGE_INSTANCE.CBE_en) ;

wire [5:0] r_oe_sigs = {`PCI_BRIDGE_INSTANCE.FRAME_en,

                        `PCI_BRIDGE_INSTANCE.IRDY_en,

                        devsel_t_s_oe,

                        ad_oe,

                        cbe_oe,

                        `PCI_BRIDGE_INSTANCE.PERR_en}

                        ;

`endif

`endif

/*wire [5:0] oe_sigs_0 = {1'b0,

                        1'b0,

                        pci_target32.ctl_enable | pci_target32.r_ctl_enable,

                        pci_target32.ad_enable,

                        1'b0,

                        pci_target32.err_enable | pci_target32.r_err_enable

                       } ;

*/

wire [5:0] oe_sigs_2 ;

wire [5:0] oe_sigs_1 ;

// signals which are used by test modules to know what to do

triand  test_accepted_l_int, error_event_int;

pullup  (test_accepted_l_int), (error_event_int);

wire    pci_reset_comb  = ~RST;

wire    pci_ext_clk     = pci_clock;

integer pci_mon_log_file_desc ;

pci_bus_monitor monitor32

(

    .pci_ext_ad                 (AD),

    .pci_ext_cbe_l              (CBE),

    .pci_ext_par                (PAR),

    .pci_ext_frame_l            (FRAME),

    .pci_ext_irdy_l             (IRDY),

    .pci_ext_devsel_l           (DEVSEL),

    .pci_ext_trdy_l             (TRDY),

    .pci_ext_stop_l             (STOP),

    .pci_ext_perr_l             (PERR),

    .pci_ext_serr_l             (SERR),

    .pci_real_req_l             (MAS0_REQ),

    .pci_real_gnt_l             (MAS0_GNT),

    .pci_ext_req_l              ({1'b1, MAS3_REQ, MAS2_REQ, MAS1_REQ}),

    .pci_ext_gnt_l              (~arb_grant_out[4:1]),

    .test_error_event           (error_event_int),

    .test_observe_r_oe_sigs     (r_oe_sigs),

    .test_observe_0_oe_sigs     (6'h00),

    .test_observe_1_oe_sigs     (oe_sigs_1),

    .test_observe_2_oe_sigs     (oe_sigs_2),

    .test_observe_3_oe_sigs     (6'h00),

    .pci_ext_reset_l            (RST),

    .pci_ext_clk                (pci_clock),

    .log_file_desc              (pci_mon_log_file_desc)

) ;

reg [2:0]  test_master_number ;

reg [31:0] test_address ;

reg [3:0]  test_command ;

reg [31:0] test_data ;

reg [3:0]  test_byte_enables_l ;

reg [9:0]  test_size ;

reg        test_make_addr_par_error ;

reg        test_make_data_par_error ;

reg [3:0]  test_master_initial_wait_states ;

reg [3:0]  test_master_subsequent_wait_states ;

reg [3:0]  test_target_initial_wait_states ;

reg [3:0]  test_target_subsequent_wait_states ;

reg [1:0]  test_target_devsel_speed ;

reg        test_fast_back_to_back ;

reg [2:0]  test_target_termination ;

reg        test_expect_master_abort ;

reg        test_start ;

reg [25:0] test_target_response ;

wire [31:0] master2_received_data ;

wire        master2_received_data_valid ;

reg         master2_check_received_data ;

pci_behaviorial_device pci_behaviorial_device2

(

    .pci_ext_ad(AD),

    .pci_ext_cbe_l(CBE),

    .pci_ext_par(PAR),

    .pci_ext_frame_l(FRAME),

    .pci_ext_irdy_l(IRDY),

    .pci_ext_devsel_l(DEVSEL),

    .pci_ext_trdy_l(TRDY),

    .pci_ext_stop_l(STOP),

    .pci_ext_perr_l(PERR),

    .pci_ext_serr_l(SERR),

    .pci_ext_idsel(TAR2_IDSEL),

    .pci_ext_inta_l(INTA),

    .pci_ext_req_l(MAS2_REQ),

    .pci_ext_gnt_l(MAS2_GNT),

    .pci_ext_reset_l(RST),

    .pci_ext_clk(pci_clock),

// Signals used by the test bench instead of using "." notation

    .test_observe_oe_sigs               (oe_sigs_2[5:0]),               //

    .test_master_number                 (test_master_number[2:0]),

    .test_address                       (test_address[PCI_BUS_DATA_RANGE:0]),

    .test_command                       (test_command[3:0]),

    .test_data                          (test_data[PCI_BUS_DATA_RANGE:0]),

    .test_byte_enables_l                (test_byte_enables_l[PCI_BUS_CBE_RANGE:0]),

    .test_size                          (test_size),

    .test_make_addr_par_error           (test_make_addr_par_error),

    .test_make_data_par_error           (test_make_data_par_error),

    .test_master_initial_wait_states    (test_master_initial_wait_states[3:0]),

    .test_master_subsequent_wait_states (test_master_subsequent_wait_states[3:0]),

    .test_target_initial_wait_states    (test_target_initial_wait_states[3:0]),

    .test_target_subsequent_wait_states (test_target_subsequent_wait_states[3:0]),

    .test_target_devsel_speed           (test_target_devsel_speed[1:0]),

    .test_fast_back_to_back             (test_fast_back_to_back),

    .test_target_termination            (test_target_termination[2:0]),

    .test_expect_master_abort           (test_expect_master_abort),

    .test_start                         (test_start),

    .test_accepted_l                    (test_accepted_l_int),

    .test_error_event                   (error_event_int),

    .test_device_id                     (`Test_Master_2),

    .test_target_response               (test_target_response),

    .master_received_data               (master2_received_data),

    .master_received_data_valid         (master2_received_data_valid),

    .master_check_received_data         (master2_check_received_data)

);

wire [31:0] master1_received_data ;

wire        master1_received_data_valid ;

reg         master1_check_received_data ;

pci_behaviorial_device pci_behaviorial_device1

(

    .pci_ext_ad(AD),

    .pci_ext_cbe_l(CBE),

    .pci_ext_par(PAR),

    .pci_ext_frame_l(FRAME),

    .pci_ext_irdy_l(IRDY),

    .pci_ext_devsel_l(DEVSEL),

    .pci_ext_trdy_l(TRDY),

    .pci_ext_stop_l(STOP),

    .pci_ext_perr_l(PERR),

    .pci_ext_serr_l(SERR),

    .pci_ext_idsel(TAR1_IDSEL),

    .pci_ext_inta_l(INTA),

    .pci_ext_req_l(MAS1_REQ),

    .pci_ext_gnt_l(MAS1_GNT),

    .pci_ext_reset_l(RST),

    .pci_ext_clk(pci_clock),

// Signals used by the test bench instead of using "." notation

    .test_observe_oe_sigs           (oe_sigs_1[5:0]),               //

    .test_master_number                 (test_master_number[2:0]),

    .test_address                               (test_address[PCI_BUS_DATA_RANGE:0]),

    .test_command                       (test_command[3:0]),

    .test_data                          (test_data[PCI_BUS_DATA_RANGE:0]),

    .test_byte_enables_l                (test_byte_enables_l[PCI_BUS_CBE_RANGE:0]),

    .test_size                          (test_size),

    .test_make_addr_par_error           (test_make_addr_par_error),

    .test_make_data_par_error           (test_make_data_par_error),

    .test_master_initial_wait_states    (test_master_initial_wait_states[3:0]),

    .test_master_subsequent_wait_states (test_master_subsequent_wait_states[3:0]),

    .test_target_initial_wait_states    (test_target_initial_wait_states[3:0]),

    .test_target_subsequent_wait_states (test_target_subsequent_wait_states[3:0]),

    .test_target_devsel_speed           (test_target_devsel_speed[1:0]),

    .test_fast_back_to_back             (test_fast_back_to_back),

    .test_target_termination            (test_target_termination[2:0]),

    .test_expect_master_abort           (test_expect_master_abort),

    .test_start                         (test_start),

    .test_accepted_l                    (test_accepted_l_int),

    .test_error_event                   (error_event_int),

    .test_device_id                     (`Test_Master_1),

    .test_target_response               (test_target_response),

    .master_received_data               (master1_received_data),

    .master_received_data_valid         (master1_received_data_valid),

    .master_check_received_data         (master1_check_received_data)

);

pci_unsupported_commands_master ipci_unsupported_commands_master

(

    .CLK    ( pci_clock),

    .AD     ( AD ),

    .CBE    ( CBE ),

    .RST    ( RST ),

    .REQ    ( MAS3_REQ ),

    .GNT    ( MAS3_GNT ),

    .FRAME  ( FRAME ),

    .IRDY   ( IRDY ),

    .DEVSEL ( DEVSEL ),

    .TRDY   ( TRDY ),

    .STOP   ( STOP ),

    .PAR    ( PAR )

) ;

`ifdef HOST

reg     [1:0]   conf_cyc_type1_target_response ;

reg     [31:0]  conf_cyc_type1_target_data ;

reg     [7:0]   conf_cyc_type1_target_bus_num ;

wire    [31:0]  conf_cyc_type1_target_data_from_PCI ;

pci_behavioral_pci2pci_bridge i_pci_behavioral_pci2pci_bridge

(

    .CLK              ( pci_clock),

    .AD               ( AD ),

    .CBE              ( CBE ),

    .RST              ( RST ),

    .FRAME            ( FRAME ),

    .IRDY             ( IRDY ),

    .DEVSEL           ( DEVSEL ),

    .TRDY             ( TRDY ),

    .STOP             ( STOP ),

    .PAR              ( PAR ),

    .response         ( conf_cyc_type1_target_response ),

    .data_out         ( conf_cyc_type1_target_data ),

    .data_in          ( conf_cyc_type1_target_data_from_PCI ),

    .devsel_speed     ( test_target_response[`TARGET_ENCODED_DEVSEL_SPEED] ),

    .wait_states      ( test_target_response[`TARGET_ENCODED_INIT_WAITSTATES] ),

    .bus_number       ( conf_cyc_type1_target_bus_num )

);

`endif

// pci clock generator

always

`ifdef PCI33

    #15 pci_clock = ~pci_clock ;

`else

`ifdef PCI66

    #7.5 pci_clock = ~pci_clock ;

`endif

`endif

// WISHBONE clock generation

always

    #(((1/`WB_FREQ)/2)) wb_clock = ~wb_clock ;

// Make test name visible when the Master starts working on it

reg     [79:0] present_test_name;

reg     [79:0] next_test_name;

wire    test_accepted = ~test_accepted_l_int;

always @(posedge test_accepted)

begin

    present_test_name <= next_test_name;

end

reg [31:0] wmem_data [0:1023] ; // data for memory mapped image writes

reg [31:0] wio_data  [0:1023] ; // data for IO mapped image writes

// basic configuration parameters for both behavioral devices

parameter [2:0] Master_ID_A                           = `Test_Master_1;

parameter [PCI_BUS_DATA_RANGE:0] Target_Config_Addr_A = `TAR2_IDSEL_ADDR;

parameter [PCI_BUS_DATA_RANGE:0] Target_Base_Addr_A0  = `BEH_TAR2_MEM_START;

parameter [PCI_BUS_DATA_RANGE:0] Target_Base_Addr_A1  = `BEH_TAR2_IO_START;

parameter [2:0] Master_ID_B                           = `Test_Master_2;

parameter [PCI_BUS_DATA_RANGE:0] Target_Config_Addr_B = `TAR1_IDSEL_ADDR;

parameter [PCI_BUS_DATA_RANGE:0] Target_Base_Addr_B0  = `BEH_TAR1_MEM_START;

parameter [PCI_BUS_DATA_RANGE:0] Target_Base_Addr_B1  = `BEH_TAR1_IO_START;

// basic configuration parameters for REAL device

reg [PCI_BUS_DATA_RANGE:0] Target_Config_Addr_R ;

reg [PCI_BUS_DATA_RANGE:0] Target_Base_Addr_R [0:5];

reg [PCI_BUS_DATA_RANGE:0] Target_Addr_Mask_R [0:5];

reg [PCI_BUS_DATA_RANGE:0] Target_Tran_Addr_R [0:5];

// reg  [2:0]   ack_err_rty_termination ;

// reg          wait_cycles ;

// reg  [7:0]   num_of_retries ;

//reg [19:0] pci_config_base ;

reg [7:0] system_burst_size ;

reg [7:0] bridge_latency ;

integer   target_mem_image ;

integer   target_io_image ;

initial

begin

    next_test_name[79:0] <= "Nowhere___";

    reset = 1'b1 ;

    pci_clock = 1'b0 ;

    wb_clock  = 1'b1 ;

    target_message = 32'h0000_0000 ;

//  num_of_retries = 8'h01 ;

//  ack_err_rty_termination = 3'b100 ;

//  wait_cycles = 1'b0 ;

    // system paameters

    system_burst_size = 16 ;

    bridge_latency    = 8 ;

    // set initial values for controling the behavioral PCI master

    Target_Config_Addr_R  = `TAR0_IDSEL_ADDR ;

    Target_Base_Addr_R[0] = `TAR0_BASE_ADDR_0;

    Target_Base_Addr_R[1] = `TAR0_BASE_ADDR_1;

    Target_Base_Addr_R[2] = `TAR0_BASE_ADDR_2;

    Target_Base_Addr_R[3] = `TAR0_BASE_ADDR_3;

    Target_Base_Addr_R[4] = `TAR0_BASE_ADDR_4;

    Target_Base_Addr_R[5] = `TAR0_BASE_ADDR_5;

    Target_Addr_Mask_R[0] = `TAR0_ADDR_MASK_0;

    Target_Addr_Mask_R[1] = `TAR0_ADDR_MASK_1;

    Target_Addr_Mask_R[2] = `TAR0_ADDR_MASK_2;

    Target_Addr_Mask_R[3] = `TAR0_ADDR_MASK_3;

    Target_Addr_Mask_R[4] = `TAR0_ADDR_MASK_4;

    Target_Addr_Mask_R[5] = `TAR0_ADDR_MASK_5;

    Target_Tran_Addr_R[0] = `TAR0_TRAN_ADDR_0;

    Target_Tran_Addr_R[1] = `TAR0_TRAN_ADDR_1;

    Target_Tran_Addr_R[2] = `TAR0_TRAN_ADDR_2;

    Target_Tran_Addr_R[3] = `TAR0_TRAN_ADDR_3;

    Target_Tran_Addr_R[4] = `TAR0_TRAN_ADDR_4;

    Target_Tran_Addr_R[5] = `TAR0_TRAN_ADDR_5;

    test_master_number = `Test_Master_2 ;

    test_address = 32'h0000_0000 ;

    test_command = `BC_RESERVED0 ;

    test_data = 32'h0000_0000 ;

    test_byte_enables_l   = 4'hF ;

    test_size = 0 ;

    test_make_addr_par_error = 0 ;

    test_make_data_par_error = 0;

    test_master_initial_wait_states = 0 ;

    test_master_subsequent_wait_states = 0 ;

    test_target_initial_wait_states = 0 ;

    test_target_subsequent_wait_states = 0;

    test_target_devsel_speed = `Test_Devsel_Fast ;

    test_fast_back_to_back = 0 ;

    test_target_termination = `Test_Target_Normal_Completion ;

    test_expect_master_abort = 0 ;

    test_start = 0 ;

    test_target_response = 0 ;

    master1_check_received_data = 0 ;