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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_master_behavioral.v"                          ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
`include "pci_testbench_defines.v"
module WB_MASTER_BEHAVIORAL
(
    CLK_I,
    RST_I,
    TAG_I,
    TAG_O,
    ACK_I,
    ADR_O,
    CYC_O,
    DAT_I,
    DAT_O,
    ERR_I,
    RTY_I,
    SEL_O,
    STB_O,
    WE_O,
    CAB_O
);
 
    input                    CLK_I;
    input                    RST_I;
    input    `WB_TAG_TYPE    TAG_I;
    output   `WB_TAG_TYPE    TAG_O;
    input                    ACK_I;
    output   `WB_ADDR_TYPE   ADR_O;
    output                   CYC_O;
    input    `WB_DATA_TYPE   DAT_I;
    output   `WB_DATA_TYPE   DAT_O;
    input                    ERR_I;
    input                    RTY_I;
    output   `WB_SEL_TYPE    SEL_O;
    output                   STB_O;
    output                   WE_O;
    output                   CAB_O;
 
// instantiate low level master module
WB_MASTER32 wbm_low_level
(
    .CLK_I(CLK_I),
    .RST_I(RST_I),
    .TAG_I(TAG_I),
    .TAG_O(TAG_O),
    .ACK_I(ACK_I),
    .ADR_O(ADR_O),
    .CYC_O(CYC_O),
    .DAT_I(DAT_I),
    .DAT_O(DAT_O),
    .ERR_I(ERR_I),
    .RTY_I(RTY_I),
    .SEL_O(SEL_O),
    .STB_O(STB_O),
    .WE_O(WE_O),
    .CAB_O(CAB_O)
) ;
 
// block read and write buffers definition
// single write buffer
reg `WRITE_STIM_TYPE  blk_write_data    [0:(`MAX_BLK_SIZE - 1)] ;
// read stimulus buffer - addresses, tags, selects etc.
reg `READ_STIM_TYPE   blk_read_data_in  [0:(`MAX_BLK_SIZE - 1)] ;
// read return buffer - data and tags received while performing block reads
reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
 
// single write task
task wb_single_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b1, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_write
 
task wb_single_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_read
 
task wb_RMW_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        if (retry === 1)
            wbm_low_level.end_cycle ;
        else
            wbm_low_level.modify_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_read
 
task wb_RMW_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        @(posedge CLK_I) ;
        ok = 1 ;
        if (rty_count !== 0)
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
 
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_write
 
task wb_block_write ;
    input  `WB_TRANSFER_FLAGS write_flags ;
    inout  `WRITE_RETURN_TYPE return ;
 
    reg in_use ;
    reg `WRITE_STIM_TYPE  current_write ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = write_flags`WB_TRANSFER_CAB ;
    wbm_low_level.start_cycle(cab, 1'b1, ok) ;
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = write_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
        wbm_low_level.wbm_write(current_write, return) ;
 
        // check result of write operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = write_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            wbm_low_level.end_cycle ;
            @(posedge CLK_I) ;
            wbm_low_level.start_cycle(cab, 1'b1, ok) ;
            if ( ok !== 1 )
            begin
                $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
                return`TB_ERROR_BIT = 1'b1 ;
                end_blk = 1 ;
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_write
 
task wb_block_read ;
    input  `WB_TRANSFER_FLAGS      read_flags ;
    inout `READ_RETURN_TYPE       return ;
 
    reg in_use ;
    reg `READ_STIM_TYPE  current_read ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
    integer transfered ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    transfered = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = read_flags`WB_TRANSFER_CAB ;
 
    wbm_low_level.start_cycle(cab, 1'b0, ok) ;
 
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = read_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
 
        wbm_low_level.wbm_read(current_read, return) ;
 
        if ( transfered !== return`CYC_ACTUAL_TRANSFER )
        begin
            blk_read_data_out[transfered] = return ;
            transfered = return`CYC_ACTUAL_TRANSFER ;
        end
 
        // check result of read operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = read_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            wbm_low_level.end_cycle ;
            @(posedge CLK_I) ;
            wbm_low_level.start_cycle(cab, 1'b0, ok) ;
            if ( ok !== 1 )
            begin
                $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
                return`TB_ERROR_BIT = 1'b1 ;
                end_blk = 1 ;
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_read
 
endmodule
 

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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_master_behavioral.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//`
38			`// CVS Revision History`
39			`//`
40			`// $Log: not supported by cvs2svn $`
41
42			`include "pci_testbench_defines.v"
43			`module WB_MASTER_BEHAVIORAL`
44			`(`
45			`CLK_I,`
46			`RST_I,`
47			`TAG_I,`
48			`TAG_O,`
49			`ACK_I,`
50			`ADR_O,`
51			`CYC_O,`
52			`DAT_I,`
53			`DAT_O,`
54			`ERR_I,`
55			`RTY_I,`
56			`SEL_O,`
57			`STB_O,`
58			`WE_O,`
59			`CAB_O`
60			`);`
61
62			`input CLK_I;`
63			`input RST_I;`
64			input `WB_TAG_TYPE TAG_I;
65			output `WB_TAG_TYPE TAG_O;
66			`input ACK_I;`
67			output `WB_ADDR_TYPE ADR_O;
68			`output CYC_O;`
69			input `WB_DATA_TYPE DAT_I;
70			output `WB_DATA_TYPE DAT_O;
71			`input ERR_I;`
72			`input RTY_I;`
73			output `WB_SEL_TYPE SEL_O;
74			`output STB_O;`
75			`output WE_O;`
76			`output CAB_O;`
77
78			`// instantiate low level master module`
79			`WB_MASTER32 wbm_low_level`
80			`(`
81			`.CLK_I(CLK_I),`
82			`.RST_I(RST_I),`
83			`.TAG_I(TAG_I),`
84			`.TAG_O(TAG_O),`
85			`.ACK_I(ACK_I),`
86			`.ADR_O(ADR_O),`
87			`.CYC_O(CYC_O),`
88			`.DAT_I(DAT_I),`
89			`.DAT_O(DAT_O),`
90			`.ERR_I(ERR_I),`
91			`.RTY_I(RTY_I),`
92			`.SEL_O(SEL_O),`
93			`.STB_O(STB_O),`
94			`.WE_O(WE_O),`
95			`.CAB_O(CAB_O)`
96			`) ;`
97
98			`// block read and write buffers definition`
99			`// single write buffer`
100			reg `WRITE_STIM_TYPE blk_write_data [0:(`MAX_BLK_SIZE - 1)] ;
101			`// read stimulus buffer - addresses, tags, selects etc.`
102			reg `READ_STIM_TYPE blk_read_data_in [0:(`MAX_BLK_SIZE - 1)] ;
103			`// read return buffer - data and tags received while performing block reads`
104			reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
105
106			`// single write task`
107			`task wb_single_write ;`
108			input `WRITE_STIM_TYPE write_data ;
109			input `WB_TRANSFER_FLAGS write_flags ;
110			inout `WRITE_RETURN_TYPE return ;
111			`reg in_use ;`
112			`reg cab ;`
113			`reg ok ;`
114			`integer cyc_count ;`
115			`integer rty_count ;`
116			`reg retry ;`
117			`begin:main`
118
119			return`TB_ERROR_BIT = 1'b0 ;
120			`cab = 0 ;`
121			return`CYC_ACTUAL_TRANSFER = 0 ;
122			`rty_count = 0 ;`
123
124			`// check if task was called before previous call finished`
125			`if ( in_use === 1 )`
126			`begin`
127			`$display("*E, wb_single_write routine re-entered! Time %t ", $time) ;`
128			return`TB_ERROR_BIT = 1'b1 ;
129			`disable main ;`
130			`end`
131
132			`in_use = 1 ;`
133
134			`retry = 1 ;`
135
136			`while (retry === 1)`
137			`begin`
138			`// synchronize operation to clock`
139			`@(posedge CLK_I) ;`
140
141			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
142			`if ( ok !== 1 )`
143			`begin`
144			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
145			return`TB_ERROR_BIT = 1'b1 ;
146			`disable main ;`
147			`end`
148
149			`// first insert initial wait states`
150			cyc_count = write_flags`INIT_WAITS ;
151			`while ( cyc_count > 0 )`
152			`begin`
153			`@(posedge CLK_I) ;`
154			`cyc_count = cyc_count - 1 ;`
155			`end`
156
157			`wbm_low_level.wbm_write(write_data, return) ;`
158
159			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
160			`begin`
161			if ( rty_count === `WB_TB_MAX_RTY )
162			`begin`
163			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
164			`retry = 0 ;`
165			`end`
166			`else`
167			`begin`
168			`retry = 1 ;`
169			`rty_count = rty_count + 1 ;`
170			`end`
171			`end`
172			`else`
173			`retry = 0 ;`
174
175			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
176			if ( return`TB_ERROR_BIT !== 0 )
177			`begin`
178			`@(posedge CLK_I) ;`
179			`wbm_low_level.end_cycle ;`
180			`disable main ;`
181			`end`
182
183			cyc_count = write_flags`SUBSEQ_WAITS ;
184			`while ( cyc_count > 0 )`
185			`begin`
186			`@(posedge CLK_I) ;`
187			`cyc_count = cyc_count - 1 ;`
188			`end`
189
190			`wbm_low_level.end_cycle ;`
191			`end`
192
193			`in_use = 0 ;`
194
195			`end //main`
196			`endtask // wb_single_write`
197
198			`task wb_single_read ;`
199			input `READ_STIM_TYPE read_data ;
200			input `WB_TRANSFER_FLAGS read_flags ;
201			inout `READ_RETURN_TYPE return ;
202			`reg in_use ;`
203			`reg cab ;`
204			`reg ok ;`
205			`integer cyc_count ;`
206			`integer rty_count ;`
207			`reg retry ;`
208			`begin:main`
209
210			return`TB_ERROR_BIT = 1'b0 ;
211			`cab = 0 ;`
212			`rty_count = 0 ;`
213			return`CYC_ACTUAL_TRANSFER = 0 ;
214
215			`// check if task was called before previous call finished`
216			`if ( in_use === 1 )`
217			`begin`
218			`$display("*E, wb_single_read routine re-entered! Time %t ", $time) ;`
219			return`TB_ERROR_BIT = 1'b1 ;
220			`disable main ;`
221			`end`
222
223			`in_use = 1 ;`
224
225			`retry = 1 ;`
226
227			`while (retry === 1)`
228			`begin`
229			`// synchronize operation to clock`
230			`@(posedge CLK_I) ;`
231
232			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
233			`if ( ok !== 1 )`
234			`begin`
235			`$display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;`
236			return`TB_ERROR_BIT = 1'b1 ;
237			`disable main ;`
238			`end`
239
240			`// first insert initial wait states`
241			cyc_count = read_flags`INIT_WAITS ;
242			`while ( cyc_count > 0 )`
243			`begin`
244			`@(posedge CLK_I) ;`
245			`cyc_count = cyc_count - 1 ;`
246			`end`
247
248			`wbm_low_level.wbm_read(read_data, return) ;`
249
250			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
251			`begin`
252			if ( rty_count === `WB_TB_MAX_RTY )
253			`begin`
254			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;`
255			`retry = 0 ;`
256			`end`
257			`else`
258			`begin`
259			`retry = 1 ;`
260			`rty_count = rty_count + 1 ;`
261			`end`
262			`end`
263			`else`
264			`begin`
265			`retry = 0 ;`
266			`end`
267
268			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
269			if ( return`TB_ERROR_BIT !== 0 )
270			`begin`
271			`@(posedge CLK_I) ;`
272			`wbm_low_level.end_cycle ;`
273			`disable main ;`
274			`end`
275
276			cyc_count = read_flags`SUBSEQ_WAITS ;
277			`while ( cyc_count > 0 )`
278			`begin`
279			`@(posedge CLK_I) ;`
280			`cyc_count = cyc_count - 1 ;`
281			`end`
282
283			`wbm_low_level.end_cycle ;`
284			`end`
285
286			`in_use = 0 ;`
287
288			`end //main`
289			`endtask // wb_single_read`
290
291			`task wb_RMW_read ;`
292			input `READ_STIM_TYPE read_data ;
293			input `WB_TRANSFER_FLAGS read_flags ;
294			inout `READ_RETURN_TYPE return ;
295			`reg in_use ;`
296			`reg cab ;`
297			`reg ok ;`
298			`integer cyc_count ;`
299			`integer rty_count ;`
300			`reg retry ;`
301			`begin:main`
302
303			return`TB_ERROR_BIT = 1'b0 ;
304			`cab = 0 ;`
305			`rty_count = 0 ;`
306			return`CYC_ACTUAL_TRANSFER = 0 ;
307
308			`// check if task was called before previous call finished`
309			`if ( in_use === 1 )`
310			`begin`
311			`$display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;`
312			return`TB_ERROR_BIT = 1'b1 ;
313			`disable main ;`
314			`end`
315
316			`in_use = 1 ;`
317
318			`retry = 1 ;`
319
320			`while (retry === 1)`
321			`begin`
322			`// synchronize operation to clock`
323			`@(posedge CLK_I) ;`
324
325			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
326			`if ( ok !== 1 )`
327			`begin`
328			`$display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;`
329			return`TB_ERROR_BIT = 1'b1 ;
330			`disable main ;`
331			`end`
332
333			`// first insert initial wait states`
334			cyc_count = read_flags`INIT_WAITS ;
335			`while ( cyc_count > 0 )`
336			`begin`
337			`@(posedge CLK_I) ;`
338			`cyc_count = cyc_count - 1 ;`
339			`end`
340
341			`wbm_low_level.wbm_read(read_data, return) ;`
342
343			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
344			`begin`
345			if ( rty_count === `WB_TB_MAX_RTY )
346			`begin`
347			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;`
348			`retry = 0 ;`
349			`end`
350			`else`
351			`begin`
352			`retry = 1 ;`
353			`rty_count = rty_count + 1 ;`
354			`end`
355			`end`
356			`else`
357			`begin`
358			`retry = 0 ;`
359			`end`
360
361			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
362			if ( return`TB_ERROR_BIT !== 0 )
363			`begin`
364			`@(posedge CLK_I) ;`
365			`wbm_low_level.end_cycle ;`
366			`disable main ;`
367			`end`
368
369			cyc_count = read_flags`SUBSEQ_WAITS ;
370			`while ( cyc_count > 0 )`
371			`begin`
372			`@(posedge CLK_I) ;`
373			`cyc_count = cyc_count - 1 ;`
374			`end`
375
376			`if (retry === 1)`
377			`wbm_low_level.end_cycle ;`
378			`else`
379			`wbm_low_level.modify_cycle ;`
380			`end`
381
382			`in_use = 0 ;`
383
384			`end //main`
385			`endtask // wb_RMW_read`
386
387			`task wb_RMW_write ;`
388			input `WRITE_STIM_TYPE write_data ;
389			input `WB_TRANSFER_FLAGS write_flags ;
390			inout `WRITE_RETURN_TYPE return ;
391			`reg in_use ;`
392			`reg cab ;`
393			`reg ok ;`
394			`integer cyc_count ;`
395			`integer rty_count ;`
396			`reg retry ;`
397			`begin:main`
398
399			return`TB_ERROR_BIT = 1'b0 ;
400			`cab = 0 ;`
401			return`CYC_ACTUAL_TRANSFER = 0 ;
402			`rty_count = 0 ;`
403
404			`// check if task was called before previous call finished`
405			`if ( in_use === 1 )`
406			`begin`
407			`$display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;`
408			return`TB_ERROR_BIT = 1'b1 ;
409			`disable main ;`
410			`end`
411
412			`in_use = 1 ;`
413
414			`retry = 1 ;`
415
416			`while (retry === 1)`
417			`begin`
418			`// synchronize operation to clock`
419			`@(posedge CLK_I) ;`
420			`ok = 1 ;`
421			`if (rty_count !== 0)`
422			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
423
424			`if ( ok !== 1 )`
425			`begin`
426			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
427			return`TB_ERROR_BIT = 1'b1 ;
428			`disable main ;`
429			`end`
430
431			`// first insert initial wait states`
432			cyc_count = write_flags`INIT_WAITS ;
433			`while ( cyc_count > 0 )`
434			`begin`
435			`@(posedge CLK_I) ;`
436			`cyc_count = cyc_count - 1 ;`
437			`end`
438
439			`wbm_low_level.wbm_write(write_data, return) ;`
440
441			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
442			`begin`
443			if ( rty_count === `WB_TB_MAX_RTY )
444			`begin`
445			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
446			`retry = 0 ;`
447			`end`
448			`else`
449			`begin`
450			`retry = 1 ;`
451			`rty_count = rty_count + 1 ;`
452			`end`
453			`end`
454			`else`
455			`retry = 0 ;`
456
457			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
458			if ( return`TB_ERROR_BIT !== 0 )
459			`begin`
460			`@(posedge CLK_I) ;`
461			`wbm_low_level.end_cycle ;`
462			`disable main ;`
463			`end`
464
465			cyc_count = write_flags`SUBSEQ_WAITS ;
466			`while ( cyc_count > 0 )`
467			`begin`
468			`@(posedge CLK_I) ;`
469			`cyc_count = cyc_count - 1 ;`
470			`end`
471
472			`wbm_low_level.end_cycle ;`
473			`end`
474
475			`in_use = 0 ;`
476
477			`end //main`
478			`endtask // wb_RMW_write`
479
480			`task wb_block_write ;`
481			input `WB_TRANSFER_FLAGS write_flags ;
482			inout `WRITE_RETURN_TYPE return ;
483
484			`reg in_use ;`
485			reg `WRITE_STIM_TYPE current_write ;
486			`reg cab ;`
487			`reg ok ;`
488			`integer cyc_count ;`
489			`integer rty_count ;`
490			`reg end_blk ;`
491			`begin:main`
492
493			return`CYC_ACTUAL_TRANSFER = 0 ;
494			`rty_count = 0 ;`
495
496			`// check if task was called before previous call finished`
497			`if ( in_use === 1 )`
498			`begin`
499			`$display("*E, wb_block_write routine re-entered! Time %t ", $time) ;`
500			return`TB_ERROR_BIT = 1'b1 ;
501			`disable main ;`
502			`end`
503
504			if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
505			`begin`
506			`$display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;`
507			return`TB_ERROR_BIT = 1'b1 ;
508			`disable main ;`
509			`end`
510
511			`in_use = 1 ;`
512			`@(posedge CLK_I) ;`
513			cab = write_flags`WB_TRANSFER_CAB ;
514			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
515			`if ( ok !== 1 )`
516			`begin`
517			`$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;`
518			return`TB_ERROR_BIT = 1'b1 ;
519			`disable main ;`
520			`end`
521
522			`// insert initial wait states`
523			cyc_count = write_flags`INIT_WAITS ;
524			`while ( cyc_count > 0 )`
525			`begin`
526			`@(posedge CLK_I) ;`
527			`cyc_count = cyc_count - 1 ;`
528			`end`
529
530			`end_blk = 0 ;`
531			`while (end_blk === 0)`
532			`begin`
533			`// collect data for current data beat`
534			current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
535			`wbm_low_level.wbm_write(current_write, return) ;`
536
537			`// check result of write operation`
538			`// check for severe test error`
539			if (return`TB_ERROR_BIT !== 0)
540			`begin`
541			`@(posedge CLK_I) ;`
542			`wbm_low_level.end_cycle ;`
543			`disable main ;`
544			`end`
545
546			`// slave returned error or error signal had invalid value`
547			if (return`CYC_ERR !== 0)
548			`end_blk = 1 ;`
549
550			`if (`
551			(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) \|\|
552			(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) \|\|
553			(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
554			`)`
555			`begin`
556			`end_blk = 1 ;`
557			`$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;`
558			$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
559			`end`
560
561			if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
562			`end_blk = 1 ;`
563
564			if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
565			`begin`
566			if ( rty_count === `WB_TB_MAX_RTY )
567			`begin`
568			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;`
569			`end_blk = 1 ;`
570			`end`
571			`else`
572			`begin`
573			`rty_count = rty_count + 1 ;`
574			`end`
575			`end`
576			`else`
577			`rty_count = 0 ;`
578
579			`// check if slave responded at all`
580			if (return`CYC_RESPONSE === 0)
581			`end_blk = 1 ;`
582
583			`// check if all intended data was transfered`
584			if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
585			`end_blk = 1 ;`
586
587			`// insert subsequent wait cycles, if transfer is supposed to continue`
588			`if ( end_blk === 0 )`
589			`begin`
590			cyc_count = write_flags`SUBSEQ_WAITS ;
591			`while ( cyc_count > 0 )`
592			`begin`
593			`@(posedge CLK_I) ;`
594			`cyc_count = cyc_count - 1 ;`
595			`end`
596			`end`
597
598			if ( (end_blk === 0) && (return`CYC_RTY === 1) )
599			`begin`
600			`wbm_low_level.end_cycle ;`
601			`@(posedge CLK_I) ;`
602			`wbm_low_level.start_cycle(cab, 1'b1, ok) ;`
603			`if ( ok !== 1 )`
604			`begin`
605			`$display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;`
606			return`TB_ERROR_BIT = 1'b1 ;
607			`end_blk = 1 ;`
608			`end`
609			`end`
610			`end //while`
611
612			`wbm_low_level.end_cycle ;`
613			`in_use = 0 ;`
614			`end //main`
615			`endtask //wb_block_write`
616
617			`task wb_block_read ;`
618			input `WB_TRANSFER_FLAGS read_flags ;
619			inout `READ_RETURN_TYPE return ;
620
621			`reg in_use ;`
622			reg `READ_STIM_TYPE current_read ;
623			`reg cab ;`
624			`reg ok ;`
625			`integer cyc_count ;`
626			`integer rty_count ;`
627			`reg end_blk ;`
628			`integer transfered ;`
629			`begin:main`
630
631			return`CYC_ACTUAL_TRANSFER = 0 ;
632			`transfered = 0 ;`
633			`rty_count = 0 ;`
634
635			`// check if task was called before previous call finished`
636			`if ( in_use === 1 )`
637			`begin`
638			`$display("*E, wb_block_read routine re-entered! Time %t ", $time) ;`
639			return`TB_ERROR_BIT = 1'b1 ;
640			`disable main ;`
641			`end`
642
643			if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
644			`begin`
645			`$display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;`
646			return`TB_ERROR_BIT = 1'b1 ;
647			`disable main ;`
648			`end`
649
650			`in_use = 1 ;`
651			`@(posedge CLK_I) ;`
652			cab = read_flags`WB_TRANSFER_CAB ;
653
654			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
655
656			`if ( ok !== 1 )`
657			`begin`
658			`$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;`
659			return`TB_ERROR_BIT = 1'b1 ;
660			`disable main ;`
661			`end`
662
663			`// insert initial wait states`
664			cyc_count = read_flags`INIT_WAITS ;
665			`while ( cyc_count > 0 )`
666			`begin`
667			`@(posedge CLK_I) ;`
668			`cyc_count = cyc_count - 1 ;`
669			`end`
670
671			`end_blk = 0 ;`
672			`while (end_blk === 0)`
673			`begin`
674			`// collect data for current data beat`
675			current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
676
677			`wbm_low_level.wbm_read(current_read, return) ;`
678
679			if ( transfered !== return`CYC_ACTUAL_TRANSFER )
680			`begin`
681			`blk_read_data_out[transfered] = return ;`
682			transfered = return`CYC_ACTUAL_TRANSFER ;
683			`end`
684
685			`// check result of read operation`
686			`// check for severe test error`
687			if (return`TB_ERROR_BIT !== 0)
688			`begin`
689			`@(posedge CLK_I) ;`
690			`wbm_low_level.end_cycle ;`
691			`disable main ;`
692			`end`
693
694			`// slave returned error or error signal had invalid value`
695			if (return`CYC_ERR !== 0)
696			`end_blk = 1 ;`
697
698			`if (`
699			(return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) \|\|
700			(return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) \|\|
701			(return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
702			`)`
703			`begin`
704			`end_blk = 1 ;`
705			`$display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;`
706			$display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
707			`end`
708
709			if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
710			`end_blk = 1 ;`
711
712			if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
713			`begin`
714			if ( rty_count === `WB_TB_MAX_RTY )
715			`begin`
716			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;`
717			`end_blk = 1 ;`
718			`end`
719			`else`
720			`begin`
721			`rty_count = rty_count + 1 ;`
722			`end`
723			`end`
724			`else`
725			`rty_count = 0 ;`
726
727			`// check if slave responded at all`
728			if (return`CYC_RESPONSE === 0)
729			`end_blk = 1 ;`
730
731			`// check if all intended data was transfered`
732			if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
733			`end_blk = 1 ;`
734
735			`// insert subsequent wait cycles, if transfer is supposed to continue`
736			`if ( end_blk === 0 )`
737			`begin`
738			cyc_count = read_flags`SUBSEQ_WAITS ;
739			`while ( cyc_count > 0 )`
740			`begin`
741			`@(posedge CLK_I) ;`
742			`cyc_count = cyc_count - 1 ;`
743			`end`
744			`end`
745
746			if ( (end_blk === 0) && (return`CYC_RTY === 1) )
747			`begin`
748			`wbm_low_level.end_cycle ;`
749			`@(posedge CLK_I) ;`
750			`wbm_low_level.start_cycle(cab, 1'b0, ok) ;`
751			`if ( ok !== 1 )`
752			`begin`
753			`$display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;`
754			return`TB_ERROR_BIT = 1'b1 ;
755			`end_blk = 1 ;`
756			`end`
757			`end`
758			`end //while`
759
760			`wbm_low_level.end_cycle ;`
761			`in_use = 0 ;`
762			`end //main`
763			`endtask //wb_block_read`
764
765			`endmodule`
766