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tadejm |
##############################################
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# BASIC UCF SYNTAX EXAMPLES V2.1.6 #
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##############################################
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#
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# The "#" symbol is a comment character. To use this sample file, find the
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# specification necessary, remove the comment character (#) from the beginning
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# of the line, and modify the line (if necessary) to fit your design.
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#
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# TIMING SPECIFICATIONS
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#
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# Timing specifications can be applied to the entire device (global) or to
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# specific groups in your design (called "time groups'). The time groups are
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# declared in two basic ways.
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#
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# Method 1: Based on a net name, where 'my_net' is a net that touches all the
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# logic to be grouped in to 'logic_grp'. Example:
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#NET my_net TNM_NET = logic_grp ;
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#
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# Method 2: Group using the key word 'TIMEGRP' and declare using the names of
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# logic in your design. Example:
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#TIMEGRP group_name = FFS ("U1/*");
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# creates a group called 'group_name' for all flip-flops within
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# the hierarchical block called U1. Wildcards are valid.
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#
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# Grouping is very important because it lets you tell the software which parts
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# of a design run at which speeds. For the majority of the designs with only
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# one clock, use simple global constraints.
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#
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# The type of grouping constraint you use can vary depending on the synthesis
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# tools you are using. Foundation Express does better with Method 2.
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#
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#
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############################################################
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# Internal to the device clock speed specifications - Tsys #
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############################################################
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#
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# data _________ /^^^^^\ _________ out
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# ----------| D Q |-----{ LOGIC } -----| D Q |------
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# | | \vvvvv/ | |
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# ---|> CLK | ---|> CLK |
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# clock | --------- | ---------
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# ------------------------------------
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#
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# ---------------
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# Single Clock
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# ---------------
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#
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# ----------------
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# PERIOD TIME-SPEC
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# ----------------
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# The PERIOD spec. covers all timing paths that start or end at a
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# register, latch, or synchronous RAM which are clocked by the reference
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# net (excluding pad destinations). Also covered is the setup
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# requirement of the synchronous element relative to other elements
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# (ex. flip flops, pads, etc...).
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# NOTE: The default unit for time is nanoseconds.
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#
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#NET clock PERIOD = 50ns ;
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#
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# -OR-
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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# FROM:TO style timespecs can be used to constrain paths between time
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# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined
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# time groups used to specify all elements of each type in a design.
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#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS
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#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS
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#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge
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#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge
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#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge
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#
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# ---------------
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# Multiple Clocks
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# ---------------
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# Requires a combination of the 'Period' and 'FROM:TO' type time specifications
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#NET clock1 TNM_NET = clk1_grp ;
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#NET clock2 TNM_NET = clk2_grp ;
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#
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#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ;
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#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ;
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#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ;
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#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ;
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#
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#
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############################################################
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# CLOCK TO OUT specifications - Tco #
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############################################################
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#
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# from _________ /^^^^^\ --------\
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# ----------| D Q |-----{ LOGIC } -----| Pad >
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# PLD | | \vvvvv/ --------/
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# ---|> CLK |
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# clock | ---------
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# --------
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#
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# ----------------
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# OFFSET TIME-SPEC
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# ----------------
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# To automatically include clock buffer/routing delay in your
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# clock-to-out timing specifications, use OFFSET constraints .
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# For an output where the maximum clock-to-out (Tco) is 25 ns:
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#
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#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ;
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#
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# -OR-
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns;
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# Note that FROM: FFS : TO: PADS constraints start the delay analysis
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# at the flip flop itself, and not the clock input pin. The recommended
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# method to create a clock-to-out constraint is to use an OFFSET constraint.
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#
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#
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############################################################
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# Pad to Flip-Flop speed specifications - Tsu #
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############################################################
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#
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# ------\ /^^^^^\ _________ into PLD
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# |pad >-------{ LOGIC } -----| D Q |------
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# ------/ \vvvvv/ | |
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# ---|> CLK |
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# clock | ---------
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# ----------------------------
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#
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# ----------------
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# OFFSET TIME-SPEC
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# ----------------
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# To automatically account for clock delay in your input setup timing
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# specifications, use OFFSET constraints.
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# For an input where the maximum setup time is 25 ns:
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#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ;
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#
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# -OR-
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns;
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# Note that FROM: PADS : TO: FFS constraints do not take into account any
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# delay for the clock path. The recommended method to create an input
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# setup time constraint is to use an OFFSET constraint.
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#
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#
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############################################################
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# Pad to Pad speed specifications - Tpd #
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############################################################
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#
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# ------\ /^^^^^\ -------\
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# |pad >-------{ LOGIC } -----| pad >
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# ------/ \vvvvv/ -------/
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns;
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#
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#
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############################################################
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# Other timing specifications #
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############################################################
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#
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# -------------
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# TIMING IGNORE
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# -------------
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# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
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# "*" character is a wild card, which can be used for bus names. A "?"
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# character can be used to wild-card one character.
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# Ignore timing of net reset_n:
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#NET : reset_n : TIG ;
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#
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# Ignore data_reg(7:0) net in instance mux_mem:
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#NET : mux_mem/data_reg* : TIG ;
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#
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# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
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# named TS01 only:
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#NET : mux_mem/data_reg* : TIG = TS01 ;
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#
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# Ignore data1_sig and data2_sig nets:
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#NET : data?_sig : TIG ;
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#
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# ---------------
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# PATH EXCEPTIONS
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# ---------------
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# If your design has outputs that can be slower than others, you can
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# create specific timespecs similar to this example for output nets
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# named out_data(7:0) and irq_n:
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#TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
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#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
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#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
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#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;
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#
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# If you have multi-cycle FF to FF paths, you can create a time group
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# using either the TIMEGRP or TNM statements.
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#
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# WARNING: Many VHDL/Verilog synthesizers do not predictably name flip
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# flop Q output nets. Most synthesizers do assign predictable instance
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# names to flip flops, however.
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#
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# TIMEGRP example:
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#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
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#inst_path/ff_q_output_net2*);
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#
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# TNM attached to instance example:
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#INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
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#INST inst_path/ff_instance_name2_reg* TNM = slowffs ;
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#
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# If a FF clock-enable is used on all flip flops of a multi-cycle path,
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# you can attach TNM to the clock enable net. NOTE: TNM attached to a
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# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
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# net.
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#NET ff_clock_enable_net TNM = slowffs ;
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#
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# Example of using "slowffs" timegroup, in a FROM:TO timespec, with
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# either of the three timegroup methods shown above:
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#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;
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#
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# Constrain the skew or delay associate with a net.
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#NET any_net_name MAXSKEW = 7 ;
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#NET any_net_name MAXDELAY = 20 ns;
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#
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#
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# Constraint priority in your .ucf file is as follows:
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#
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# highest 1. Timing Ignore (TIG)
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# 2. FROM : THRU : TO specs
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# 3. FROM : TO specs
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# lowest 4. PERIOD specs
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#
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# See the on-line "Library Reference Guide" document for
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# additional timespec features and more information.
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#
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#
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############################################################
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# #
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# LOCATION and ATTRIBUTE SPECIFICATIONS #
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# #
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############################################################
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# Pin and CLB location locking constraints #
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############################################################
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#
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# -----------------------
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# Assign an IO pin number
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# -----------------------
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#INST io_buf_instance_name LOC = P110 ;
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#NET io_net_name LOC = P111 ;
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#
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# -----------------------
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# Assign a signal to a range of I/O pins
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# -----------------------
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#NET "signal_name" LOC=P32, P33, P34;
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#
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# -----------------------
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# Place a logic element(called a BEL) in a specific CLB location.
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# BEL = FF, LUT, RAM, etc...
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# -----------------------
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#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ;
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#
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# -----------------------
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# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
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# -----------------------
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#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;
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#
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# -----------------------
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# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7
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# -----------------------
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#INST /U1* LOC=clb_r1c1:clb_r5c7;
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#
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# -----------------------
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# Prohibit IO pin P26 or CLBR5C3 from being used:
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# -----------------------
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#CONFIG PROHIBIT = P26 ;
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#CONFIG PROHIBIT = CLB_R5C3 ;
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# Config Prohibit is very important for forcing the software to not use critical
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# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG
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# Pins require a special pad so they will not be available to this constraint
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#
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# -----------------------
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# Assign an OBUF to be FAST or SLOW:
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# -----------------------
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#INST obuf_instance_name FAST ;
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#INST obuf_instance_name SLOW ;
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#
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# -----------------------
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# FPGAs only: IOB input Flip-flop delay specification
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# -----------------------
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# Declare an IOB input FF delay (default = MAXDELAY).
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# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
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# into an IOB by the "map -pr i" option.
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#INST input_ff_instance_name MEDDELAY ;
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#INST input_ff_instance_name NODELAY ;
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#
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# -----------------------
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# Assign Global Clock Buffers Lower Left Right Side
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# -----------------------
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# INST gbuf1 LOC=SSW
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#
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# #
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################################################################################
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# Define Device, Package, And Speed Grade
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################################################################################
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#
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CONFIG PART = XC2S200-FG456-5 ;
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#
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################################################################################
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# Prohibited Pins List
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################################################################################
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#
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CONFIG PROHIBIT = "A20" ; #IO_WRITE
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CONFIG PROHIBIT = "C19" ; #IO_CS
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CONFIG PROHIBIT = "C21" ; #IO_DOUT_BUSY
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CONFIG PROHIBIT = "D20" ; #IO_DIN_D0
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CONFIG PROHIBIT = "H22" ; #IO_D1
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CONFIG PROHIBIT = "H20" ; #IO_D2
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CONFIG PROHIBIT = "K20" ; #IO_D3
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#CONFIG PROHIBIT = "N22" ; #IO_D4
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CONFIG PROHIBIT = "R21" ; #IO_D5
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CONFIG PROHIBIT = "T22" ; #IO_D6
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CONFIG PROHIBIT = "Y21" ; #IO_D7
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CONFIG PROHIBIT = "V19" ; #IO_INIT
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|
| 326 |
|
|
NET "CLK" IOSTANDARD = PCI33_5 ;
|
| 327 |
|
|
NET "CLK" TNM_NET = "CLK";
|
| 328 |
|
|
NET "CRT_CLK" TNM_NET = "CRT_CLK";
|
| 329 |
|
|
|
| 330 |
|
|
TIMESPEC "TS_CLK" = PERIOD "CLK" 30 ns HIGH 50 %;
|
| 331 |
|
|
TIMESPEC "TS_CRT_CLK" = PERIOD "CRT_CLK" 44 ns HIGH 50 %;
|
| 332 |
|
|
TIMESPEC "TS_CLK_2_CRT_CLK" = FROM : "CLK" : TO : "CRT_CLK" : 15 ;
|
| 333 |
|
|
TIMESPEC "TS_CRT_CLK_2_CLK" = FROM : "CRT_CLK" : TO : "CLK" : 15 ;
|
| 334 |
|
|
|
| 335 |
|
|
INST "AD0.PAD" TNM = "PCI_AD";
|
| 336 |
|
|
INST "AD1.PAD" TNM = "PCI_AD";
|
| 337 |
|
|
INST "AD2.PAD" TNM = "PCI_AD";
|
| 338 |
|
|
INST "AD3.PAD" TNM = "PCI_AD";
|
| 339 |
|
|
INST "AD4.PAD" TNM = "PCI_AD";
|
| 340 |
|
|
INST "AD5.PAD" TNM = "PCI_AD";
|
| 341 |
|
|
INST "AD6.PAD" TNM = "PCI_AD";
|
| 342 |
|
|
INST "AD7.PAD" TNM = "PCI_AD";
|
| 343 |
|
|
INST "AD8.PAD" TNM = "PCI_AD";
|
| 344 |
|
|
INST "AD9.PAD" TNM = "PCI_AD";
|
| 345 |
|
|
INST "AD10.PAD" TNM = "PCI_AD";
|
| 346 |
|
|
INST "AD11.PAD" TNM = "PCI_AD";
|
| 347 |
|
|
INST "AD12.PAD" TNM = "PCI_AD";
|
| 348 |
|
|
INST "AD13.PAD" TNM = "PCI_AD";
|
| 349 |
|
|
INST "AD14.PAD" TNM = "PCI_AD";
|
| 350 |
|
|
INST "AD15.PAD" TNM = "PCI_AD";
|
| 351 |
|
|
INST "AD16.PAD" TNM = "PCI_AD";
|
| 352 |
|
|
INST "AD17.PAD" TNM = "PCI_AD";
|
| 353 |
|
|
INST "AD18.PAD" TNM = "PCI_AD";
|
| 354 |
|
|
INST "AD19.PAD" TNM = "PCI_AD";
|
| 355 |
|
|
INST "AD20.PAD" TNM = "PCI_AD";
|
| 356 |
|
|
INST "AD21.PAD" TNM = "PCI_AD";
|
| 357 |
|
|
INST "AD22.PAD" TNM = "PCI_AD";
|
| 358 |
|
|
INST "AD23.PAD" TNM = "PCI_AD";
|
| 359 |
|
|
INST "AD24.PAD" TNM = "PCI_AD";
|
| 360 |
|
|
INST "AD25.PAD" TNM = "PCI_AD";
|
| 361 |
|
|
INST "AD26.PAD" TNM = "PCI_AD";
|
| 362 |
|
|
INST "AD27.PAD" TNM = "PCI_AD";
|
| 363 |
|
|
INST "AD28.PAD" TNM = "PCI_AD";
|
| 364 |
|
|
INST "AD29.PAD" TNM = "PCI_AD";
|
| 365 |
|
|
INST "AD30.PAD" TNM = "PCI_AD";
|
| 366 |
|
|
INST "AD31.PAD" TNM = "PCI_AD";
|
| 367 |
|
|
TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK";
|
| 368 |
|
|
TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK";
|
| 369 |
|
|
NET "AD0" IOSTANDARD = PCI33_5;
|
| 370 |
|
|
NET "AD1" IOSTANDARD = PCI33_5;
|
| 371 |
|
|
NET "AD2" IOSTANDARD = PCI33_5;
|
| 372 |
|
|
NET "AD3" IOSTANDARD = PCI33_5;
|
| 373 |
|
|
NET "AD4" IOSTANDARD = PCI33_5;
|
| 374 |
|
|
NET "AD5" IOSTANDARD = PCI33_5;
|
| 375 |
|
|
NET "AD6" IOSTANDARD = PCI33_5;
|
| 376 |
|
|
NET "AD7" IOSTANDARD = PCI33_5;
|
| 377 |
|
|
NET "AD8" IOSTANDARD = PCI33_5;
|
| 378 |
|
|
NET "AD9" IOSTANDARD = PCI33_5;
|
| 379 |
|
|
NET "AD10" IOSTANDARD = PCI33_5;
|
| 380 |
|
|
NET "AD11" IOSTANDARD = PCI33_5;
|
| 381 |
|
|
NET "AD12" IOSTANDARD = PCI33_5;
|
| 382 |
|
|
NET "AD13" IOSTANDARD = PCI33_5;
|
| 383 |
|
|
NET "AD14" IOSTANDARD = PCI33_5;
|
| 384 |
|
|
NET "AD15" IOSTANDARD = PCI33_5;
|
| 385 |
|
|
NET "AD16" IOSTANDARD = PCI33_5;
|
| 386 |
|
|
NET "AD17" IOSTANDARD = PCI33_5;
|
| 387 |
|
|
NET "AD18" IOSTANDARD = PCI33_5;
|
| 388 |
|
|
NET "AD19" IOSTANDARD = PCI33_5;
|
| 389 |
|
|
NET "AD20" IOSTANDARD = PCI33_5;
|
| 390 |
|
|
NET "AD21" IOSTANDARD = PCI33_5;
|
| 391 |
|
|
NET "AD22" IOSTANDARD = PCI33_5;
|
| 392 |
|
|
NET "AD23" IOSTANDARD = PCI33_5;
|
| 393 |
|
|
NET "AD24" IOSTANDARD = PCI33_5;
|
| 394 |
|
|
NET "AD25" IOSTANDARD = PCI33_5;
|
| 395 |
|
|
NET "AD26" IOSTANDARD = PCI33_5;
|
| 396 |
|
|
NET "AD27" IOSTANDARD = PCI33_5;
|
| 397 |
|
|
NET "AD28" IOSTANDARD = PCI33_5;
|
| 398 |
|
|
NET "AD29" IOSTANDARD = PCI33_5;
|
| 399 |
|
|
NET "AD30" IOSTANDARD = PCI33_5;
|
| 400 |
|
|
NET "AD31" IOSTANDARD = PCI33_5;
|
| 401 |
|
|
INST "CBE0.PAD" TNM = "PCI_CBE";
|
| 402 |
|
|
INST "CBE1.PAD" TNM = "PCI_CBE";
|
| 403 |
|
|
INST "CBE2.PAD" TNM = "PCI_CBE";
|
| 404 |
|
|
INST "CBE3.PAD" TNM = "PCI_CBE";
|
| 405 |
|
|
|
| 406 |
|
|
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK";
|
| 407 |
|
|
TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK";
|
| 408 |
|
|
|
| 409 |
|
|
NET "CBE0" IOSTANDARD = PCI33_5;
|
| 410 |
|
|
NET "CBE1" IOSTANDARD = PCI33_5;
|
| 411 |
|
|
NET "CBE2" IOSTANDARD = PCI33_5;
|
| 412 |
|
|
NET "CBE3" IOSTANDARD = PCI33_5;
|
| 413 |
|
|
|
| 414 |
|
|
#INST "DEVSEL.PAD" TNM = "PCI_CTRL" ;
|
| 415 |
|
|
|
| 416 |
|
|
NET "DEVSEL" OFFSET = IN 7 ns BEFORE "CLK";
|
| 417 |
|
|
|
| 418 |
|
|
NET "DEVSEL" OFFSET = OUT 11 ns AFTER "CLK";
|
| 419 |
|
|
|
| 420 |
|
|
NET "DEVSEL" IOSTANDARD = PCI33_5;
|
| 421 |
|
|
|
| 422 |
|
|
NET "FRAME" OFFSET = IN 7 ns BEFORE "CLK";
|
| 423 |
|
|
|
| 424 |
|
|
NET "FRAME" OFFSET = OUT 11 ns AFTER "CLK";
|
| 425 |
|
|
|
| 426 |
|
|
NET "FRAME" IOSTANDARD = PCI33_5;
|
| 427 |
|
|
|
| 428 |
|
|
#INST "FRAME.PAD" TNM = "PCI_CTRL" ;
|
| 429 |
|
|
|
| 430 |
|
|
NET "GNT" OFFSET = IN 10 ns BEFORE "CLK";
|
| 431 |
|
|
|
| 432 |
|
|
NET "GNT" IOSTANDARD = PCI33_5;
|
| 433 |
|
|
NET "RST" IOSTANDARD = PCI33_5;
|
| 434 |
|
|
NET "INTA" IOSTANDARD = PCI33_5;
|
| 435 |
|
|
|
| 436 |
|
|
#INST "GNT.PAD" TNM = "PCI_GNT" ;
|
| 437 |
|
|
|
| 438 |
|
|
NET "IRDY" OFFSET = IN 7 ns BEFORE "CLK";
|
| 439 |
|
|
NET "IRDY" OFFSET = OUT 11 ns AFTER "CLK";
|
| 440 |
|
|
|
| 441 |
|
|
NET "IRDY" IOSTANDARD = PCI33_5;
|
| 442 |
|
|
|
| 443 |
|
|
#INST "IRDY.PAD" TNM="PCI_CTRL" ;
|
| 444 |
|
|
|
| 445 |
|
|
NET "PAR" OFFSET = IN 7 ns BEFORE "CLK";
|
| 446 |
|
|
NET "PAR" OFFSET = OUT 11 ns AFTER "CLK";
|
| 447 |
|
|
|
| 448 |
|
|
NET "PAR" IOSTANDARD = PCI33_5;
|
| 449 |
|
|
|
| 450 |
|
|
#INST "PAR.PAD" TNM = "PCI_CTRL" ;
|
| 451 |
|
|
|
| 452 |
|
|
NET "PERR" OFFSET = IN 7 ns BEFORE "CLK";
|
| 453 |
|
|
|
| 454 |
|
|
NET "PERR" OFFSET = OUT 11 ns AFTER "CLK";
|
| 455 |
|
|
|
| 456 |
|
|
NET "PERR" IOSTANDARD = PCI33_5;
|
| 457 |
|
|
|
| 458 |
|
|
#INST "PERR.PAD" TNM = "PCI_CTRL" ;
|
| 459 |
|
|
|
| 460 |
|
|
NET "REQ" OFFSET = OUT 12 ns AFTER "CLK";
|
| 461 |
|
|
|
| 462 |
|
|
NET "REQ" IOSTANDARD = PCI33_5;
|
| 463 |
|
|
|
| 464 |
|
|
#INST "REQ.PAD" TNM = "PCI_REQ" ;
|
| 465 |
|
|
|
| 466 |
|
|
NET "SERR" OFFSET = OUT 11 ns AFTER "CLK";
|
| 467 |
|
|
|
| 468 |
|
|
NET "SERR" IOSTANDARD = PCI33_5;
|
| 469 |
|
|
|
| 470 |
|
|
#INST "SERR.PAD" TNM = "PCI_CTRL" ;
|
| 471 |
|
|
|
| 472 |
|
|
NET "STOP" OFFSET = IN 7 ns BEFORE "CLK";
|
| 473 |
|
|
NET "STOP" OFFSET = OUT 11 ns AFTER "CLK";
|
| 474 |
|
|
|
| 475 |
|
|
NET "STOP" IOSTANDARD = PCI33_5;
|
| 476 |
|
|
|
| 477 |
|
|
#INST "STOP.PAD" TNM = "PCI_CTRL" ;
|
| 478 |
|
|
|
| 479 |
|
|
NET "TRDY" OFFSET = IN 7 ns BEFORE "CLK";
|
| 480 |
|
|
NET "TRDY" OFFSET = OUT 10 ns AFTER "CLK";
|
| 481 |
|
|
|
| 482 |
|
|
NET "TRDY" IOSTANDARD = PCI33_5;
|
| 483 |
|
|
|
| 484 |
|
|
#INST "TRDY.PAD" TNM = "PCI_CTRL" ;
|
| 485 |
|
|
|
| 486 |
|
|
NET "IDSEL" OFFSET = IN 7ns BEFORE "CLK" ;
|
| 487 |
|
|
NET "IDSEL" IOSTANDARD = PCI33_5 ;
|
| 488 |
|
|
|
| 489 |
|
|
##################################################################################
|
| 490 |
|
|
# Pin locations
|
| 491 |
|
|
##################################################################################
|
| 492 |
|
|
NET "CLK" LOC = "C11" ;
|
| 493 |
|
|
NET "INTA" LOC = "M3" ;
|
| 494 |
|
|
NET "RST" LOC = "E2" ;
|
| 495 |
|
|
NET "GNT" LOC = "L5" ;
|
| 496 |
|
|
NET "REQ" LOC = "K2" ;
|
| 497 |
|
|
NET "AD31" LOC = "E1" ;
|
| 498 |
|
|
NET "AD30" LOC = "G4" ;
|
| 499 |
|
|
NET "AD29" LOC = "G3" ;
|
| 500 |
|
|
NET "AD28" LOC = "H5" ;
|
| 501 |
|
|
NET "AD27" LOC = "F2" ;
|
| 502 |
|
|
NET "AD26" LOC = "F1" ;
|
| 503 |
|
|
NET "AD25" LOC = "H4" ;
|
| 504 |
|
|
NET "AD24" LOC = "G1" ;
|
| 505 |
|
|
NET "CBE3" LOC = "N2" ;
|
| 506 |
|
|
NET "IDSEL" LOC = "L6" ;
|
| 507 |
|
|
NET "AD23" LOC = "H3" ;
|
| 508 |
|
|
NET "AD22" LOC = "H2" ;
|
| 509 |
|
|
NET "AD21" LOC = "J4" ;
|
| 510 |
|
|
NET "AD20" LOC = "H1" ;
|
| 511 |
|
|
NET "AD19" LOC = "J5" ;
|
| 512 |
|
|
NET "AD18" LOC = "J2" ;
|
| 513 |
|
|
NET "AD17" LOC = "J3" ;
|
| 514 |
|
|
NET "AD16" LOC = "J1" ;
|
| 515 |
|
|
NET "CBE2" LOC = "N3" ;
|
| 516 |
|
|
NET "FRAME" LOC = "M6" ;
|
| 517 |
|
|
NET "IRDY" LOC = "L3" ;
|
| 518 |
|
|
#
|
| 519 |
|
|
NET "TRDY" LOC = "M1" ;
|
| 520 |
|
|
NET "DEVSEL" LOC = "L1" ;
|
| 521 |
|
|
NET "STOP" LOC = "L4" ;
|
| 522 |
|
|
NET "PERR" LOC = "N5" ;
|
| 523 |
|
|
NET "SERR" LOC = "M4" ;
|
| 524 |
|
|
NET "PAR" LOC = "P2" ;
|
| 525 |
|
|
NET "CBE1" LOC = "N4" ;
|
| 526 |
|
|
NET "AD15" LOC = "K5" ;
|
| 527 |
|
|
NET "AD14" LOC = "K1" ;
|
| 528 |
|
|
NET "AD13" LOC = "K3" ;
|
| 529 |
|
|
NET "AD12" LOC = "K4" ;
|
| 530 |
|
|
NET "AD11" LOC = "P4" ;
|
| 531 |
|
|
NET "AD10" LOC = "R1" ;
|
| 532 |
|
|
NET "AD9" LOC = "P5" ;
|
| 533 |
|
|
NET "AD8" LOC = "P3" ;
|
| 534 |
|
|
NET "CBE0" LOC = "P1" ;
|
| 535 |
|
|
NET "AD7" LOC = "R2" ;
|
| 536 |
|
|
NET "AD6" LOC = "T1" ;
|
| 537 |
|
|
NET "AD5" LOC = "R4" ;
|
| 538 |
|
|
NET "AD4" LOC = "T2" ;
|
| 539 |
|
|
NET "AD3" LOC = "U1" ;
|
| 540 |
|
|
NET "AD2" LOC = "R5" ;
|
| 541 |
|
|
NET "AD1" LOC = "V1" ;
|
| 542 |
|
|
NET "AD0" LOC = "T5" ;
|
| 543 |
|
|
|
| 544 |
|
|
# Dime Pinout: http://ece-www.colorado.edu/~ecen5633/dime.html
|
| 545 |
|
|
# Opencore VGA Dime connection http://www.opencores.org/projects/pci/test_board
|
| 546 |
|
|
#
|
| 547 |
|
|
#NET "HSYNC" LOC = "W17" ;
|
| 548 |
|
|
#NET "VSYNC" LOC = "W18" ;
|
| 549 |
|
|
#NET "RGB<0>" LOC = "" ;
|
| 550 |
|
|
#NET "RGB<1>" LOC = "" ;
|
| 551 |
|
|
#NET "RGB<2>" LOC = "" ;
|
| 552 |
|
|
#NET "RGB<3>" LOC = "" ;
|
| 553 |
|
|
#
|
| 554 |
|
|
NET "CRT_CLK" LOC = "W12" ;
|
| 555 |
|
|
NET "HSYNC" LOC = "W17" ;
|
| 556 |
|
|
NET "VSYNC" LOC = "W18" ;
|
| 557 |
|
|
NET "RGB4" LOC = "AA19" ;
|
| 558 |
|
|
NET "RGB5" LOC = "V12" ;
|
| 559 |
|
|
NET "RGB6" LOC = "Y15" ;
|
| 560 |
|
|
NET "RGB7" LOC = "Y12" ;
|
| 561 |
|
|
NET "RGB8" LOC = "Y16" ;
|
| 562 |
|
|
NET "RGB9" LOC = "V13" ;
|
| 563 |
|
|
NET "RGB10" LOC = "Y17" ;
|
| 564 |
|
|
NET "RGB11" LOC = "Y13" ;
|
| 565 |
|
|
NET "RGB12" LOC = "Y18" ;
|
| 566 |
|
|
NET "RGB13" LOC = "W13" ;
|
| 567 |
|
|
NET "RGB14" LOC = "Y14" ;
|
| 568 |
|
|
NET "RGB15" LOC = "V14" ;
|
| 569 |
|
|
#NET "LED" LOC = "" ;
|
| 570 |
|
|
#
|
| 571 |
|
|
|
| 572 |
|
|
##################################################################################
|
| 573 |
|
|
# IOB force
|
| 574 |
|
|
##################################################################################
|
| 575 |
|
|
#INST "bridge/pci_io_mux/ad_iob0/dat_out_reg" IOB = TRUE ;
|
| 576 |
|
|
#INST "bridge/pci_io_mux/ad_iob1/dat_out_reg" IOB = TRUE ;
|
| 577 |
|
|
#INST "bridge/pci_io_mux/ad_iob2/dat_out_reg" IOB = TRUE ;
|
| 578 |
|
|
#INST "bridge/pci_io_mux/ad_iob3/dat_out_reg" IOB = TRUE ;
|
| 579 |
|
|
#INST "bridge/pci_io_mux/ad_iob4/dat_out_reg" IOB = TRUE ;
|
| 580 |
|
|
#INST "bridge/pci_io_mux/ad_iob5/dat_out_reg" IOB = TRUE ;
|
| 581 |
|
|
#INST "bridge/pci_io_mux/ad_iob6/dat_out_reg" IOB = TRUE ;
|
| 582 |
|
|
#INST "bridge/pci_io_mux/ad_iob7/dat_out_reg" IOB = TRUE ;
|
| 583 |
|
|
#INST "bridge/pci_io_mux/ad_iob8/dat_out_reg" IOB = TRUE ;
|
| 584 |
|
|
#INST "bridge/pci_io_mux/ad_iob9/dat_out_reg" IOB = TRUE ;
|
| 585 |
|
|
#INST "bridge/pci_io_mux/ad_iob10/dat_out_reg" IOB = TRUE ;
|
| 586 |
|
|
#INST "bridge/pci_io_mux/ad_iob11/dat_out_reg" IOB = TRUE ;
|
| 587 |
|
|
#INST "bridge/pci_io_mux/ad_iob12/dat_out_reg" IOB = TRUE ;
|
| 588 |
|
|
#INST "bridge/pci_io_mux/ad_iob13/dat_out_reg" IOB = TRUE ;
|
| 589 |
|
|
#INST "bridge/pci_io_mux/ad_iob14/dat_out_reg" IOB = TRUE ;
|
| 590 |
|
|
#INST "bridge/pci_io_mux/ad_iob15/dat_out_reg" IOB = TRUE ;
|
| 591 |
|
|
#INST "bridge/pci_io_mux/ad_iob16/dat_out_reg" IOB = TRUE ;
|
| 592 |
|
|
#INST "bridge/pci_io_mux/ad_iob17/dat_out_reg" IOB = TRUE ;
|
| 593 |
|
|
#INST "bridge/pci_io_mux/ad_iob18/dat_out_reg" IOB = TRUE ;
|
| 594 |
|
|
#INST "bridge/pci_io_mux/ad_iob19/dat_out_reg" IOB = TRUE ;
|
| 595 |
|
|
#INST "bridge/pci_io_mux/ad_iob20/dat_out_reg" IOB = TRUE ;
|
| 596 |
|
|
#INST "bridge/pci_io_mux/ad_iob21/dat_out_reg" IOB = TRUE ;
|
| 597 |
|
|
#INST "bridge/pci_io_mux/ad_iob22/dat_out_reg" IOB = TRUE ;
|
| 598 |
|
|
#INST "bridge/pci_io_mux/ad_iob23/dat_out_reg" IOB = TRUE ;
|
| 599 |
|
|
#INST "bridge/pci_io_mux/ad_iob24/dat_out_reg" IOB = TRUE ;
|
| 600 |
|
|
#INST "bridge/pci_io_mux/ad_iob25/dat_out_reg" IOB = TRUE ;
|
| 601 |
|
|
#INST "bridge/pci_io_mux/ad_iob26/dat_out_reg" IOB = TRUE ;
|
| 602 |
|
|
#INST "bridge/pci_io_mux/ad_iob27/dat_out_reg" IOB = TRUE ;
|
| 603 |
|
|
#INST "bridge/pci_io_mux/ad_iob28/dat_out_reg" IOB = TRUE ;
|
| 604 |
|
|
#INST "bridge/pci_io_mux/ad_iob29/dat_out_reg" IOB = TRUE ;
|
| 605 |
|
|
#INST "bridge/pci_io_mux/ad_iob30/dat_out_reg" IOB = TRUE ;
|
| 606 |
|
|
#INST "bridge/pci_io_mux/ad_iob31/dat_out_reg" IOB = TRUE ;
|
| 607 |
|
|
|
| 608 |
|
|
####################################################################################
|
| 609 |
|
|
# Force output enable IOBs
|
| 610 |
|
|
####################################################################################
|
| 611 |
|
|
#INST "bridge/pci_io_mux/ad_iob0/en_out_reg" IOB = TRUE ;
|
| 612 |
|
|
#INST "bridge/pci_io_mux/ad_iob1/en_out_reg" IOB = TRUE ;
|
| 613 |
|
|
#INST "bridge/pci_io_mux/ad_iob2/en_out_reg" IOB = TRUE ;
|
| 614 |
|
|
#INST "bridge/pci_io_mux/ad_iob3/en_out_reg" IOB = TRUE ;
|
| 615 |
|
|
#INST "bridge/pci_io_mux/ad_iob4/en_out_reg" IOB = TRUE ;
|
| 616 |
|
|
#INST "bridge/pci_io_mux/ad_iob5/en_out_reg" IOB = TRUE ;
|
| 617 |
|
|
#INST "bridge/pci_io_mux/ad_iob6/en_out_reg" IOB = TRUE ;
|
| 618 |
|
|
#INST "bridge/pci_io_mux/ad_iob7/en_out_reg" IOB = TRUE ;
|
| 619 |
|
|
#INST "bridge/pci_io_mux/ad_iob8/en_out_reg" IOB = TRUE ;
|
| 620 |
|
|
#INST "bridge/pci_io_mux/ad_iob9/en_out_reg" IOB = TRUE ;
|
| 621 |
|
|
#INST "bridge/pci_io_mux/ad_iob10/en_out_reg" IOB = TRUE ;
|
| 622 |
|
|
#INST "bridge/pci_io_mux/ad_iob11/en_out_reg" IOB = TRUE ;
|
| 623 |
|
|
#INST "bridge/pci_io_mux/ad_iob12/en_out_reg" IOB = TRUE ;
|
| 624 |
|
|
#INST "bridge/pci_io_mux/ad_iob13/en_out_reg" IOB = TRUE ;
|
| 625 |
|
|
#INST "bridge/pci_io_mux/ad_iob14/en_out_reg" IOB = TRUE ;
|
| 626 |
|
|
#INST "bridge/pci_io_mux/ad_iob15/en_out_reg" IOB = TRUE ;
|
| 627 |
|
|
#INST "bridge/pci_io_mux/ad_iob16/en_out_reg" IOB = TRUE ;
|
| 628 |
|
|
#INST "bridge/pci_io_mux/ad_iob17/en_out_reg" IOB = TRUE ;
|
| 629 |
|
|
#INST "bridge/pci_io_mux/ad_iob18/en_out_reg" IOB = TRUE ;
|
| 630 |
|
|
#INST "bridge/pci_io_mux/ad_iob19/en_out_reg" IOB = TRUE ;
|
| 631 |
|
|
#INST "bridge/pci_io_mux/ad_iob20/en_out_reg" IOB = TRUE ;
|
| 632 |
|
|
#INST "bridge/pci_io_mux/ad_iob21/en_out_reg" IOB = TRUE ;
|
| 633 |
|
|
#INST "bridge/pci_io_mux/ad_iob22/en_out_reg" IOB = TRUE ;
|
| 634 |
|
|
#INST "bridge/pci_io_mux/ad_iob23/en_out_reg" IOB = TRUE ;
|
| 635 |
|
|
#INST "bridge/pci_io_mux/ad_iob24/en_out_reg" IOB = TRUE ;
|
| 636 |
|
|
#INST "bridge/pci_io_mux/ad_iob25/en_out_reg" IOB = TRUE ;
|
| 637 |
|
|
#INST "bridge/pci_io_mux/ad_iob26/en_out_reg" IOB = TRUE ;
|
| 638 |
|
|
#INST "bridge/pci_io_mux/ad_iob27/en_out_reg" IOB = TRUE ;
|
| 639 |
|
|
#INST "bridge/pci_io_mux/ad_iob28/en_out_reg" IOB = TRUE ;
|
| 640 |
|
|
#INST "bridge/pci_io_mux/ad_iob29/en_out_reg" IOB = TRUE ;
|
| 641 |
|
|
#INST "bridge/pci_io_mux/ad_iob30/en_out_reg" IOB = TRUE ;
|
| 642 |
|
|
#INST "bridge/pci_io_mux/ad_iob31/en_out_reg" IOB = TRUE ;
|
| 643 |
|
|
|
| 644 |
|
|
####################################################################################
|
| 645 |
|
|
# CBE IOBs
|
| 646 |
|
|
####################################################################################
|
| 647 |
|
|
#INST "bridge/pci_io_mux/cbe_iob0/dat_out_reg" IOB = TRUE ;
|
| 648 |
|
|
#INST "bridge/pci_io_mux/cbe_iob1/dat_out_reg" IOB = TRUE ;
|
| 649 |
|
|
#INST "bridge/pci_io_mux/cbe_iob2/dat_out_reg" IOB = TRUE ;
|
| 650 |
|
|
#INST "bridge/pci_io_mux/cbe_iob3/dat_out_reg" IOB = TRUE ;
|
| 651 |
|
|
#
|
| 652 |
|
|
#INST "bridge/pci_io_mux/cbe_iob0/en_out_reg" IOB = TRUE ;
|
| 653 |
|
|
#INST "bridge/pci_io_mux/cbe_iob1/en_out_reg" IOB = TRUE ;
|
| 654 |
|
|
#INST "bridge/pci_io_mux/cbe_iob2/en_out_reg" IOB = TRUE ;
|
| 655 |
|
|
#INST "bridge/pci_io_mux/cbe_iob3/en_out_reg" IOB = TRUE ;
|
| 656 |
|
|
|
| 657 |
|
|
####################################################################################
|
| 658 |
|
|
# Control signals IOBs
|
| 659 |
|
|
####################################################################################
|
| 660 |
|
|
#INST "bridge/pci_io_mux/frame_iob/dat_out_reg" IOB = TRUE ;
|
| 661 |
|
|
#INST "bridge/pci_io_mux/frame_iob/en_out_reg" IOB = TRUE ;
|
| 662 |
|
|
#INST "bridge/pci_io_mux/irdy_iob/dat_out_reg" IOB = TRUE ;
|
| 663 |
|
|
#INST "bridge/pci_io_mux/irdy_iob/en_out_reg" IOB = TRUE ;
|
| 664 |
|
|
#
|
| 665 |
|
|
#INST "bridge/pci_io_mux/trdy_iob/dat_out_reg" IOB = TRUE ;
|
| 666 |
|
|
#INST "bridge/pci_io_mux/trdy_iob/en_out_reg" IOB = TRUE ;
|
| 667 |
|
|
#
|
| 668 |
|
|
#INST "bridge/pci_io_mux/devsel_iob/dat_out_reg" IOB = TRUE ;
|
| 669 |
|
|
#INST "bridge/pci_io_mux/devsel_iob/en_out_reg" IOB = TRUE ;
|
| 670 |
|
|
#
|
| 671 |
|
|
#INST "bridge/pci_io_mux/stop_iob/dat_out_reg" IOB = TRUE ;
|
| 672 |
|
|
#INST "bridge/pci_io_mux/stop_iob/en_out_reg" IOB = TRUE ;
|
| 673 |
|
|
#
|
| 674 |
|
|
#INST "bridge/pci_io_mux/par_iob/dat_out_reg" IOB = TRUE ;
|
| 675 |
|
|
#INST "bridge/pci_io_mux/par_iob/en_out_reg" IOB = TRUE ;
|
| 676 |
|
|
#
|
| 677 |
|
|
#INST "bridge/pci_io_mux/perr_iob/dat_out_reg" IOB = TRUE ;
|
| 678 |
|
|
#INST "bridge/pci_io_mux/perr_iob/en_out_reg" IOB = TRUE ;
|
| 679 |
|
|
#
|
| 680 |
|
|
#INST "bridge/pci_io_mux/serr_iob/dat_out_reg" IOB = TRUE ;
|
| 681 |
|
|
#INST "bridge/pci_io_mux/serr_iob/en_out_reg" IOB = TRUE ;
|
| 682 |
|
|
#
|
| 683 |
|
|
#INST "bridge/pci_io_mux/req_iob/dat_out_reg" IOB = TRUE ;
|
| 684 |
|
|
#INST "bridge/pci_io_mux/req_iob/en_out_reg" IOB = TRUE ;
|
| 685 |
|
|
|
| 686 |
|
|
#INST "bridge/wishbone_slave_unit/pci_initiator_if" TNM=FFS:PCI_MIF_FFS ;
|
| 687 |
|
|
#INST "bridge/wishbone_slave_unit/pci_initiator_sm" TNM=FFS:PCI_MSM_FFS ;
|
| 688 |
|
|
#INST "bridge/pci_io_mux/frame_iob/dat_out_reg" TNM=FFS:PCI_O_FFS ;
|
| 689 |
|
|
#INST "bridge/parity_checker" TNM=FFS:PCI_PAR_FFS ;
|
| 690 |
|
|
#INST "bridge/input_register" TNM=FFS:PCI_I_FFS ;
|
| 691 |
|
|
|
| 692 |
|
|
#TIMEGRP "ALL_PCI_FFS" = "PCI_O_FFS" ;
|
| 693 |
|
|
|
| 694 |
|
|
#TIMESPEC TS_PCI_AD_SETUP = FROM : "PCI_AD" : TO : "ALL_PCI_FFS" : 7.000 ;
|
| 695 |
|
|
#TIMESPEC TS_PCI_CBE_SETUP = FROM : "PCI_CBE" : TO : "ALL_PCI_FFS" : 7.000 ;
|
| 696 |
|
|
#TIMESPEC TS_PCI_CTRL_SETUP = FROM : "PCI_CTRL" : TO : "ALL_PCI_FFS" : 7.000 ;
|
| 697 |
|
|
|
| 698 |
|
|
#TIMESPEC TS_PCI_REQ_TIME_OUT = FROM : "ALL_PCI_FFS" : TO : "PCI_REQ" : 12.000 ;
|
| 699 |
|
|
#TIMESPEC TS_PCI_GNT_SETUP = FROM : "PCI_GNT" : TO : "ALL_PCI_FFS" : 10.000 ;
|
| 700 |
|
|
|
| 701 |
|
|
#TIMESPEC TS_PCI_AD_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_AD" : 11.000 ;
|
| 702 |
|
|
#TIMESPEC TS_PCI_CBE_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_CBE" : 11.000 ;
|
| 703 |
|
|
#TIMESPEC TS_PCI_CTRL_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_CTRL" : 11.000 ;
|
