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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_async_reset_flop.v] - Blame information for rev 154

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//===========================================================================
// $Id: pci_async_reset_flop.v,v 1.1 2003-01-27 16:49:31 mihad Exp $
//
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// async_reset_flop                                             ////
////                                                              ////
//// This file is part of the general opencores effort.           ////
//// <http://www.opencores.org/cores/misc/>                       ////
////                                                              ////
//// Module Description:                                          ////
////                                                              ////
//// Make a rising-edge triggered flop with async reset with a    ////
////   distinguished name so that it's output can be easily       ////
////   traced, because it is used for asynchronous reset of some  ////
////   flip-flops.                                                ////
////                                                              ////
//// This flop should be used instead of a regular flop for ALL   ////
////   asynchronous-reset generator flops.                        ////
////                                                              ////
//// To Do:                                                       ////
//// Nothing                                                      ////
////                                                              ////
//// Author(s):                                                   ////
////      - Tadej Markovic, tadej@opencores.org                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/08/14 16:44:19  mihad
// Include statement was enclosed in synosys translate off/on directive - repaired
//
// Revision 1.2  2002/02/25 15:15:43  mihad
// Added include statement that was missing and causing errors
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
// 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "pci_constants.v"
 
module pci_async_reset_flop (
  data_in, clk_in, async_reset_data_out, reset_in
);
 
input      data_in;
input      clk_in;
output     async_reset_data_out;
input      reset_in;
 
reg        async_reset_data_out;
 
always @(posedge clk_in or posedge reset_in)
begin
  if (reset_in)
  begin
    async_reset_data_out <= #`FF_DELAY 1'b0;
  end
  else
  begin
    async_reset_data_out <= #`FF_DELAY data_in;
  end
end
 
endmodule
 

Line No.	Rev	Author	Line
1	77	mihad	`//===========================================================================`
2			`// $Id: pci_async_reset_flop.v,v 1.1 2003-01-27 16:49:31 mihad Exp $`
3			`//`
4			`//////////////////////////////////////////////////////////////////////`
5			`//// ////`
6			`//// async_reset_flop ////`
7			`//// ////`
8			`//// This file is part of the general opencores effort. ////`
9			`//// <http://www.opencores.org/cores/misc/> ////`
10			`//// ////`
11			`//// Module Description: ////`
12			`//// ////`
13			`//// Make a rising-edge triggered flop with async reset with a ////`
14			`//// distinguished name so that it's output can be easily ////`
15			`//// traced, because it is used for asynchronous reset of some ////`
16			`//// flip-flops. ////`
17			`//// ////`
18			`//// This flop should be used instead of a regular flop for ALL ////`
19			`//// asynchronous-reset generator flops. ////`
20			`//// ////`
21			`//// To Do: ////`
22			`//// Nothing ////`
23			`//// ////`
24			`//// Author(s): ////`
25			`//// - Tadej Markovic, tadej@opencores.org ////`
26			`//// ////`
27			`//////////////////////////////////////////////////////////////////////`
28			`//// ////`
29			`//// Copyright (C) 2001 Authors and OPENCORES.ORG ////`
30			`//// ////`
31			`//// This source file may be used and distributed without ////`
32			`//// restriction provided that this copyright statement is not ////`
33			`//// removed from the file and that any derivative work contains ////`
34			`//// the original copyright notice and the associated disclaimer. ////`
35			`//// ////`
36			`//// This source file is free software; you can redistribute it ////`
37			`//// and/or modify it under the terms of the GNU Lesser General ////`
38			`//// Public License as published by the Free Software Foundation; ////`
39			`//// either version 2.1 of the License, or (at your option) any ////`
40			`//// later version. ////`
41			`//// ////`
42			`//// This source is distributed in the hope that it will be ////`
43			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
44			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
45			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
46			`//// details. ////`
47			`//// ////`
48			`//// You should have received a copy of the GNU Lesser General ////`
49			`//// Public License along with this source; if not, download it ////`
50			`//// from <http://www.opencores.org/lgpl.shtml> ////`
51			`//// ////`
52			`//////////////////////////////////////////////////////////////////////`
53			`//`
54			`// CVS Revision History`
55			`//`
56			`// $Log: not supported by cvs2svn $`
57			`// Revision 1.3 2002/08/14 16:44:19 mihad`
58			`// Include statement was enclosed in synosys translate off/on directive - repaired`
59			`//`
60			`// Revision 1.2 2002/02/25 15:15:43 mihad`
61			`// Added include statement that was missing and causing errors`
62			`//`
63			`// Revision 1.1 2002/02/01 14:43:31 mihad`
64			`// * empty log message *`
65			`//`
66			`//`
67			`//`
68
69			`// synopsys translate_off`
70			`include "timescale.v"
71			`// synopsys translate_on`
72
73			`include "pci_constants.v"
74
75			`module pci_async_reset_flop (`
76			`data_in, clk_in, async_reset_data_out, reset_in`
77			`);`
78
79			`input data_in;`
80			`input clk_in;`
81			`output async_reset_data_out;`
82			`input reset_in;`
83
84			`reg async_reset_data_out;`
85
86			`always @(posedge clk_in or posedge reset_in)`
87			`begin`
88			`if (reset_in)`
89			`begin`
90			async_reset_data_out <= #`FF_DELAY 1'b0;
91			`end`
92			`else`
93			`begin`
94			async_reset_data_out <= #`FF_DELAY data_in;
95			`end`
96			`end`
97
98			`endmodule`
99

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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_async_reset_flop.v] - Blame information for rev 154