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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_io_mux.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:29  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
// this module instantiates output flip flops for PCI interface and
// some fanout downsizing logic because of heavily constrained PCI signals
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_io_mux
(
    reset_in,
    clk_in,
    frame_in,
    frame_en_in,
    frame_load_in,
    irdy_in,
    irdy_en_in,
    devsel_in,
    devsel_en_in,
    trdy_in,
    trdy_en_in,
    stop_in,
    stop_en_in,
    master_load_in,
    master_load_on_transfer_in,
    target_load_in,
    target_load_on_transfer_in,
    cbe_in,
    cbe_en_in,
    mas_ad_in,
    tar_ad_in,
 
    par_in,
    par_en_in,
    perr_in,
    perr_en_in,
    serr_in,
    serr_en_in,
 
    req_in,
 
    mas_ad_en_in,
    tar_ad_en_in,
    tar_ad_en_reg_in,
 
    ad_en_out,
    frame_en_out,
    irdy_en_out,
    devsel_en_out,
    trdy_en_out,
    stop_en_out,
    cbe_en_out,
 
    frame_out,
    irdy_out,
    devsel_out,
    trdy_out,
    stop_out,
    cbe_out,
    ad_out,
    ad_load_out,
    ad_en_unregistered_out,
 
    par_out,
    par_en_out,
    perr_out,
    perr_en_out,
    serr_out,
    serr_en_out,
 
    req_out,
    req_en_out,
    pci_trdy_in,
    pci_irdy_in,
    pci_frame_in,
    pci_stop_in
);
 
input reset_in, clk_in ;
 
input           frame_in ;
input           frame_en_in ;
input           frame_load_in ;
input           irdy_in ;
input           irdy_en_in ;
input           devsel_in ;
input           devsel_en_in ;
input           trdy_in ;
input           trdy_en_in ;
input           stop_in ;
input           stop_en_in ;
input           master_load_in ;
input           target_load_in ;
 
input [3:0]     cbe_in ;
input           cbe_en_in ;
input [31:0]    mas_ad_in ;
input [31:0]    tar_ad_in ;
 
input           mas_ad_en_in ;
input           tar_ad_en_in ;
input           tar_ad_en_reg_in ;
 
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
 
output          frame_en_out ;
output          irdy_en_out ;
output          devsel_en_out ;
output          trdy_en_out ;
output          stop_en_out ;
output [31:0]   ad_en_out ;
output [3:0]    cbe_en_out ;
 
output          frame_out ;
output          irdy_out ;
output          devsel_out ;
output          trdy_out ;
output          stop_out ;
output [3:0]    cbe_out ;
output [31:0]   ad_out ;
output          ad_load_out ;
output          ad_en_unregistered_out ;
 
output          par_out ;
output          par_en_out ;
output          perr_out ;
output          perr_en_out ;
output          serr_out ;
output          serr_en_out ;
 
input           req_in ;
 
output          req_out ;
output          req_en_out ;
 
input           pci_trdy_in,
                pci_irdy_in,
                pci_frame_in,
                pci_stop_in ;
 
input           master_load_on_transfer_in ;
input           target_load_on_transfer_in ;
 
wire   [31:0]   temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
 
wire ad_en_ctrl_low ;
 
wire ad_en_ctrl_mlow ;
 
wire ad_en_ctrl_mhigh ;
 
wire ad_en_ctrl_high ;
 
wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
 
pci_io_mux_ad_en_crit ad_en_low_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_low)
);
 
pci_io_mux_ad_en_crit ad_en_mlow_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_mlow)
);
 
pci_io_mux_ad_en_crit ad_en_mhigh_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_mhigh)
);
 
pci_io_mux_ad_en_crit ad_en_high_gen
(
    .ad_en_in       (ad_enable_internal),
    .pci_frame_in   (pci_frame_in),
    .pci_trdy_in    (pci_trdy_in),
    .pci_stop_in    (pci_stop_in),
    .ad_en_out      (ad_en_ctrl_high)
);
 
assign ad_en_unregistered_out = ad_en_ctrl_high ;
 
wire load = master_load_in || target_load_in ;
wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
 
wire   ad_load_ctrl_low ;
wire   ad_load_ctrl_mlow ;
wire   ad_load_ctrl_mhigh ;
wire   ad_load_ctrl_high ;
 
assign ad_load_out = ad_load_ctrl_high ;
 
pci_io_mux_ad_load_crit ad_load_low_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_low)
);
 
pci_io_mux_ad_load_crit ad_load_mlow_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_mlow)
);
 
pci_io_mux_ad_load_crit ad_load_mhigh_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_mhigh)
);
 
pci_io_mux_ad_load_crit ad_load_high_gen
(
    .load_in(load),
    .load_on_transfer_in(load_on_transfer),
    .pci_irdy_in(pci_irdy_in),
    .pci_trdy_in(pci_trdy_in),
    .load_out(ad_load_ctrl_high)
);
 
pci_out_reg ad_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[0] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[0] ),
    .dat_out      ( ad_out[0] )
);
 
pci_out_reg ad_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[1] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[1] ),
    .dat_out      ( ad_out[1] )
);
 
pci_out_reg ad_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[2] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[2] ),
    .dat_out      ( ad_out[2] )
);
 
pci_out_reg ad_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[3] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[3] ),
    .dat_out      ( ad_out[3] )
);
 
pci_out_reg ad_iob4
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[4] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[4] ),
    .dat_out      ( ad_out[4] )
);
 
pci_out_reg ad_iob5
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[5] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[5] ),
    .dat_out      ( ad_out[5] )
);
 
pci_out_reg ad_iob6
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[6] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[6] ),
    .dat_out      ( ad_out[6] )
);
 
pci_out_reg ad_iob7
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_low ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[7] ) ,
    .en_in        ( ad_en_ctrl_low ) ,
    .en_out       ( ad_en_out[7] ),
    .dat_out      ( ad_out[7] )
);
 
pci_out_reg ad_iob8
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[8] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[8] ),
    .dat_out      ( ad_out[8] )
);
 
pci_out_reg ad_iob9
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[9] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[9] ),
    .dat_out      ( ad_out[9] )
);
 
pci_out_reg ad_iob10
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[10] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[10] ),
    .dat_out      ( ad_out[10] )
);
 
pci_out_reg ad_iob11
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[11] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[11] ),
    .dat_out      ( ad_out[11] )
);
 
pci_out_reg ad_iob12
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[12] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[12] ),
    .dat_out      ( ad_out[12] )
);
 
pci_out_reg ad_iob13
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[13] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[13] ),
    .dat_out      ( ad_out[13] )
);
 
pci_out_reg ad_iob14
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[14] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[14] ),
    .dat_out      ( ad_out[14] )
);
 
pci_out_reg ad_iob15
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mlow ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[15] ) ,
    .en_in        ( ad_en_ctrl_mlow ) ,
    .en_out       ( ad_en_out[15] ),
    .dat_out      ( ad_out[15] )
);
 
pci_out_reg ad_iob16
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[16] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[16] ),
    .dat_out      ( ad_out[16] )
);
 
pci_out_reg ad_iob17
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[17] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[17] ),
    .dat_out      ( ad_out[17] )
);
 
pci_out_reg ad_iob18
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[18] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[18] ),
    .dat_out      ( ad_out[18] )
);
 
pci_out_reg ad_iob19
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[19] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[19] ),
    .dat_out      ( ad_out[19] )
);
 
pci_out_reg ad_iob20
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[20] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[20] ),
    .dat_out      ( ad_out[20] )
);
 
pci_out_reg ad_iob21
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[21] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[21] ),
    .dat_out      ( ad_out[21] )
);
 
pci_out_reg ad_iob22
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[22] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[22] ),
    .dat_out      ( ad_out[22] )
);
 
pci_out_reg ad_iob23
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_mhigh ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[23] ) ,
    .en_in        ( ad_en_ctrl_mhigh ) ,
    .en_out       ( ad_en_out[23] ),
    .dat_out      ( ad_out[23] )
);
 
pci_out_reg ad_iob24
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[24] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[24] ),
    .dat_out      ( ad_out[24] )
);
 
pci_out_reg ad_iob25
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[25] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[25] ),
    .dat_out      ( ad_out[25] )
);
 
pci_out_reg ad_iob26
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[26] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[26] ),
    .dat_out      ( ad_out[26] )
);
 
pci_out_reg ad_iob27
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[27] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[27] ),
    .dat_out      ( ad_out[27] )
);
 
pci_out_reg ad_iob28
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[28] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[28] ),
    .dat_out      ( ad_out[28] )
);
 
pci_out_reg ad_iob29
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[29] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[29] ),
    .dat_out      ( ad_out[29] )
);
 
pci_out_reg ad_iob30
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[30] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[30] ),
    .dat_out      ( ad_out[30] )
);
 
pci_out_reg ad_iob31
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( ad_load_ctrl_high ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( temp_ad[31] ) ,
    .en_in        ( ad_en_ctrl_high ) ,
    .en_out       ( ad_en_out[31] ),
    .dat_out      ( ad_out[31] )
);
 
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
wire [3:0] cbe_en_ctrl   = {4{ cbe_en_in }} ;
 
pci_out_reg cbe_iob0
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[0] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[0] ) ,
    .en_in        ( cbe_en_ctrl[0] ) ,
    .en_out       ( cbe_en_out[0] ),
    .dat_out      ( cbe_out[0] )
);
 
pci_out_reg cbe_iob1
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[1] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[1] ) ,
    .en_in        ( cbe_en_ctrl[1] ) ,
    .en_out       ( cbe_en_out[1] ),
    .dat_out      ( cbe_out[1] )
);
 
pci_out_reg cbe_iob2
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[2] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[2] ) ,
    .en_in        ( cbe_en_ctrl[2] ) ,
    .en_out       ( cbe_en_out[2] ),
    .dat_out      ( cbe_out[2] )
);
 
pci_out_reg cbe_iob3
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( cbe_load_ctrl[3] ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( cbe_in[3] ) ,
    .en_in        ( cbe_en_ctrl[3] ) ,
    .en_out       ( cbe_en_out[3] ),
    .dat_out      ( cbe_out[3] )
);
 
pci_out_reg frame_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( frame_load_in ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( frame_in ) ,
    .en_in        ( frame_en_in ) ,
    .en_out       ( frame_en_out ),
    .dat_out      ( frame_out )
);
 
pci_out_reg irdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( irdy_in ) ,
    .en_in        ( irdy_en_in ) ,
    .en_out       ( irdy_en_out ),
    .dat_out      ( irdy_out )
);
 
pci_out_reg trdy_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( trdy_in ) ,
    .en_in        ( trdy_en_in ) ,
    .en_out       ( trdy_en_out ),
    .dat_out      ( trdy_out )
);
 
pci_out_reg stop_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( stop_in ) ,
    .en_in        ( stop_en_in ) ,
    .en_out       ( stop_en_out ),
    .dat_out      ( stop_out )
);
 
pci_out_reg devsel_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( devsel_in ) ,
    .en_in        ( devsel_en_in ) ,
    .en_out       ( devsel_en_out ),
    .dat_out      ( devsel_out )
);
 
pci_out_reg par_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( par_in ) ,
    .en_in        ( par_en_in ) ,
    .en_out       ( par_en_out ),
    .dat_out      ( par_out )
);
 
pci_out_reg perr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( perr_in ) ,
    .en_in        ( perr_en_in ) ,
    .en_out       ( perr_en_out ),
    .dat_out      ( perr_out )
);
 
pci_out_reg serr_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( serr_in ) ,
    .en_in        ( serr_en_in ) ,
    .en_out       ( serr_en_out ),
    .dat_out      ( serr_out )
);
 
pci_out_reg req_iob
(
    .reset_in     ( reset_in ),
    .clk_in       ( clk_in) ,
    .dat_en_in    ( 1'b1 ),
    .en_en_in     ( 1'b1 ),
    .dat_in       ( req_in ) ,
    .en_in        ( 1'b1 ) ,
    .en_out       ( req_en_out ),
    .dat_out      ( req_out )
);
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_io_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	77	mihad	`// Revision 1.3 2002/02/01 15:25:12 mihad`
46			`// Repaired a few bugs, updated specification, added test bench files and design document`
47			`//`
48	21	mihad	`// Revision 1.2 2001/10/05 08:14:29 mihad`
49			`// Updated all files with inclusion of timescale file for simulation purposes.`
50			`//`
51	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
52			`// New project directory structure`
53	2	mihad	`//`
54	6	mihad	`//`
55	2	mihad
56			`// this module instantiates output flip flops for PCI interface and`
57			`// some fanout downsizing logic because of heavily constrained PCI signals`
58	21	mihad
59			`// synopsys translate_off`
60	6	mihad	`include "timescale.v"
61	21	mihad	`// synopsys translate_on`
62	6	mihad
63	77	mihad	`module pci_io_mux`
64	2	mihad	`(`
65			`reset_in,`
66			`clk_in,`
67			`frame_in,`
68			`frame_en_in,`
69			`frame_load_in,`
70			`irdy_in,`
71			`irdy_en_in,`
72			`devsel_in,`
73			`devsel_en_in,`
74			`trdy_in,`
75			`trdy_en_in,`
76			`stop_in,`
77			`stop_en_in,`
78			`master_load_in,`
79	21	mihad	`master_load_on_transfer_in,`
80	2	mihad	`target_load_in,`
81	21	mihad	`target_load_on_transfer_in,`
82	2	mihad	`cbe_in,`
83			`cbe_en_in,`
84			`mas_ad_in,`
85			`tar_ad_in,`
86
87			`par_in,`
88			`par_en_in,`
89			`perr_in,`
90			`perr_en_in,`
91			`serr_in,`
92			`serr_en_in,`
93
94			`req_in,`
95	21	mihad
96	2	mihad	`mas_ad_en_in,`
97			`tar_ad_en_in,`
98			`tar_ad_en_reg_in,`
99	21	mihad
100	2	mihad	`ad_en_out,`
101			`frame_en_out,`
102			`irdy_en_out,`
103			`devsel_en_out,`
104			`trdy_en_out,`
105			`stop_en_out,`
106			`cbe_en_out,`
107
108			`frame_out,`
109			`irdy_out,`
110			`devsel_out,`
111			`trdy_out,`
112			`stop_out,`
113			`cbe_out,`
114			`ad_out,`
115	21	mihad	`ad_load_out,`
116			`ad_en_unregistered_out,`
117
118	2	mihad	`par_out,`
119			`par_en_out,`
120			`perr_out,`
121			`perr_en_out,`
122			`serr_out,`
123			`serr_en_out,`
124
125			`req_out,`
126	21	mihad	`req_en_out,`
127			`pci_trdy_in,`
128			`pci_irdy_in,`
129			`pci_frame_in,`
130			`pci_stop_in`
131	2	mihad	`);`
132
133			`input reset_in, clk_in ;`
134
135			`input frame_in ;`
136			`input frame_en_in ;`
137			`input frame_load_in ;`
138			`input irdy_in ;`
139			`input irdy_en_in ;`
140			`input devsel_in ;`
141			`input devsel_en_in ;`
142			`input trdy_in ;`
143			`input trdy_en_in ;`
144			`input stop_in ;`
145			`input stop_en_in ;`
146			`input master_load_in ;`
147			`input target_load_in ;`
148
149			`input [3:0] cbe_in ;`
150			`input cbe_en_in ;`
151			`input [31:0] mas_ad_in ;`
152			`input [31:0] tar_ad_in ;`
153
154			`input mas_ad_en_in ;`
155			`input tar_ad_en_in ;`
156			`input tar_ad_en_reg_in ;`
157
158			`input par_in ;`
159			`input par_en_in ;`
160	21	mihad	`input perr_in ;`
161	2	mihad	`input perr_en_in ;`
162	21	mihad	`input serr_in ;`
163	2	mihad	`input serr_en_in ;`
164
165			`output frame_en_out ;`
166			`output irdy_en_out ;`
167			`output devsel_en_out ;`
168			`output trdy_en_out ;`
169			`output stop_en_out ;`
170			`output [31:0] ad_en_out ;`
171			`output [3:0] cbe_en_out ;`
172
173			`output frame_out ;`
174			`output irdy_out ;`
175			`output devsel_out ;`
176			`output trdy_out ;`
177			`output stop_out ;`
178			`output [3:0] cbe_out ;`
179			`output [31:0] ad_out ;`
180	21	mihad	`output ad_load_out ;`
181			`output ad_en_unregistered_out ;`
182	2	mihad
183			`output par_out ;`
184			`output par_en_out ;`
185	21	mihad	`output perr_out ;`
186	2	mihad	`output perr_en_out ;`
187	21	mihad	`output serr_out ;`
188	2	mihad	`output serr_en_out ;`
189
190			`input req_in ;`
191
192			`output req_out ;`
193			`output req_en_out ;`
194
195	21	mihad	`input pci_trdy_in,`
196			`pci_irdy_in,`
197			`pci_frame_in,`
198			`pci_stop_in ;`
199	2	mihad
200	21	mihad	`input master_load_on_transfer_in ;`
201			`input target_load_on_transfer_in ;`
202
203	2	mihad	`wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;`
204
205			`wire ad_en_ctrl_low ;`
206
207			`wire ad_en_ctrl_mlow ;`
208
209			`wire ad_en_ctrl_mhigh ;`
210
211			`wire ad_en_ctrl_high ;`
212
213	21	mihad	`wire ad_enable_internal = mas_ad_en_in \|\| tar_ad_en_in ;`
214	2	mihad
215	77	mihad	`pci_io_mux_ad_en_crit ad_en_low_gen`
216	21	mihad	`(`
217			`.ad_en_in (ad_enable_internal),`
218			`.pci_frame_in (pci_frame_in),`
219			`.pci_trdy_in (pci_trdy_in),`
220			`.pci_stop_in (pci_stop_in),`
221			`.ad_en_out (ad_en_ctrl_low)`
222			`);`
223	2	mihad
224	77	mihad	`pci_io_mux_ad_en_crit ad_en_mlow_gen`
225	21	mihad	`(`
226			`.ad_en_in (ad_enable_internal),`
227			`.pci_frame_in (pci_frame_in),`
228			`.pci_trdy_in (pci_trdy_in),`
229			`.pci_stop_in (pci_stop_in),`
230			`.ad_en_out (ad_en_ctrl_mlow)`
231			`);`
232	2	mihad
233	77	mihad	`pci_io_mux_ad_en_crit ad_en_mhigh_gen`
234	21	mihad	`(`
235			`.ad_en_in (ad_enable_internal),`
236			`.pci_frame_in (pci_frame_in),`
237			`.pci_trdy_in (pci_trdy_in),`
238			`.pci_stop_in (pci_stop_in),`
239			`.ad_en_out (ad_en_ctrl_mhigh)`
240			`);`
241	2	mihad
242	77	mihad	`pci_io_mux_ad_en_crit ad_en_high_gen`
243	21	mihad	`(`
244			`.ad_en_in (ad_enable_internal),`
245			`.pci_frame_in (pci_frame_in),`
246			`.pci_trdy_in (pci_trdy_in),`
247			`.pci_stop_in (pci_stop_in),`
248			`.ad_en_out (ad_en_ctrl_high)`
249			`);`
250
251			`assign ad_en_unregistered_out = ad_en_ctrl_high ;`
252
253			`wire load = master_load_in \|\| target_load_in ;`
254			`wire load_on_transfer = master_load_on_transfer_in \|\| target_load_on_transfer_in ;`
255
256			`wire ad_load_ctrl_low ;`
257			`wire ad_load_ctrl_mlow ;`
258			`wire ad_load_ctrl_mhigh ;`
259			`wire ad_load_ctrl_high ;`
260
261			`assign ad_load_out = ad_load_ctrl_high ;`
262
263	77	mihad	`pci_io_mux_ad_load_crit ad_load_low_gen`
264	21	mihad	`(`
265			`.load_in(load),`
266			`.load_on_transfer_in(load_on_transfer),`
267			`.pci_irdy_in(pci_irdy_in),`
268			`.pci_trdy_in(pci_trdy_in),`
269			`.load_out(ad_load_ctrl_low)`
270			`);`
271
272	77	mihad	`pci_io_mux_ad_load_crit ad_load_mlow_gen`
273	21	mihad	`(`
274			`.load_in(load),`
275			`.load_on_transfer_in(load_on_transfer),`
276			`.pci_irdy_in(pci_irdy_in),`
277			`.pci_trdy_in(pci_trdy_in),`
278			`.load_out(ad_load_ctrl_mlow)`
279			`);`
280
281	77	mihad	`pci_io_mux_ad_load_crit ad_load_mhigh_gen`
282	21	mihad	`(`
283			`.load_in(load),`
284			`.load_on_transfer_in(load_on_transfer),`
285			`.pci_irdy_in(pci_irdy_in),`
286			`.pci_trdy_in(pci_trdy_in),`
287			`.load_out(ad_load_ctrl_mhigh)`
288			`);`
289
290	77	mihad	`pci_io_mux_ad_load_crit ad_load_high_gen`
291	21	mihad	`(`
292			`.load_in(load),`
293			`.load_on_transfer_in(load_on_transfer),`
294			`.pci_irdy_in(pci_irdy_in),`
295			`.pci_trdy_in(pci_trdy_in),`
296			`.load_out(ad_load_ctrl_high)`
297			`);`
298
299	77	mihad	`pci_out_reg ad_iob0`
300	21	mihad	`(`
301	2	mihad	`.reset_in ( reset_in ),`
302			`.clk_in ( clk_in) ,`
303			`.dat_en_in ( ad_load_ctrl_low ),`
304			`.en_en_in ( 1'b1 ),`
305			`.dat_in ( temp_ad[0] ) ,`
306			`.en_in ( ad_en_ctrl_low ) ,`
307			`.en_out ( ad_en_out[0] ),`
308			`.dat_out ( ad_out[0] )`
309			`);`
310
311	77	mihad	`pci_out_reg ad_iob1`
312	21	mihad	`(`
313	2	mihad	`.reset_in ( reset_in ),`
314			`.clk_in ( clk_in) ,`
315			`.dat_en_in ( ad_load_ctrl_low ),`
316			`.en_en_in ( 1'b1 ),`
317			`.dat_in ( temp_ad[1] ) ,`
318			`.en_in ( ad_en_ctrl_low ) ,`
319			`.en_out ( ad_en_out[1] ),`
320			`.dat_out ( ad_out[1] )`
321			`);`
322
323	77	mihad	`pci_out_reg ad_iob2`
324	21	mihad	`(`
325	2	mihad	`.reset_in ( reset_in ),`
326			`.clk_in ( clk_in) ,`
327			`.dat_en_in ( ad_load_ctrl_low ),`
328			`.en_en_in ( 1'b1 ),`
329			`.dat_in ( temp_ad[2] ) ,`
330			`.en_in ( ad_en_ctrl_low ) ,`
331			`.en_out ( ad_en_out[2] ),`
332			`.dat_out ( ad_out[2] )`
333			`);`
334
335	77	mihad	`pci_out_reg ad_iob3`
336	21	mihad	`(`
337	2	mihad	`.reset_in ( reset_in ),`
338			`.clk_in ( clk_in) ,`
339			`.dat_en_in ( ad_load_ctrl_low ),`
340			`.en_en_in ( 1'b1 ),`
341			`.dat_in ( temp_ad[3] ) ,`
342			`.en_in ( ad_en_ctrl_low ) ,`
343			`.en_out ( ad_en_out[3] ),`
344			`.dat_out ( ad_out[3] )`
345			`);`
346
347	77	mihad	`pci_out_reg ad_iob4`
348	21	mihad	`(`
349	2	mihad	`.reset_in ( reset_in ),`
350			`.clk_in ( clk_in) ,`
351			`.dat_en_in ( ad_load_ctrl_low ),`
352			`.en_en_in ( 1'b1 ),`
353			`.dat_in ( temp_ad[4] ) ,`
354			`.en_in ( ad_en_ctrl_low ) ,`
355			`.en_out ( ad_en_out[4] ),`
356			`.dat_out ( ad_out[4] )`
357			`);`
358
359	77	mihad	`pci_out_reg ad_iob5`
360	21	mihad	`(`
361	2	mihad	`.reset_in ( reset_in ),`
362			`.clk_in ( clk_in) ,`
363			`.dat_en_in ( ad_load_ctrl_low ),`
364			`.en_en_in ( 1'b1 ),`
365			`.dat_in ( temp_ad[5] ) ,`
366			`.en_in ( ad_en_ctrl_low ) ,`
367			`.en_out ( ad_en_out[5] ),`
368			`.dat_out ( ad_out[5] )`
369			`);`
370
371	77	mihad	`pci_out_reg ad_iob6`
372	21	mihad	`(`
373	2	mihad	`.reset_in ( reset_in ),`
374			`.clk_in ( clk_in) ,`
375			`.dat_en_in ( ad_load_ctrl_low ),`
376			`.en_en_in ( 1'b1 ),`
377			`.dat_in ( temp_ad[6] ) ,`
378			`.en_in ( ad_en_ctrl_low ) ,`
379			`.en_out ( ad_en_out[6] ),`
380			`.dat_out ( ad_out[6] )`
381			`);`
382
383	77	mihad	`pci_out_reg ad_iob7`
384	21	mihad	`(`
385	2	mihad	`.reset_in ( reset_in ),`
386			`.clk_in ( clk_in) ,`
387			`.dat_en_in ( ad_load_ctrl_low ),`
388			`.en_en_in ( 1'b1 ),`
389			`.dat_in ( temp_ad[7] ) ,`
390			`.en_in ( ad_en_ctrl_low ) ,`
391			`.en_out ( ad_en_out[7] ),`
392			`.dat_out ( ad_out[7] )`
393			`);`
394
395	77	mihad	`pci_out_reg ad_iob8`
396	21	mihad	`(`
397	2	mihad	`.reset_in ( reset_in ),`
398			`.clk_in ( clk_in) ,`
399			`.dat_en_in ( ad_load_ctrl_mlow ),`
400			`.en_en_in ( 1'b1 ),`
401			`.dat_in ( temp_ad[8] ) ,`
402			`.en_in ( ad_en_ctrl_mlow ) ,`
403			`.en_out ( ad_en_out[8] ),`
404			`.dat_out ( ad_out[8] )`
405			`);`
406
407	77	mihad	`pci_out_reg ad_iob9`
408	21	mihad	`(`
409	2	mihad	`.reset_in ( reset_in ),`
410			`.clk_in ( clk_in) ,`
411			`.dat_en_in ( ad_load_ctrl_mlow ),`
412			`.en_en_in ( 1'b1 ),`
413			`.dat_in ( temp_ad[9] ) ,`
414			`.en_in ( ad_en_ctrl_mlow ) ,`
415			`.en_out ( ad_en_out[9] ),`
416			`.dat_out ( ad_out[9] )`
417			`);`
418
419	77	mihad	`pci_out_reg ad_iob10`
420	21	mihad	`(`
421	2	mihad	`.reset_in ( reset_in ),`
422			`.clk_in ( clk_in) ,`
423			`.dat_en_in ( ad_load_ctrl_mlow ),`
424			`.en_en_in ( 1'b1 ),`
425			`.dat_in ( temp_ad[10] ) ,`
426			`.en_in ( ad_en_ctrl_mlow ) ,`
427			`.en_out ( ad_en_out[10] ),`
428			`.dat_out ( ad_out[10] )`
429			`);`
430
431	77	mihad	`pci_out_reg ad_iob11`
432	21	mihad	`(`
433	2	mihad	`.reset_in ( reset_in ),`
434			`.clk_in ( clk_in) ,`
435			`.dat_en_in ( ad_load_ctrl_mlow ),`
436			`.en_en_in ( 1'b1 ),`
437			`.dat_in ( temp_ad[11] ) ,`
438			`.en_in ( ad_en_ctrl_mlow ) ,`
439			`.en_out ( ad_en_out[11] ),`
440			`.dat_out ( ad_out[11] )`
441			`);`
442
443	77	mihad	`pci_out_reg ad_iob12`
444	21	mihad	`(`
445	2	mihad	`.reset_in ( reset_in ),`
446			`.clk_in ( clk_in) ,`
447			`.dat_en_in ( ad_load_ctrl_mlow ),`
448			`.en_en_in ( 1'b1 ),`
449			`.dat_in ( temp_ad[12] ) ,`
450			`.en_in ( ad_en_ctrl_mlow ) ,`
451			`.en_out ( ad_en_out[12] ),`
452			`.dat_out ( ad_out[12] )`
453			`);`
454
455	77	mihad	`pci_out_reg ad_iob13`
456	21	mihad	`(`
457	2	mihad	`.reset_in ( reset_in ),`
458			`.clk_in ( clk_in) ,`
459			`.dat_en_in ( ad_load_ctrl_mlow ),`
460			`.en_en_in ( 1'b1 ),`
461			`.dat_in ( temp_ad[13] ) ,`
462			`.en_in ( ad_en_ctrl_mlow ) ,`
463			`.en_out ( ad_en_out[13] ),`
464			`.dat_out ( ad_out[13] )`
465			`);`
466
467	77	mihad	`pci_out_reg ad_iob14`
468	21	mihad	`(`
469	2	mihad	`.reset_in ( reset_in ),`
470			`.clk_in ( clk_in) ,`
471			`.dat_en_in ( ad_load_ctrl_mlow ),`
472			`.en_en_in ( 1'b1 ),`
473			`.dat_in ( temp_ad[14] ) ,`
474			`.en_in ( ad_en_ctrl_mlow ) ,`
475			`.en_out ( ad_en_out[14] ),`
476			`.dat_out ( ad_out[14] )`
477			`);`
478
479	77	mihad	`pci_out_reg ad_iob15`
480	21	mihad	`(`
481	2	mihad	`.reset_in ( reset_in ),`
482			`.clk_in ( clk_in) ,`
483			`.dat_en_in ( ad_load_ctrl_mlow ),`
484			`.en_en_in ( 1'b1 ),`
485			`.dat_in ( temp_ad[15] ) ,`
486			`.en_in ( ad_en_ctrl_mlow ) ,`
487			`.en_out ( ad_en_out[15] ),`
488			`.dat_out ( ad_out[15] )`
489			`);`
490
491	77	mihad	`pci_out_reg ad_iob16`
492	21	mihad	`(`
493	2	mihad	`.reset_in ( reset_in ),`
494			`.clk_in ( clk_in) ,`
495			`.dat_en_in ( ad_load_ctrl_mhigh ),`
496			`.en_en_in ( 1'b1 ),`
497			`.dat_in ( temp_ad[16] ) ,`
498			`.en_in ( ad_en_ctrl_mhigh ) ,`
499			`.en_out ( ad_en_out[16] ),`
500			`.dat_out ( ad_out[16] )`

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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_io_mux.v] - Blame information for rev 154