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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_out_reg.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "out_reg.v"                                       ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/02/01 15:25:12  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:28  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
`include "pci_constants.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// module inferes a single IOB output block as known in FPGA architectures
// It provides data flip flop with clock enable and output enable flip flop with clock enable
// This is tested in Xilinx FPGA - active low output enable
// Check polarity of output enable flip flop for specific architecure.
module pci_out_reg
(
    reset_in,
    clk_in,
    dat_en_in,
    en_en_in,
    dat_in,
    en_in,
    en_out,
    dat_out
);
 
input   reset_in,
        clk_in,
        dat_en_in,
        en_en_in,
        dat_in,
        en_in ;
 
output dat_out ;
output en_out ;
 
reg dat_out,
    en_out ;
 
`ifdef ACTIVE_LOW_OE
wire en = ~en_in ;
`else
`ifdef ACTIVE_HIGH_OE
wire en = en_in ;
`endif
`endif
 
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        dat_out <= #`FF_DELAY 1'b0 ;
    else if ( dat_en_in )
        dat_out <= #`FF_DELAY dat_in ;
end
 
always@(posedge reset_in or posedge clk_in)
begin
    if ( reset_in )
        `ifdef ACTIVE_LOW_OE
        en_out <= #`FF_DELAY 1'b1 ;
        `else
        `ifdef ACTIVE_HIGH_OE
        en_out <= #`FF_DELAY 1'b0 ;
        `endif
        `endif
    else if ( en_en_in )
        en_out <= #`FF_DELAY en ;
end
 
endmodule

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "out_reg.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`// Revision 1.3 2002/02/01 15:25:12 mihad`
46			`// Repaired a few bugs, updated specification, added test bench files and design document`
47			`//`
48			`// Revision 1.2 2001/10/05 08:14:28 mihad`
49			`// Updated all files with inclusion of timescale file for simulation purposes.`
50			`//`
51			`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
52			`// New project directory structure`
53			`//`
54			`//`
55
56			`include "pci_constants.v"
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61
62			`// module inferes a single IOB output block as known in FPGA architectures`
63			`// It provides data flip flop with clock enable and output enable flip flop with clock enable`
64			`// This is tested in Xilinx FPGA - active low output enable`
65			`// Check polarity of output enable flip flop for specific architecure.`
66			`module pci_out_reg`
67			`(`
68			`reset_in,`
69			`clk_in,`
70			`dat_en_in,`
71			`en_en_in,`
72			`dat_in,`
73			`en_in,`
74			`en_out,`
75			`dat_out`
76			`);`
77
78			`input reset_in,`
79			`clk_in,`
80			`dat_en_in,`
81			`en_en_in,`
82			`dat_in,`
83			`en_in ;`
84
85			`output dat_out ;`
86			`output en_out ;`
87
88			`reg dat_out,`
89			`en_out ;`
90
91			`ifdef ACTIVE_LOW_OE
92			`wire en = ~en_in ;`
93			`else
94			`ifdef ACTIVE_HIGH_OE
95			`wire en = en_in ;`
96			`endif
97			`endif
98
99			`always@(posedge reset_in or posedge clk_in)`
100			`begin`
101			`if ( reset_in )`
102			dat_out <= #`FF_DELAY 1'b0 ;
103			`else if ( dat_en_in )`
104			dat_out <= #`FF_DELAY dat_in ;
105			`end`
106
107			`always@(posedge reset_in or posedge clk_in)`
108			`begin`
109			`if ( reset_in )`
110			`ifdef ACTIVE_LOW_OE
111			en_out <= #`FF_DELAY 1'b1 ;
112			`else
113			`ifdef ACTIVE_HIGH_OE
114			en_out <= #`FF_DELAY 1'b0 ;
115			`endif
116			`endif
117			`else if ( en_en_in )`
118			en_out <= #`FF_DELAY en ;
119			`end`
120
121			`endmodule`

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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_out_reg.v] - Blame information for rev 154