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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_sync_module.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "sync_module.v"                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Tadej Markovic, tadej@opencores.org                   ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/03/26 13:16:18  mihad
// Added the reset value parameter to the synchronizer flop module.
// Added resets to all synchronizer flop instances.
// Repaired initial sync value in fifos.
//
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_sync_module
(
                                        set_clk_in,
                                        delete_clk_in,
                                        reset_in,
                                        delete_set_out,
                                        block_set_out,
                                        delete_in
);
 
// system inputs from two clock domains
input   set_clk_in;
input   delete_clk_in;
input   reset_in;
// control outputs
output  delete_set_out;
output  block_set_out;
// control input
input   delete_in;
 
// internal signals
reg             del_bit;
wire    meta_del_bit;
reg             sync_del_bit;
reg             delayed_del_bit;
wire    meta_bckp_bit;
reg             sync_bckp_bit;
reg             delayed_bckp_bit;
 
 
// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
always@(posedge delete_clk_in or posedge reset_in)
begin
        if (reset_in)
                del_bit <= 1'b0;
        else
        begin
                if (!delayed_bckp_bit && sync_bckp_bit)
                        del_bit <= 1'b0;
                else if (delete_in)
                        del_bit <= 1'b1;
        end
end
assign  block_set_out = del_bit;
 
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop   #(1, 0) delete_sync
(
    .data_in        (del_bit),
    .clk_out        (set_clk_in),
    .sync_data_out  (meta_del_bit),
    .async_reset    (reset_in)
) ;
 
// Final synchronization of del_bit signal to the set clock domain
always@(posedge set_clk_in or posedge reset_in)
begin
        if (reset_in)
                sync_del_bit <= 1'b0;
        else
                sync_del_bit <= meta_del_bit;
end
 
// Delayed sync_del_bit signal for one clock period pulse generation
always@(posedge set_clk_in or posedge reset_in)
begin
        if (reset_in)
                delayed_del_bit <= 1'b0;
        else
                delayed_del_bit <= sync_del_bit;
end
 
assign  delete_set_out = !delayed_del_bit && sync_del_bit;
 
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop   #(1, 0) clear_delete_sync
(
    .data_in        (sync_del_bit),
    .clk_out        (delete_clk_in),
    .sync_data_out  (meta_bckp_bit),
    .async_reset    (reset_in)
) ;
 
// Final synchronization of sync_del_bit signal to the delete clock domain
always@(posedge delete_clk_in or posedge reset_in)
begin
        if (reset_in)
                sync_bckp_bit <= 1'b0;
        else
                sync_bckp_bit <= meta_bckp_bit;
end
 
// Delayed sync_bckp_bit signal for one clock period pulse generation
always@(posedge delete_clk_in or posedge reset_in)
begin
        if (reset_in)
                delayed_bckp_bit <= 1'b0;
        else
                delayed_bckp_bit <= sync_bckp_bit;
end
 
endmodule

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "sync_module.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Tadej Markovic, tadej@opencores.org ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	111	simons	`// Revision 1.2 2003/03/26 13:16:18 mihad`
46			`// Added the reset value parameter to the synchronizer flop module.`
47			`// Added resets to all synchronizer flop instances.`
48			`// Repaired initial sync value in fifos.`
49			`//`
50	88	mihad	`// Revision 1.1 2003/01/27 16:49:31 mihad`
51			`// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.`
52			`//`
53	77	mihad	`// Revision 1.1 2002/02/01 14:43:31 mihad`
54			`// * empty log message *`
55			`//`
56			`//`
57			`//`
58
59			`// synopsys translate_off`
60			`include "timescale.v"
61			`// synopsys translate_on`
62
63			`module pci_sync_module`
64			`(`
65			`set_clk_in,`
66			`delete_clk_in,`
67			`reset_in,`
68			`delete_set_out,`
69			`block_set_out,`
70			`delete_in`
71			`);`
72
73			`// system inputs from two clock domains`
74			`input set_clk_in;`
75			`input delete_clk_in;`
76			`input reset_in;`
77			`// control outputs`
78			`output delete_set_out;`
79			`output block_set_out;`
80			`// control input`
81			`input delete_in;`
82
83			`// internal signals`
84			`reg del_bit;`
85			`wire meta_del_bit;`
86			`reg sync_del_bit;`
87			`reg delayed_del_bit;`
88			`wire meta_bckp_bit;`
89			`reg sync_bckp_bit;`
90			`reg delayed_bckp_bit;`
91
92
93			`// DELETE_IN input FF - when set must be active, until it is sinchronously cleared`
94			`always@(posedge delete_clk_in or posedge reset_in)`
95			`begin`
96			`if (reset_in)`
97			`del_bit <= 1'b0;`
98			`else`
99			`begin`
100			`if (!delayed_bckp_bit && sync_bckp_bit)`
101			`del_bit <= 1'b0;`
102			`else if (delete_in)`
103			`del_bit <= 1'b1;`
104			`end`
105			`end`
106			`assign block_set_out = del_bit;`
107
108			`// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability`
109	111	simons	`pci_synchronizer_flop #(1, 0) delete_sync`
110	77	mihad	`(`
111			`.data_in (del_bit),`
112			`.clk_out (set_clk_in),`
113			`.sync_data_out (meta_del_bit),`
114			`.async_reset (reset_in)`
115			`) ;`
116
117			`// Final synchronization of del_bit signal to the set clock domain`
118			`always@(posedge set_clk_in or posedge reset_in)`
119			`begin`
120			`if (reset_in)`
121			`sync_del_bit <= 1'b0;`
122			`else`
123			`sync_del_bit <= meta_del_bit;`
124			`end`
125
126			`// Delayed sync_del_bit signal for one clock period pulse generation`
127			`always@(posedge set_clk_in or posedge reset_in)`
128			`begin`
129			`if (reset_in)`
130			`delayed_del_bit <= 1'b0;`
131			`else`
132			`delayed_del_bit <= sync_del_bit;`
133			`end`
134
135			`assign delete_set_out = !delayed_del_bit && sync_del_bit;`
136
137			`// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability`
138	111	simons	`pci_synchronizer_flop #(1, 0) clear_delete_sync`
139	77	mihad	`(`
140			`.data_in (sync_del_bit),`
141			`.clk_out (delete_clk_in),`
142			`.sync_data_out (meta_bckp_bit),`
143			`.async_reset (reset_in)`
144			`) ;`
145
146			`// Final synchronization of sync_del_bit signal to the delete clock domain`
147			`always@(posedge delete_clk_in or posedge reset_in)`
148			`begin`
149			`if (reset_in)`
150			`sync_bckp_bit <= 1'b0;`
151			`else`
152			`sync_bckp_bit <= meta_bckp_bit;`
153			`end`
154
155			`// Delayed sync_bckp_bit signal for one clock period pulse generation`
156			`always@(posedge delete_clk_in or posedge reset_in)`
157			`begin`
158			`if (reset_in)`
159			`delayed_bckp_bit <= 1'b0;`
160			`else`
161			`delayed_bckp_bit <= sync_bckp_bit;`
162			`end`
163
164			`endmodule`

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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_sync_module.v] - Blame information for rev 154