URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_sync_module.v] - Blame information for rev 88

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "sync_module.v"                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Tadej Markovic, tadej@opencores.org                   ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_sync_module
(
                                        set_clk_in,
                                        delete_clk_in,
                                        reset_in,
                                        delete_set_out,
                                        block_set_out,
                                        delete_in
);
 
// system inputs from two clock domains
input   set_clk_in;
input   delete_clk_in;
input   reset_in;
// control outputs
output  delete_set_out;
output  block_set_out;
// control input
input   delete_in;
 
// internal signals
reg             del_bit;
wire    meta_del_bit;
reg             sync_del_bit;
reg             delayed_del_bit;
wire    meta_bckp_bit;
reg             sync_bckp_bit;
reg             delayed_bckp_bit;
 
 
// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
always@(posedge delete_clk_in or posedge reset_in)
begin
        if (reset_in)
                del_bit <= 1'b0;
        else
        begin
                if (!delayed_bckp_bit && sync_bckp_bit)
                        del_bit <= 1'b0;
                else if (delete_in)
                        del_bit <= 1'b1;
        end
end
assign  block_set_out = del_bit;
 
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
synchronizer_flop       #(1, 0) delete_sync
(
    .data_in        (del_bit),
    .clk_out        (set_clk_in),
    .sync_data_out  (meta_del_bit),
    .async_reset    (reset_in)
) ;
 
// Final synchronization of del_bit signal to the set clock domain
always@(posedge set_clk_in or posedge reset_in)
begin
        if (reset_in)
                sync_del_bit <= 1'b0;
        else
                sync_del_bit <= meta_del_bit;
end
 
// Delayed sync_del_bit signal for one clock period pulse generation
always@(posedge set_clk_in or posedge reset_in)
begin
        if (reset_in)
                delayed_del_bit <= 1'b0;
        else
                delayed_del_bit <= sync_del_bit;
end
 
assign  delete_set_out = !delayed_del_bit && sync_del_bit;
 
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
synchronizer_flop       #(1, 0) clear_delete_sync
(
    .data_in        (sync_del_bit),
    .clk_out        (delete_clk_in),
    .sync_data_out  (meta_bckp_bit),
    .async_reset    (reset_in)
) ;
 
// Final synchronization of sync_del_bit signal to the delete clock domain
always@(posedge delete_clk_in or posedge reset_in)
begin
        if (reset_in)
                sync_bckp_bit <= 1'b0;
        else
                sync_bckp_bit <= meta_bckp_bit;
end
 
// Delayed sync_bckp_bit signal for one clock period pulse generation
always@(posedge delete_clk_in or posedge reset_in)
begin
        if (reset_in)
                delayed_bckp_bit <= 1'b0;
        else
                delayed_bckp_bit <= sync_bckp_bit;
end
 
endmodule

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "sync_module.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Tadej Markovic, tadej@opencores.org ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	88	mihad	`// Revision 1.1 2003/01/27 16:49:31 mihad`
46			`// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.`
47			`//`
48	77	mihad	`// Revision 1.1 2002/02/01 14:43:31 mihad`
49			`// * empty log message *`
50			`//`
51			`//`
52			`//`
53
54			`// synopsys translate_off`
55			`include "timescale.v"
56			`// synopsys translate_on`
57
58			`module pci_sync_module`
59			`(`
60			`set_clk_in,`
61			`delete_clk_in,`
62			`reset_in,`
63			`delete_set_out,`
64			`block_set_out,`
65			`delete_in`
66			`);`
67
68			`// system inputs from two clock domains`
69			`input set_clk_in;`
70			`input delete_clk_in;`
71			`input reset_in;`
72			`// control outputs`
73			`output delete_set_out;`
74			`output block_set_out;`
75			`// control input`
76			`input delete_in;`
77
78			`// internal signals`
79			`reg del_bit;`
80			`wire meta_del_bit;`
81			`reg sync_del_bit;`
82			`reg delayed_del_bit;`
83			`wire meta_bckp_bit;`
84			`reg sync_bckp_bit;`
85			`reg delayed_bckp_bit;`
86
87
88			`// DELETE_IN input FF - when set must be active, until it is sinchronously cleared`
89			`always@(posedge delete_clk_in or posedge reset_in)`
90			`begin`
91			`if (reset_in)`
92			`del_bit <= 1'b0;`
93			`else`
94			`begin`
95			`if (!delayed_bckp_bit && sync_bckp_bit)`
96			`del_bit <= 1'b0;`
97			`else if (delete_in)`
98			`del_bit <= 1'b1;`
99			`end`
100			`end`
101			`assign block_set_out = del_bit;`
102
103			`// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability`
104	88	mihad	`synchronizer_flop #(1, 0) delete_sync`
105	77	mihad	`(`
106			`.data_in (del_bit),`
107			`.clk_out (set_clk_in),`
108			`.sync_data_out (meta_del_bit),`
109			`.async_reset (reset_in)`
110			`) ;`
111
112			`// Final synchronization of del_bit signal to the set clock domain`
113			`always@(posedge set_clk_in or posedge reset_in)`
114			`begin`
115			`if (reset_in)`
116			`sync_del_bit <= 1'b0;`
117			`else`
118			`sync_del_bit <= meta_del_bit;`
119			`end`
120
121			`// Delayed sync_del_bit signal for one clock period pulse generation`
122			`always@(posedge set_clk_in or posedge reset_in)`
123			`begin`
124			`if (reset_in)`
125			`delayed_del_bit <= 1'b0;`
126			`else`
127			`delayed_del_bit <= sync_del_bit;`
128			`end`
129
130			`assign delete_set_out = !delayed_del_bit && sync_del_bit;`
131
132			`// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability`
133	88	mihad	`synchronizer_flop #(1, 0) clear_delete_sync`
134	77	mihad	`(`
135			`.data_in (sync_del_bit),`
136			`.clk_out (delete_clk_in),`
137			`.sync_data_out (meta_bckp_bit),`
138			`.async_reset (reset_in)`
139			`) ;`
140
141			`// Final synchronization of sync_del_bit signal to the delete clock domain`
142			`always@(posedge delete_clk_in or posedge reset_in)`
143			`begin`
144			`if (reset_in)`
145			`sync_bckp_bit <= 1'b0;`
146			`else`
147			`sync_bckp_bit <= meta_bckp_bit;`
148			`end`
149
150			`// Delayed sync_bckp_bit signal for one clock period pulse generation`
151			`always@(posedge delete_clk_in or posedge reset_in)`
152			`begin`
153			`if (reset_in)`
154			`delayed_bckp_bit <= 1'b0;`
155			`else`
156			`delayed_bckp_bit <= sync_bckp_bit;`
157			`end`
158
159			`endmodule`

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_sync_module.v] - Blame information for rev 88