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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_wb_addr_mux.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_addr_mux.v"                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/08/19 16:54:25  mihad
// Got rid of undef directives
//
// Revision 1.3  2002/02/01 15:25:13  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
//
//
 
// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images
`include "pci_constants.v"
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_wb_addr_mux
(
    `ifdef REGISTER_WBS_OUTPUTS
    clk_in,
    reset_in,
    sample_address_in,
    `endif
    address_in,
    bar0_in,
    bar1_in,
    bar2_in,
    bar3_in,
    bar4_in,
    bar5_in,
    am0_in,
    am1_in,
    am2_in,
    am3_in,
    am4_in,
    am5_in,
    ta0_in,
    ta1_in,
    ta2_in,
    ta3_in,
    ta4_in,
    ta5_in,
    at_en_in,
    hit_out,
    address_out
);
 
input [31:0] address_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in  ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in   ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in   ;
input [5:0]  at_en_in ;
output [5:0] hit_out  ;
output [31:0] address_out ;
reg    [31:0] address_out ;
 
wire [31:0] addr0 ;
wire [31:0] addr1 ;
wire [31:0] addr2 ;
wire [31:0] addr3 ;
wire [31:0] addr4 ;
wire [31:0] addr5 ;
 
wire [5:0] hit ;
assign hit_out = hit ;
 
`ifdef REGISTER_WBS_OUTPUTS
    input clk_in, reset_in, sample_address_in ;
 
    reg [31:0] address ;
    always@(posedge clk_in or posedge reset_in)
    begin
       if ( reset_in )
           address <= #`FF_DELAY 0 ;
       else
       if ( sample_address_in )
           address <= #`FF_DELAY address_in ;
    end
`else
    wire [31:0] address = address_in ;
`endif
 
`ifdef GUEST
    `ifdef NO_CNF_IMAGE
    `else
        `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
    `endif
`else
`ifdef HOST
    `define PCI_WB_ADDR_MUX_DEC0_INCLUDE
`endif
`endif
 
`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
    (
     .hit       (hit[0]),
     .addr_out  (addr0),
     .addr_in   (address),
     .base_addr (bar0_in),
     .mask_addr (am0_in),
     .tran_addr (ta0_in),
     .at_en     (1'b0)
    ) ;
`else
    // configuration image not implemented
    assign hit[0] = 1'b0 ;
    assign addr0  = 32'h0000_0000 ;
`endif
 
// one image is always implemented
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
(
 .hit       (hit[1]),
 .addr_out  (addr1),
 .addr_in   (address),
 .base_addr (bar1_in),
 .mask_addr (am1_in),
 .tran_addr (ta1_in),
 .at_en     (at_en_in[1])
) ;
 
`ifdef WB_IMAGE2
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
    (
     .hit       (hit[2]),
     .addr_out  (addr2),
     .addr_in   (address),
     .base_addr (bar2_in),
     .mask_addr (am2_in),
     .tran_addr (ta2_in),
     .at_en     (at_en_in[2])
    ) ;
 
`else
    assign hit[2] = 1'b0 ;
    assign addr2  = 0 ;
`endif
 
`ifdef WB_IMAGE3
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
    (
     .hit       (hit[3]),
     .addr_out  (addr3),
     .addr_in   (address),
     .base_addr (bar3_in),
     .mask_addr (am3_in),
     .tran_addr (ta3_in),
     .at_en     (at_en_in[3])
    ) ;
`else
    assign hit[3] = 1'b0 ;
    assign addr3  = 0 ;
`endif
 
`ifdef WB_IMAGE4
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
    (
     .hit       (hit[4]),
     .addr_out  (addr4),
     .addr_in   (address),
     .base_addr (bar4_in),
     .mask_addr (am4_in),
     .tran_addr (ta4_in),
     .at_en     (at_en_in[4])
    ) ;
`else
    assign hit[4] = 1'b0 ;
    assign addr4  = 0 ;
`endif
 
`ifdef WB_IMAGE5
    pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
    (
     .hit       (hit[5]),
     .addr_out  (addr5),
     .addr_in   (address),
     .base_addr (bar5_in),
     .mask_addr (am5_in),
     .tran_addr (ta5_in),
     .at_en     (at_en_in[5])
    ) ;
`else
    assign hit[5] = 1'b0 ;
    assign addr5  = 0 ;
`endif
 
// address multiplexer
always@
(
 hit or
 addr0 or
 addr1 or
 addr2 or
 addr3 or
 addr4 or
 addr5
)
begin
    case ( {hit[5:2], hit[0]} )
        5'b0_0_0_0_1: address_out = addr0 ;
        5'b0_0_0_1_0: address_out = addr2 ;
        5'b0_0_1_0_0: address_out = addr3 ;
        5'b0_1_0_0_0: address_out = addr4 ;
        5'b1_0_0_0_0: address_out = addr5 ;
 
        // default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image
        // this multiplexer can be completely removed during synthesys
        default:      address_out = addr1 ;
    endcase
end
 
endmodule

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_wb_addr_mux.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_addr_mux.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`// Revision 1.4 2002/08/19 16:54:25 mihad`
46			`// Got rid of undef directives`
47			`//`
48			`// Revision 1.3 2002/02/01 15:25:13 mihad`
49			`// Repaired a few bugs, updated specification, added test bench files and design document`
50			`//`
51			`// Revision 1.2 2001/10/05 08:14:30 mihad`
52			`// Updated all files with inclusion of timescale file for simulation purposes.`
53			`//`
54			`// Revision 1.1.1.1 2001/10/02 15:33:47 mihad`
55			`// New project directory structure`
56			`//`
57			`//`
58
59			`// module provides instantiation of address decoders and address multiplexer for various number of implemented wishbone images`
60			`include "pci_constants.v"
61			`// synopsys translate_off`
62			`include "timescale.v"
63			`// synopsys translate_on`
64
65			`module pci_wb_addr_mux`
66			`(`
67			`ifdef REGISTER_WBS_OUTPUTS
68			`clk_in,`
69			`reset_in,`
70			`sample_address_in,`
71			`endif
72			`address_in,`
73			`bar0_in,`
74			`bar1_in,`
75			`bar2_in,`
76			`bar3_in,`
77			`bar4_in,`
78			`bar5_in,`
79			`am0_in,`
80			`am1_in,`
81			`am2_in,`
82			`am3_in,`
83			`am4_in,`
84			`am5_in,`
85			`ta0_in,`
86			`ta1_in,`
87			`ta2_in,`
88			`ta3_in,`
89			`ta4_in,`
90			`ta5_in,`
91			`at_en_in,`
92			`hit_out,`
93			`address_out`
94			`);`
95
96			`input [31:0] address_in ;`
97			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
98			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
99			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
100			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
101			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
102			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
103			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
104			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
105			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
106			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
107			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
108			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
109			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
110			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
111			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
112			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
113			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
114			input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
115			`input [5:0] at_en_in ;`
116			`output [5:0] hit_out ;`
117			`output [31:0] address_out ;`
118			`reg [31:0] address_out ;`
119
120			`wire [31:0] addr0 ;`
121			`wire [31:0] addr1 ;`
122			`wire [31:0] addr2 ;`
123			`wire [31:0] addr3 ;`
124			`wire [31:0] addr4 ;`
125			`wire [31:0] addr5 ;`
126
127			`wire [5:0] hit ;`
128			`assign hit_out = hit ;`
129
130			`ifdef REGISTER_WBS_OUTPUTS
131			`input clk_in, reset_in, sample_address_in ;`
132
133			`reg [31:0] address ;`
134			`always@(posedge clk_in or posedge reset_in)`
135			`begin`
136			`if ( reset_in )`
137			address <= #`FF_DELAY 0 ;
138			`else`
139			`if ( sample_address_in )`
140			address <= #`FF_DELAY address_in ;
141			`end`
142			`else
143			`wire [31:0] address = address_in ;`
144			`endif
145
146			`ifdef GUEST
147			`ifdef NO_CNF_IMAGE
148			`else
149			`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
150			`endif
151			`else
152			`ifdef HOST
153			`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
154			`endif
155			`endif
156
157			`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
158			pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
159			`(`
160			`.hit (hit[0]),`
161			`.addr_out (addr0),`
162			`.addr_in (address),`
163			`.base_addr (bar0_in),`
164			`.mask_addr (am0_in),`
165			`.tran_addr (ta0_in),`
166			`.at_en (1'b0)`
167			`) ;`
168			`else
169			`// configuration image not implemented`
170			`assign hit[0] = 1'b0 ;`
171			`assign addr0 = 32'h0000_0000 ;`
172			`endif
173
174			`// one image is always implemented`
175			pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
176			`(`
177			`.hit (hit[1]),`
178			`.addr_out (addr1),`
179			`.addr_in (address),`
180			`.base_addr (bar1_in),`
181			`.mask_addr (am1_in),`
182			`.tran_addr (ta1_in),`
183			`.at_en (at_en_in[1])`
184			`) ;`
185
186			`ifdef WB_IMAGE2
187			pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
188			`(`
189			`.hit (hit[2]),`
190			`.addr_out (addr2),`
191			`.addr_in (address),`
192			`.base_addr (bar2_in),`
193			`.mask_addr (am2_in),`
194			`.tran_addr (ta2_in),`
195			`.at_en (at_en_in[2])`
196			`) ;`
197
198			`else
199			`assign hit[2] = 1'b0 ;`
200			`assign addr2 = 0 ;`
201			`endif
202
203			`ifdef WB_IMAGE3
204			pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
205			`(`
206			`.hit (hit[3]),`
207			`.addr_out (addr3),`
208			`.addr_in (address),`
209			`.base_addr (bar3_in),`
210			`.mask_addr (am3_in),`
211			`.tran_addr (ta3_in),`
212			`.at_en (at_en_in[3])`
213			`) ;`
214			`else
215			`assign hit[3] = 1'b0 ;`
216			`assign addr3 = 0 ;`
217			`endif
218
219			`ifdef WB_IMAGE4
220			pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
221			`(`
222			`.hit (hit[4]),`
223			`.addr_out (addr4),`
224			`.addr_in (address),`
225			`.base_addr (bar4_in),`
226			`.mask_addr (am4_in),`
227			`.tran_addr (ta4_in),`
228			`.at_en (at_en_in[4])`
229			`) ;`
230			`else
231			`assign hit[4] = 1'b0 ;`
232			`assign addr4 = 0 ;`
233			`endif
234
235			`ifdef WB_IMAGE5
236			pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
237			`(`
238			`.hit (hit[5]),`
239			`.addr_out (addr5),`
240			`.addr_in (address),`
241			`.base_addr (bar5_in),`
242			`.mask_addr (am5_in),`
243			`.tran_addr (ta5_in),`
244			`.at_en (at_en_in[5])`
245			`) ;`
246			`else
247			`assign hit[5] = 1'b0 ;`
248			`assign addr5 = 0 ;`
249			`endif
250
251			`// address multiplexer`
252			`always@`
253			`(`
254			`hit or`
255			`addr0 or`
256			`addr1 or`
257			`addr2 or`
258			`addr3 or`
259			`addr4 or`
260			`addr5`
261			`)`
262			`begin`
263			`case ( {hit[5:2], hit[0]} )`
264			`5'b0_0_0_0_1: address_out = addr0 ;`
265			`5'b0_0_0_1_0: address_out = addr2 ;`
266			`5'b0_0_1_0_0: address_out = addr3 ;`
267			`5'b0_1_0_0_0: address_out = addr4 ;`
268			`5'b1_0_0_0_0: address_out = addr5 ;`
269
270			`// default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image`
271			`// this multiplexer can be completely removed during synthesys`
272			`default: address_out = addr1 ;`
273			`endcase`
274			`end`
275
276			`endmodule`