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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_wb_tpram.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of pci bridge project                     ////
////  http://www.opencores.org/cvsweb.shtml/pci/                  ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (Altera, VS etc)                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Miha Dolenc, mihad@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.7  2002/10/18 03:36:37  tadejm
// Changed wrong signal name scanb_sen into scanb_en.
//
// Revision 1.6  2002/10/17 22:49:22  tadejm
// Changed BIST signals for RAMs.
//
// Revision 1.5  2002/10/11 10:09:01  mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.4  2002/10/08 17:17:06  mihad
// Added BIST signals for RAMs.
//
// Revision 1.3  2002/09/30 17:22:27  mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.2  2002/08/19 16:51:36  mihad
// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
//
// Revision 1.1  2002/02/01 14:43:31  mihad
// *** empty log message ***
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module pci_wb_tpram
(
        // Generic synchronous two-port RAM interface
        clk_a,
    rst_a,
    ce_a,
    we_a,
    oe_a,
    addr_a,
    di_a,
    do_a,
        clk_b,
    rst_b,
    ce_b,
    we_b,
    oe_b,
    addr_b,
    di_b,
    do_b
`ifdef PCI_BIST
    ,
    // debug chain signals
    scanb_rst,      // bist scan reset
    scanb_clk,      // bist scan clock
    scanb_si,       // bist scan serial in
    scanb_so,       // bist scan serial out
    scanb_en        // bist scan shift enable
`endif
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
`ifdef PCI_BIST
// debug chain signals
input   scanb_rst;      // bist scan reset
input   scanb_clk;      // bist scan clock
input   scanb_si;       // bist scan serial in
output  scanb_so;       // bist scan serial out
input   scanb_en;       // bist scan shift enable
`endif
 
//
// Internal wires and registers
//
 
`ifdef WB_VS_STP
    `define PCI_WB_RAM_SELECTED
    `ifdef PCI_BIST
        vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
    `else
        vs_hdtp_64x40 i_vs_hdtp_64x40
    `endif
        (
            .RCK        (clk_b),
            .WCK        (clk_a),
            .RADR       (addr_b),
            .WADR       (addr_a),
            .DI         (di_a),
            .DOUT       (do_b),
            .REN        (1'b0),
            .WEN        (!we_a)
        `ifdef PCI_BIST
            ,
            // debug chain signals
            .scanb_rst  (scanb_rst),
            .scanb_clk  (scanb_clk),
            .scanb_si   (scanb_si),
            .scanb_so   (scanb_so),
            .scanb_en   (scanb_en)
        `endif
        );
 
    assign do_a = 0 ;
`endif
 
`ifdef WB_ARTISAN_SDP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Artisan Synchronous Double-Port RAM (ra2sh)
    //
    `ifdef PCI_BIST
        art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp
        (
                .QA(do_a),
                .CLKA(clk_a),
                .CENA(~ce_a),
                .WENA(~we_a),
                .AA(addr_a),
                .DA(di_a),
                .OENA(~oe_a),
                .QB(do_b),
                .CLKB(clk_b),
                .CENB(~ce_b),
                .WENB(~we_b),
                .AB(addr_b),
                .DB(di_b),
                .OENB(~oe_b),
          .scanb_rst  (scanb_rst),
          .scanb_clk  (scanb_clk),
          .scanb_si   (scanb_si),
          .scanb_so   (scanb_so),
          .scanb_en   (scanb_en)
        );
    `else
        art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
        (
                .QA(do_a),
                .CLKA(clk_a),
                .CENA(~ce_a),
                .WENA(~we_a),
                .AA(addr_a),
                .DA(di_a),
                .OENA(~oe_a),
                .QB(do_b),
                .CLKB(clk_b),
                .CENB(~ce_b),
                .WENB(~we_b),
                .AB(addr_b),
                .DB(di_b),
                .OENB(~oe_b)
        );
    `endif
`endif
 
`ifdef AVANT_ATP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Avant! Asynchronous Two-Port RAM
    //
    avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
    );
 
`endif
 
`ifdef VIRAGE_STP
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of ASIC memory:
    //
    // Virage Synchronous 2-port R/W RAM
    //
    virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
    );
 
`endif
 
`ifdef WB_XILINX_DIST_RAM
    `define PCI_WB_RAM_SELECTED
 
    reg [(aw-1):0] out_address ;
    always@(posedge clk_b or posedge rst_b)
    begin
        if ( rst_b )
            out_address <= #1 0 ;
        else if (ce_b)
            out_address <= #1 addr_b ;
    end
 
    pci_ram_16x40d #(aw) wb_distributed_ram
    (
        .data_out       (do_b),
        .we             (we_a),
        .data_in        (di_a),
        .read_address   (out_address),
        .write_address  (addr_a),
        .wclk           (clk_a)
    );
    assign do_a = 0 ;
`endif
`ifdef WB_XILINX_RAMB4
    `define PCI_WB_RAM_SELECTED
    //
    // Instantiation of FPGA memory:
    //
    // Virtex/Spartan2
    //
 
    //
    // Block 0
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
    );
 
    //
    // Block 1
    //
 
    RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
    );
 
    //
    // Block 2
    //
    // block ram2 wires - non generic width of block rams
    wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
    wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
    wire [15:0] blk2_do_a ;
    wire [15:0] blk2_do_b ;
 
    assign do_a[39:32] = blk2_do_a[7:0] ;
    assign do_b[39:32] = blk2_do_b[7:0] ;
 
    RAMB4_S16_S16 ramb4_s16_s16_2(
            .CLKA(clk_a),
            .RSTA(rst_a),
            .ADDRA(addr_a),
            .DIA(blk2_di_a),
            .ENA(ce_a),
            .WEA(we_a),
            .DOA(blk2_do_a),
 
            .CLKB(clk_b),
            .RSTB(rst_b),
            .ADDRB(addr_b),
            .DIB(blk2_di_b),
            .ENB(ce_b),
            .WEB(we_b),
            .DOB(blk2_do_b)
    );
 
`endif
 
`ifdef PCI_WB_RAM_SELECTED
`else
    //
    // Generic two-port synchronous RAM model
    //
 
    //
    // Generic RAM's registers and wires
    //
    reg [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
    reg [dw-1:0] do_reg_a;               // RAM data output register
    reg [dw-1:0] do_reg_b;               // RAM data output register
 
    //
    // Data output drivers
    //
    assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
    assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
    //
    // RAM read and write
    //
    always @(posedge clk_a)
        if (ce_a && !we_a)
                do_reg_a <= #1 mem[addr_a];
        else if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
    //
    // RAM read and write
    //
    always @(posedge clk_b)
        if (ce_b && !we_b)
                do_reg_b <= #1 mem[addr_b];
        else if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
    if (dw !== 40)
    begin
        $display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
        $finish ;
    end
    `ifdef XILINX_RAMB4
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
    // currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
    `ifdef ARTISAN_SDP
        if (aw !== 8)
        begin
            $display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
            $finish ;
        end
    `endif
end
// synopsys translate_on
 
endmodule

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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [pci_wb_tpram.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	77	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of pci bridge project ////`
6			`//// http://www.opencores.org/cvsweb.shtml/pci/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// ////`
26			`//// To Do: ////`
27			`//// - fix Avant! ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - add additional RAMs (Altera, VS etc) ////`
30			`//// ////`
31			`//// Author(s): ////`
32			`//// - Damjan Lampret, lampret@opencores.org ////`
33			`//// - Miha Dolenc, mihad@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65	111	simons	`// Revision 1.1 2003/01/27 16:49:31 mihad`
66			`// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.`
67			`//`
68	77	mihad	`// Revision 1.7 2002/10/18 03:36:37 tadejm`
69			`// Changed wrong signal name scanb_sen into scanb_en.`
70			`//`
71			`// Revision 1.6 2002/10/17 22:49:22 tadejm`
72			`// Changed BIST signals for RAMs.`
73			`//`
74			`// Revision 1.5 2002/10/11 10:09:01 mihad`
75			`// Added additional testcase and changed rst name in BIST to trst`
76			`//`
77			`// Revision 1.4 2002/10/08 17:17:06 mihad`
78			`// Added BIST signals for RAMs.`
79			`//`
80			`// Revision 1.3 2002/09/30 17:22:27 mihad`
81			`// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!`
82			`//`
83			`// Revision 1.2 2002/08/19 16:51:36 mihad`
84			`// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives`
85			`//`
86			`// Revision 1.1 2002/02/01 14:43:31 mihad`
87			`// * empty log message *`
88			`//`
89			`//`
90
91			`// synopsys translate_off`
92			`include "timescale.v"
93			`// synopsys translate_on`
94			`include "pci_constants.v"
95
96			`module pci_wb_tpram`
97			`(`
98			`// Generic synchronous two-port RAM interface`
99			`clk_a,`
100			`rst_a,`
101			`ce_a,`
102			`we_a,`
103			`oe_a,`
104			`addr_a,`
105			`di_a,`
106			`do_a,`
107			`clk_b,`
108			`rst_b,`
109			`ce_b,`
110			`we_b,`
111			`oe_b,`
112			`addr_b,`
113			`di_b,`
114			`do_b`
115			`ifdef PCI_BIST
116			`,`
117			`// debug chain signals`
118			`scanb_rst, // bist scan reset`
119			`scanb_clk, // bist scan clock`
120			`scanb_si, // bist scan serial in`
121			`scanb_so, // bist scan serial out`
122			`scanb_en // bist scan shift enable`
123			`endif
124			`);`
125
126			`//`
127			`// Default address and data buses width`
128			`//`
129			`parameter aw = 8;`
130			`parameter dw = 40;`
131
132			`//`
133			`// Generic synchronous two-port RAM interface`
134			`//`
135			`input clk_a; // Clock`
136			`input rst_a; // Reset`
137			`input ce_a; // Chip enable input`
138			`input we_a; // Write enable input`
139			`input oe_a; // Output enable input`
140			`input [aw-1:0] addr_a; // address bus inputs`
141			`input [dw-1:0] di_a; // input data bus`
142			`output [dw-1:0] do_a; // output data bus`
143			`input clk_b; // Clock`
144			`input rst_b; // Reset`
145			`input ce_b; // Chip enable input`
146			`input we_b; // Write enable input`
147			`input oe_b; // Output enable input`
148			`input [aw-1:0] addr_b; // address bus inputs`
149			`input [dw-1:0] di_b; // input data bus`
150			`output [dw-1:0] do_b; // output data bus`
151
152			`ifdef PCI_BIST
153			`// debug chain signals`
154			`input scanb_rst; // bist scan reset`
155			`input scanb_clk; // bist scan clock`
156			`input scanb_si; // bist scan serial in`
157			`output scanb_so; // bist scan serial out`
158			`input scanb_en; // bist scan shift enable`
159			`endif
160
161			`//`
162			`// Internal wires and registers`
163			`//`
164
165			`ifdef WB_VS_STP
166			`define PCI_WB_RAM_SELECTED
167			`ifdef PCI_BIST
168			`vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist`
169			`else
170			`vs_hdtp_64x40 i_vs_hdtp_64x40`
171			`endif
172			`(`
173			`.RCK (clk_b),`
174			`.WCK (clk_a),`
175			`.RADR (addr_b),`
176			`.WADR (addr_a),`
177			`.DI (di_a),`
178			`.DOUT (do_b),`
179			`.REN (1'b0),`
180			`.WEN (!we_a)`
181			`ifdef PCI_BIST
182			`,`
183			`// debug chain signals`
184			`.scanb_rst (scanb_rst),`
185			`.scanb_clk (scanb_clk),`
186			`.scanb_si (scanb_si),`
187			`.scanb_so (scanb_so),`
188			`.scanb_en (scanb_en)`
189			`endif
190			`);`
191
192			`assign do_a = 0 ;`
193			`endif
194
195			`ifdef WB_ARTISAN_SDP
196			`define PCI_WB_RAM_SELECTED
197			`//`
198			`// Instantiation of ASIC memory:`
199			`//`
200			`// Artisan Synchronous Double-Port RAM (ra2sh)`
201			`//`
202	111	simons	`ifdef PCI_BIST
203			`art_hsdp_64x40_bist /#(dw, 1<<aw, aw) / artisan_sdp`
204			`(`
205			`.QA(do_a),`
206			`.CLKA(clk_a),`
207			`.CENA(~ce_a),`
208			`.WENA(~we_a),`
209			`.AA(addr_a),`
210			`.DA(di_a),`
211			`.OENA(~oe_a),`
212			`.QB(do_b),`
213			`.CLKB(clk_b),`
214			`.CENB(~ce_b),`
215			`.WENB(~we_b),`
216			`.AB(addr_b),`
217			`.DB(di_b),`
218			`.OENB(~oe_b),`
219			`.scanb_rst (scanb_rst),`
220			`.scanb_clk (scanb_clk),`
221			`.scanb_si (scanb_si),`
222			`.scanb_so (scanb_so),`
223			`.scanb_en (scanb_en)`
224			`);`
225			`else
226			`art_hsdp_64x40 /#(dw, 1<<aw, aw) / artisan_sdp`
227			`(`
228			`.QA(do_a),`
229			`.CLKA(clk_a),`
230			`.CENA(~ce_a),`
231			`.WENA(~we_a),`
232			`.AA(addr_a),`
233			`.DA(di_a),`
234			`.OENA(~oe_a),`
235			`.QB(do_b),`
236			`.CLKB(clk_b),`
237			`.CENB(~ce_b),`
238			`.WENB(~we_b),`
239			`.AB(addr_b),`
240			`.DB(di_b),`
241			`.OENB(~oe_b)`
242			`);`
243			`endif
244	77	mihad	`endif
245
246			`ifdef AVANT_ATP
247			`define PCI_WB_RAM_SELECTED
248			`//`
249			`// Instantiation of ASIC memory:`
250			`//`
251			`// Avant! Asynchronous Two-Port RAM`
252			`//`
253			`avant_atp avant_atp(`
254			`.web(~we),`
255			`.reb(),`
256			`.oeb(~oe),`
257			`.rcsb(),`
258			`.wcsb(),`
259			`.ra(addr),`
260			`.wa(addr),`
261			`.di(di),`
262			`.do(do)`
263			`);`
264
265			`endif
266
267			`ifdef VIRAGE_STP
268			`define PCI_WB_RAM_SELECTED
269			`//`
270			`// Instantiation of ASIC memory:`
271			`//`
272			`// Virage Synchronous 2-port R/W RAM`
273			`//`
274			`virage_stp virage_stp(`
275			`.QA(do_a),`
276			`.QB(do_b),`
277
278			`.ADRA(addr_a),`
279			`.DA(di_a),`
280			`.WEA(we_a),`
281			`.OEA(oe_a),`
282			`.MEA(ce_a),`
283			`.CLKA(clk_a),`
284
285			`.ADRB(adr_b),`
286			`.DB(di_b),`
287			`.WEB(we_b),`
288			`.OEB(oe_b),`
289			`.MEB(ce_b),`
290			`.CLKB(clk_b)`
291			`);`
292
293			`endif
294
295			`ifdef WB_XILINX_DIST_RAM
296			`define PCI_WB_RAM_SELECTED
297
298			`reg [(aw-1):0] out_address ;`
299			`always@(posedge clk_b or posedge rst_b)`
300			`begin`
301			`if ( rst_b )`
302			`out_address <= #1 0 ;`
303			`else if (ce_b)`
304			`out_address <= #1 addr_b ;`
305			`end`
306
307			`pci_ram_16x40d #(aw) wb_distributed_ram`
308			`(`
309			`.data_out (do_b),`
310			`.we (we_a),`
311			`.data_in (di_a),`
312			`.read_address (out_address),`
313			`.write_address (addr_a),`
314			`.wclk (clk_a)`
315			`);`
316			`assign do_a = 0 ;`
317			`endif
318			`ifdef WB_XILINX_RAMB4
319			`define PCI_WB_RAM_SELECTED
320			`//`
321			`// Instantiation of FPGA memory:`
322			`//`
323			`// Virtex/Spartan2`
324			`//`
325
326			`//`
327			`// Block 0`
328			`//`
329
330			`RAMB4_S16_S16 ramb4_s16_s16_0(`
331			`.CLKA(clk_a),`
332			`.RSTA(rst_a),`
333			`.ADDRA(addr_a),`
334			`.DIA(di_a[15:0]),`
335			`.ENA(ce_a),`
336			`.WEA(we_a),`
337			`.DOA(do_a[15:0]),`
338
339			`.CLKB(clk_b),`
340			`.RSTB(rst_b),`
341			`.ADDRB(addr_b),`
342			`.DIB(di_b[15:0]),`
343			`.ENB(ce_b),`
344			`.WEB(we_b),`
345			`.DOB(do_b[15:0])`
346			`);`
347
348			`//`
349			`// Block 1`
350			`//`
351
352			`RAMB4_S16_S16 ramb4_s16_s16_1(`
353			`.CLKA(clk_a),`
354			`.RSTA(rst_a),`
355			`.ADDRA(addr_a),`
356			`.DIA(di_a[31:16]),`
357			`.ENA(ce_a),`
358			`.WEA(we_a),`
359			`.DOA(do_a[31:16]),`
360
361			`.CLKB(clk_b),`
362			`.RSTB(rst_b),`
363			`.ADDRB(addr_b),`
364			`.DIB(di_b[31:16]),`
365			`.ENB(ce_b),`
366			`.WEB(we_b),`
367			`.DOB(do_b[31:16])`
368			`);`
369
370			`//`
371			`// Block 2`
372			`//`
373			`// block ram2 wires - non generic width of block rams`
374			`wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;`
375			`wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;`
376
377			`wire [15:0] blk2_do_a ;`
378			`wire [15:0] blk2_do_b ;`
379
380			`assign do_a[39:32] = blk2_do_a[7:0] ;`
381			`assign do_b[39:32] = blk2_do_b[7:0] ;`
382
383			`RAMB4_S16_S16 ramb4_s16_s16_2(`
384			`.CLKA(clk_a),`
385			`.RSTA(rst_a),`
386			`.ADDRA(addr_a),`
387			`.DIA(blk2_di_a),`
388			`.ENA(ce_a),`
389			`.WEA(we_a),`
390			`.DOA(blk2_do_a),`
391
392			`.CLKB(clk_b),`
393			`.RSTB(rst_b),`
394			`.ADDRB(addr_b),`
395			`.DIB(blk2_di_b),`
396			`.ENB(ce_b),`
397			`.WEB(we_b),`
398			`.DOB(blk2_do_b)`
399			`);`
400
401			`endif
402
403			`ifdef PCI_WB_RAM_SELECTED
404			`else
405			`//`
406			`// Generic two-port synchronous RAM model`
407			`//`
408
409			`//`
410			`// Generic RAM's registers and wires`
411			`//`
412			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
413			`reg [dw-1:0] do_reg_a; // RAM data output register`
414			`reg [dw-1:0] do_reg_b; // RAM data output register`
415
416			`//`
417			`// Data output drivers`
418			`//`
419			`assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};`
420			`assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};`
421
422			`//`
423			`// RAM read and write`
424			`//`
425			`always @(posedge clk_a)`
426			`if (ce_a && !we_a)`
427			`do_reg_a <= #1 mem[addr_a];`
428			`else if (ce_a && we_a)`
429			`mem[addr_a] <= #1 di_a;`
430
431			`//`
432			`// RAM read and write`
433			`//`
434			`always @(posedge clk_b)`
435			`if (ce_b && !we_b)`
436			`do_reg_b <= #1 mem[addr_b];`
437			`else if (ce_b && we_b)`
438			`mem[addr_b] <= #1 di_b;`
439			`endif
440
441			`// synopsys translate_off`
442			`initial`
443			`begin`
444			`if (dw !== 40)`
445			`begin`
446			`$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;`
447			`$finish ;`
448			`end`
449			`ifdef XILINX_RAMB4
450			`if (aw !== 8)`
451			`begin`
452			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
453			`$finish ;`
454			`end`
455			`endif
456			`// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models`
457			`ifdef ARTISAN_SDP
458			`if (aw !== 8)`
459			`begin`
460			`$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;`
461			`$finish ;`
462			`end`
463			`endif
464			`end`
465			`// synopsys translate_on`
466
467			`endmodule`