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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] [top.v] - Blame information for rev 77

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1 2 mihad
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "top.v"                                           ////
4
////                                                              ////
5
////  This file is part of the "PCI bridge" project               ////
6
////  http://www.opencores.org/cores/pci/                         ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Miha Dolenc (mihad@opencores.org)                     ////
10
////                                                              ////
11
////  All additional information is avaliable in the README       ////
12
////  file.                                                       ////
13
////                                                              ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 77 mihad
// Revision 1.8  2002/10/18 03:36:37  tadejm
46
// Changed wrong signal name scanb_sen into scanb_en.
47
//
48 68 tadejm
// Revision 1.7  2002/10/17 22:49:22  tadejm
49
// Changed BIST signals for RAMs.
50
//
51 67 tadejm
// Revision 1.6  2002/10/11 10:09:01  mihad
52
// Added additional testcase and changed rst name in BIST to trst
53
//
54 63 mihad
// Revision 1.5  2002/10/08 17:17:06  mihad
55
// Added BIST signals for RAMs.
56
//
57 62 mihad
// Revision 1.4  2002/03/21 07:36:04  mihad
58
// Files updated with missing includes, resolved some race conditions in test bench
59
//
60 35 mihad
// Revision 1.3  2002/02/01 15:25:13  mihad
61
// Repaired a few bugs, updated specification, added test bench files and design document
62
//
63 21 mihad
// Revision 1.2  2001/10/05 08:14:30  mihad
64
// Updated all files with inclusion of timescale file for simulation purposes.
65
//
66 6 mihad
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
67
// New project directory structure
68 2 mihad
//
69 6 mihad
//
70 2 mihad
 
71
// This top module is primarly used for testing plain PCI bridge core without any other cores attached.
72
// Other cores can be included in this top module and appropriate changes incorporated for overall design
73 21 mihad
 
74
// synopsys translate_off
75 6 mihad
`include "timescale.v"
76 21 mihad
// synopsys translate_on
77 35 mihad
`include "pci_constants.v"
78 2 mihad
 
79
module TOP
80
(
81
    CLK,
82 21 mihad
    AD,
83
    CBE,
84
    RST,
85 2 mihad
    INTA,
86
    REQ,
87
    GNT,
88
    FRAME,
89
    IRDY,
90
    IDSEL,
91
    DEVSEL,
92
    TRDY,
93
    STOP,
94
    PAR,
95
    PERR,
96
    SERR,
97 21 mihad
 
98 2 mihad
    CLK_I,
99
    RST_I,
100
    RST_O,
101
    INT_I,
102
    INT_O,
103
 
104
    // WISHBONE slave interface
105
    ADR_I,
106
    SDAT_I,
107
    SDAT_O,
108
    SEL_I,
109
    CYC_I,
110
    STB_I,
111
    WE_I,
112
    CAB_I,
113
    ACK_O,
114
    RTY_O,
115
    ERR_O,
116
 
117
    // WISHBONE master interface
118
    ADR_O,
119
    MDAT_I,
120
    MDAT_O,
121
    SEL_O,
122
    CYC_O,
123
    STB_O,
124
    WE_O,
125
    CAB_O,
126
    ACK_I,
127
    RTY_I,
128 21 mihad
    ERR_I
129 62 mihad
 
130
`ifdef PCI_BIST
131
    ,
132
    // debug chain signals
133 67 tadejm
    scanb_rst,      // bist scan reset
134
    scanb_clk,      // bist scan clock
135
    scanb_si,       // bist scan serial in
136
    scanb_so,       // bist scan serial out
137 68 tadejm
    scanb_en        // bist scan shift enable
138 62 mihad
`endif
139 2 mihad
);
140
 
141
input           CLK ;
142
inout   [31:0]  AD ;
143
inout   [3:0]   CBE ;
144
inout           RST ;
145
inout           INTA ;
146
output          REQ ;
147
input           GNT ;
148
inout           FRAME ;
149
inout           IRDY ;
150
input           IDSEL ;
151
inout           DEVSEL ;
152
inout           TRDY ;
153
inout           STOP ;
154
inout           PAR ;
155
inout           PERR ;
156
output          SERR ;
157
 
158
// WISHBONE system signals
159
input   CLK_I ;
160
input   RST_I ;
161
output  RST_O ;
162
input   INT_I ;
163
output  INT_O ;
164
 
165
// WISHBONE slave interface
166
input   [31:0]  ADR_I ;
167
input   [31:0]  SDAT_I ;
168
output  [31:0]  SDAT_O ;
169
input   [3:0]   SEL_I ;
170
input           CYC_I ;
171
input           STB_I ;
172
input           WE_I  ;
173
input           CAB_I ;
174
output          ACK_O ;
175
output          RTY_O ;
176
output          ERR_O ;
177
 
178
// WISHBONE master interface
179
output  [31:0]  ADR_O ;
180
input   [31:0]  MDAT_I ;
181
output  [31:0]  MDAT_O ;
182
output  [3:0]   SEL_O ;
183
output          CYC_O ;
184
output          STB_O ;
185
output          WE_O  ;
186
output          CAB_O ;
187
input           ACK_I ;
188
input           RTY_I ;
189
input           ERR_I ;
190
 
191 62 mihad
`ifdef PCI_BIST
192
/*-----------------------------------------------------
193
BIST debug chain port signals
194
-----------------------------------------------------*/
195 67 tadejm
input   scanb_rst;      // bist scan reset
196
input   scanb_clk;      // bist scan clock
197
input   scanb_si;       // bist scan serial in
198
output  scanb_so;       // bist scan serial out
199 68 tadejm
input   scanb_en;       // bist scan shift enable
200 62 mihad
`endif
201
 
202 2 mihad
wire    [31:0]  AD_out ;
203
wire    [31:0]  AD_en ;
204
 
205
 
206
wire    [31:0]  AD_in = AD ;
207
 
208
wire    [3:0]   CBE_in = CBE ;
209
wire    [3:0]   CBE_out ;
210
wire    [3:0]   CBE_en ;
211
 
212
 
213
 
214
wire            RST_in = RST ;
215
wire            RST_out ;
216
wire            RST_en ;
217
 
218
wire            INTA_in = INTA ;
219
wire            INTA_en ;
220
wire            INTA_out ;
221
 
222
wire            REQ_en ;
223
wire            REQ_out ;
224
 
225
wire            FRAME_in = FRAME ;
226
wire            FRAME_out ;
227
wire            FRAME_en ;
228
 
229
wire            IRDY_in = IRDY ;
230
wire            IRDY_out ;
231
wire            IRDY_en ;
232
 
233
wire            DEVSEL_in = DEVSEL ;
234
wire            DEVSEL_out ;
235
wire            DEVSEL_en ;
236
 
237
wire            TRDY_in = TRDY ;
238
wire            TRDY_out ;
239
wire            TRDY_en ;
240
 
241
wire            STOP_in = STOP ;
242
wire            STOP_out ;
243
wire            STOP_en ;
244
 
245
wire            PAR_in = PAR ;
246
wire            PAR_out ;
247
wire            PAR_en ;
248
 
249
wire            PERR_in = PERR ;
250
wire            PERR_out ;
251
wire            PERR_en ;
252
 
253
wire            SERR_out ;
254
wire            SERR_en ;
255
 
256 77 mihad
pci_bridge32 bridge
257 2 mihad
(
258
    // WISHBONE system signals
259 77 mihad
    .wb_clk_i(CLK_I),
260
    .wb_rst_i(RST_I),
261
    .wb_rst_o(RST_O),
262
    .wb_int_i(INT_I),
263
    .wb_int_o(INT_O),
264 21 mihad
 
265 2 mihad
    // WISHBONE slave interface
266 77 mihad
    .wbs_adr_i(ADR_I),
267
    .wbs_dat_i(SDAT_I),
268
    .wbs_dat_o(SDAT_O),
269
    .wbs_sel_i(SEL_I),
270
    .wbs_cyc_i(CYC_I),
271
    .wbs_stb_i(STB_I),
272
    .wbs_we_i (WE_I),
273
    .wbs_cab_i(CAB_I),
274
    .wbs_ack_o(ACK_O),
275
    .wbs_rty_o(RTY_O),
276
    .wbs_err_o(ERR_O),
277 21 mihad
 
278 2 mihad
    // WISHBONE master interface
279 77 mihad
    .wbm_adr_o(ADR_O),
280
    .wbm_dat_i(MDAT_I),
281
    .wbm_dat_o(MDAT_O),
282
    .wbm_sel_o(SEL_O),
283
    .wbm_cyc_o(CYC_O),
284
    .wbm_stb_o(STB_O),
285
    .wbm_we_o (WE_O),
286
    .wbm_cab_o(CAB_O),
287
    .wbm_ack_i(ACK_I),
288
    .wbm_rty_i(RTY_I),
289
    .wbm_err_i(ERR_I),
290 21 mihad
 
291 2 mihad
    // pci interface - system pins
292 77 mihad
    .pci_clk_i    (CLK),
293
    .pci_rst_i    ( RST_in ),
294
    .pci_rst_o    ( RST_out ),
295
    .pci_inta_i   ( INTA_in ),
296
    .pci_inta_o   ( INTA_out),
297
    .pci_rst_oe_o ( RST_en),
298
    .pci_inta_oe_o(INTA_en),
299 21 mihad
 
300 2 mihad
    // arbitration pins
301 77 mihad
    .pci_req_o   ( REQ_out ),
302
    .pci_req_oe_o( REQ_en ),
303 21 mihad
 
304 77 mihad
    .pci_gnt_i   ( GNT ),
305 21 mihad
 
306 2 mihad
    // protocol pins
307 77 mihad
    .pci_frame_i   ( FRAME_in),
308
    .pci_frame_o   ( FRAME_out ),
309
 
310
    .pci_frame_oe_o( FRAME_en ),
311
    .pci_irdy_oe_o ( IRDY_en ),
312
    .pci_devsel_oe_o( DEVSEL_en ),
313
    .pci_trdy_oe_o ( TRDY_en ),
314
    .pci_stop_oe_o ( STOP_en ),
315
    .pci_ad_oe_o   (AD_en),
316
    .pci_cbe_oe_o  ( CBE_en) ,
317
 
318
    .pci_irdy_i    ( IRDY_in ),
319
    .pci_irdy_o    ( IRDY_out ),
320
 
321
    .pci_idsel_i   ( IDSEL ),
322
 
323
    .pci_devsel_i  ( DEVSEL_in ),
324
    .pci_devsel_o  ( DEVSEL_out ),
325
 
326
    .pci_trdy_i    ( TRDY_in ),
327
    .pci_trdy_o    ( TRDY_out ),
328
 
329
    .pci_stop_i    ( STOP_in ),
330
    .pci_stop_o    ( STOP_out ),
331 2 mihad
 
332 21 mihad
    // data transfer pins
333 77 mihad
    .pci_ad_i(AD_in),
334
    .pci_ad_o(AD_out),
335
 
336
    .pci_cbe_i( CBE_in ),
337
    .pci_cbe_o( CBE_out ),
338 21 mihad
 
339 2 mihad
    // parity generation and checking pins
340 77 mihad
    .pci_par_i    ( PAR_in ),
341
    .pci_par_o    ( PAR_out ),
342
    .pci_par_oe_o ( PAR_en ),
343
 
344
    .pci_perr_i   ( PERR_in ),
345
    .pci_perr_o   ( PERR_out ),
346
    .pci_perr_oe_o( PERR_en ),
347 21 mihad
 
348 2 mihad
    // system error pin
349 77 mihad
    .pci_serr_o   ( SERR_out ),
350
    .pci_serr_oe_o( SERR_en )
351 62 mihad
 
352
`ifdef PCI_BIST
353
    ,
354 67 tadejm
    .scanb_rst      (scanb_rst),
355
    .scanb_clk      (scanb_clk),
356
    .scanb_si       (scanb_si),
357
    .scanb_so       (scanb_so),
358 68 tadejm
    .scanb_en       (scanb_en)
359 62 mihad
`endif
360 2 mihad
);
361 35 mihad
 
362
 
363 21 mihad
// PCI IO buffers instantiation
364
`ifdef ACTIVE_LOW_OE
365 35 mihad
 
366 2 mihad
bufif0 AD_buf0   ( AD[0],  AD_out[0], AD_en[0]) ;
367
bufif0 AD_buf1   ( AD[1],  AD_out[1], AD_en[1]) ;
368
bufif0 AD_buf2   ( AD[2],  AD_out[2], AD_en[2]) ;
369
bufif0 AD_buf3   ( AD[3],  AD_out[3], AD_en[3]) ;
370
bufif0 AD_buf4   ( AD[4],  AD_out[4], AD_en[4]) ;
371
bufif0 AD_buf5   ( AD[5],  AD_out[5], AD_en[5]) ;
372
bufif0 AD_buf6   ( AD[6],  AD_out[6], AD_en[6]) ;
373
bufif0 AD_buf7   ( AD[7],  AD_out[7], AD_en[7]) ;
374
bufif0 AD_buf8   ( AD[8],  AD_out[8], AD_en[8]) ;
375
bufif0 AD_buf9   ( AD[9],  AD_out[9], AD_en[9]) ;
376
bufif0 AD_buf10  ( AD[10], AD_out[10],AD_en[10] ) ;
377
bufif0 AD_buf11  ( AD[11], AD_out[11],AD_en[11] ) ;
378
bufif0 AD_buf12  ( AD[12], AD_out[12],AD_en[12] ) ;
379
bufif0 AD_buf13  ( AD[13], AD_out[13],AD_en[13] ) ;
380
bufif0 AD_buf14  ( AD[14], AD_out[14],AD_en[14] ) ;
381
bufif0 AD_buf15  ( AD[15], AD_out[15],AD_en[15] ) ;
382
bufif0 AD_buf16  ( AD[16], AD_out[16],AD_en[16] ) ;
383
bufif0 AD_buf17  ( AD[17], AD_out[17],AD_en[17] ) ;
384
bufif0 AD_buf18  ( AD[18], AD_out[18],AD_en[18] ) ;
385
bufif0 AD_buf19  ( AD[19], AD_out[19],AD_en[19] ) ;
386
bufif0 AD_buf20  ( AD[20], AD_out[20],AD_en[20] ) ;
387
bufif0 AD_buf21  ( AD[21], AD_out[21],AD_en[21] ) ;
388
bufif0 AD_buf22  ( AD[22], AD_out[22],AD_en[22] ) ;
389
bufif0 AD_buf23  ( AD[23], AD_out[23],AD_en[23] ) ;
390
bufif0 AD_buf24  ( AD[24], AD_out[24],AD_en[24] ) ;
391
bufif0 AD_buf25  ( AD[25], AD_out[25],AD_en[25] ) ;
392
bufif0 AD_buf26  ( AD[26], AD_out[26],AD_en[26] ) ;
393
bufif0 AD_buf27  ( AD[27], AD_out[27],AD_en[27] ) ;
394
bufif0 AD_buf28  ( AD[28], AD_out[28],AD_en[28] ) ;
395
bufif0 AD_buf29  ( AD[29], AD_out[29],AD_en[29] ) ;
396
bufif0 AD_buf30  ( AD[30], AD_out[30],AD_en[30] ) ;
397
bufif0 AD_buf31  ( AD[31], AD_out[31],AD_en[31] ) ;
398
 
399
bufif0 CBE_buf0 ( CBE[0], CBE_out[0], CBE_en[0] ) ;
400
bufif0 CBE_buf1 ( CBE[1], CBE_out[1], CBE_en[1] ) ;
401
bufif0 CBE_buf2 ( CBE[2], CBE_out[2], CBE_en[2] ) ;
402
bufif0 CBE_buf3 ( CBE[3], CBE_out[3], CBE_en[3] ) ;
403 21 mihad
 
404 2 mihad
bufif0 FRAME_buf    ( FRAME, FRAME_out, FRAME_en ) ;
405
bufif0 IRDY_buf     ( IRDY, IRDY_out, IRDY_en ) ;
406
bufif0 DEVSEL_buf   ( DEVSEL, DEVSEL_out, DEVSEL_en ) ;
407
bufif0 TRDY_buf     ( TRDY, TRDY_out, TRDY_en ) ;
408
bufif0 STOP_buf     ( STOP, STOP_out, STOP_en ) ;
409 21 mihad
 
410 2 mihad
bufif0 RST_buf      ( RST, RST_out, RST_en ) ;
411
bufif0 INTA_buf     ( INTA, INTA_out, INTA_en) ;
412
bufif0 REQ_buf      ( REQ, REQ_out, REQ_en ) ;
413
bufif0 PAR_buf      ( PAR, PAR_out, PAR_en ) ;
414
bufif0 PERR_buf     ( PERR, PERR_out, PERR_en ) ;
415
bufif0 SERR_buf     ( SERR, SERR_out, SERR_en ) ;
416
 
417 21 mihad
`else
418 35 mihad
 `ifdef ACTIVE_HIGH_OE
419
 
420 21 mihad
bufif1 AD_buf0   ( AD[0],  AD_out[0], AD_en[0]) ;
421
bufif1 AD_buf1   ( AD[1],  AD_out[1], AD_en[1]) ;
422
bufif1 AD_buf2   ( AD[2],  AD_out[2], AD_en[2]) ;
423
bufif1 AD_buf3   ( AD[3],  AD_out[3], AD_en[3]) ;
424
bufif1 AD_buf4   ( AD[4],  AD_out[4], AD_en[4]) ;
425
bufif1 AD_buf5   ( AD[5],  AD_out[5], AD_en[5]) ;
426
bufif1 AD_buf6   ( AD[6],  AD_out[6], AD_en[6]) ;
427
bufif1 AD_buf7   ( AD[7],  AD_out[7], AD_en[7]) ;
428
bufif1 AD_buf8   ( AD[8],  AD_out[8], AD_en[8]) ;
429
bufif1 AD_buf9   ( AD[9],  AD_out[9], AD_en[9]) ;
430
bufif1 AD_buf10  ( AD[10], AD_out[10],AD_en[10] ) ;
431
bufif1 AD_buf11  ( AD[11], AD_out[11],AD_en[11] ) ;
432
bufif1 AD_buf12  ( AD[12], AD_out[12],AD_en[12] ) ;
433
bufif1 AD_buf13  ( AD[13], AD_out[13],AD_en[13] ) ;
434
bufif1 AD_buf14  ( AD[14], AD_out[14],AD_en[14] ) ;
435
bufif1 AD_buf15  ( AD[15], AD_out[15],AD_en[15] ) ;
436
bufif1 AD_buf16  ( AD[16], AD_out[16],AD_en[16] ) ;
437
bufif1 AD_buf17  ( AD[17], AD_out[17],AD_en[17] ) ;
438
bufif1 AD_buf18  ( AD[18], AD_out[18],AD_en[18] ) ;
439
bufif1 AD_buf19  ( AD[19], AD_out[19],AD_en[19] ) ;
440
bufif1 AD_buf20  ( AD[20], AD_out[20],AD_en[20] ) ;
441
bufif1 AD_buf21  ( AD[21], AD_out[21],AD_en[21] ) ;
442
bufif1 AD_buf22  ( AD[22], AD_out[22],AD_en[22] ) ;
443
bufif1 AD_buf23  ( AD[23], AD_out[23],AD_en[23] ) ;
444
bufif1 AD_buf24  ( AD[24], AD_out[24],AD_en[24] ) ;
445
bufif1 AD_buf25  ( AD[25], AD_out[25],AD_en[25] ) ;
446
bufif1 AD_buf26  ( AD[26], AD_out[26],AD_en[26] ) ;
447
bufif1 AD_buf27  ( AD[27], AD_out[27],AD_en[27] ) ;
448
bufif1 AD_buf28  ( AD[28], AD_out[28],AD_en[28] ) ;
449
bufif1 AD_buf29  ( AD[29], AD_out[29],AD_en[29] ) ;
450
bufif1 AD_buf30  ( AD[30], AD_out[30],AD_en[30] ) ;
451
bufif1 AD_buf31  ( AD[31], AD_out[31],AD_en[31] ) ;
452
 
453
bufif1 CBE_buf0 ( CBE[0], CBE_out[0], CBE_en[0] ) ;
454
bufif1 CBE_buf1 ( CBE[1], CBE_out[1], CBE_en[1] ) ;
455
bufif1 CBE_buf2 ( CBE[2], CBE_out[2], CBE_en[2] ) ;
456
bufif1 CBE_buf3 ( CBE[3], CBE_out[3], CBE_en[3] ) ;
457
 
458
bufif1 FRAME_buf    ( FRAME, FRAME_out, FRAME_en ) ;
459
bufif1 IRDY_buf     ( IRDY, IRDY_out, IRDY_en ) ;
460
bufif1 DEVSEL_buf   ( DEVSEL, DEVSEL_out, DEVSEL_en ) ;
461
bufif1 TRDY_buf     ( TRDY, TRDY_out, TRDY_en ) ;
462
bufif1 STOP_buf     ( STOP, STOP_out, STOP_en ) ;
463
 
464
bufif1 RST_buf      ( RST, RST_out, RST_en ) ;
465
bufif1 INTA_buf     ( INTA, INTA_out, INTA_en) ;
466
bufif1 REQ_buf      ( REQ, REQ_out, REQ_en ) ;
467
bufif1 PAR_buf      ( PAR, PAR_out, PAR_en ) ;
468
bufif1 PERR_buf     ( PERR, PERR_out, PERR_en ) ;
469
bufif1 SERR_buf     ( SERR, SERR_out, SERR_en ) ;
470
`endif
471
`endif
472
 
473
 
474
endmodule

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