| 1 |
17 |
mihad |
-cdslib ../bin/cds.lib
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| 2 |
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-hdlvar ../bin/hdl.var
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| 3 |
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-logfile ../log/ncvlog.log
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| 4 |
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-update
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| 5 |
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-messages
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| 6 |
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-INCDIR ../../../bench/verilog
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| 7 |
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-INCDIR ../../../rtl/verilog
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| 8 |
106 |
mihad |
-DEFINE REGRESSION
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| 9 |
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-DEFINE REGR_FIFO_SMALL_GENERIC
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| 10 |
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-DEFINE GUEST
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| 11 |
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-DEFINE WB_DECODE_FAST
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| 12 |
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-DEFINE PCI_DECODE_MAX
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| 13 |
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-DEFINE WB_DECODE_MED
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| 14 |
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-DEFINE PCI66
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| 15 |
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-DEFINE WB_CLK66
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| 16 |
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-DEFINE ACTIVE_HIGH_OE
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| 17 |
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-DEFINE WB_CNF_BASE_ZERO
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| 18 |
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-DEFINE NO_CNF_IMAGE
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| 19 |
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-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2
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| 20 |
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-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS
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| 21 |
17 |
mihad |
../../../rtl/verilog/pci_parity_check.v
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| 22 |
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|
../../../rtl/verilog/pci_target_unit.v
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| 23 |
92 |
mihad |
../../../rtl/verilog/pci_wb_addr_mux.v
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| 24 |
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../../../rtl/verilog/pci_cbe_en_crit.v
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| 25 |
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../../../rtl/verilog/pci_pcir_fifo_control.v
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| 26 |
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../../../rtl/verilog/pci_out_reg.v
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| 27 |
|
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../../../rtl/verilog/pci_pci_tpram.v
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| 28 |
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../../../rtl/verilog/pci_wb_master.v
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| 29 |
|
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../../../rtl/verilog/pci_conf_cyc_addr_dec.v
|
| 30 |
|
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../../../rtl/verilog/pci_frame_crit.v
|
| 31 |
17 |
mihad |
../../../rtl/verilog/pci_target32_clk_en.v
|
| 32 |
92 |
mihad |
../../../rtl/verilog/pci_pciw_fifo_control.v
|
| 33 |
|
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../../../rtl/verilog/pci_wb_slave.v
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| 34 |
|
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../../../rtl/verilog/pci_conf_space.v
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| 35 |
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../../../rtl/verilog/pci_frame_en_crit.v
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| 36 |
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../../../rtl/verilog/pci_par_crit.v
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| 37 |
|
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../../../rtl/verilog/pci_pciw_pcir_fifos.v
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| 38 |
|
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../../../rtl/verilog/pci_wb_slave_unit.v
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| 39 |
|
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../../../rtl/verilog/pci_frame_load_crit.v
|
| 40 |
17 |
mihad |
../../../rtl/verilog/pci_bridge32.v
|
| 41 |
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|
../../../rtl/verilog/pci_target32_devs_crit.v
|
| 42 |
92 |
mihad |
../../../rtl/verilog/pci_perr_crit.v
|
| 43 |
|
|
../../../rtl/verilog/pci_wbr_fifo_control.v
|
| 44 |
|
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../../../rtl/verilog/pci_cur_out_reg.v
|
| 45 |
|
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../../../rtl/verilog/pci_pci_decoder.v
|
| 46 |
17 |
mihad |
../../../rtl/verilog/pci_target32_interface.v
|
| 47 |
92 |
mihad |
../../../rtl/verilog/pci_perr_en_crit.v
|
| 48 |
|
|
../../../rtl/verilog/pci_wbw_fifo_control.v
|
| 49 |
|
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../../../rtl/verilog/pci_wb_decoder.v
|
| 50 |
17 |
mihad |
../../../rtl/verilog/pci_in_reg.v
|
| 51 |
92 |
mihad |
../../../rtl/verilog/pci_serr_crit.v
|
| 52 |
|
|
../../../rtl/verilog/pci_wbw_wbr_fifos.v
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| 53 |
|
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../../../rtl/verilog/pci_delayed_sync.v
|
| 54 |
|
|
../../../rtl/verilog/pci_irdy_out_crit.v
|
| 55 |
17 |
mihad |
../../../rtl/verilog/pci_io_mux.v
|
| 56 |
|
|
../../../rtl/verilog/pci_io_mux_ad_en_crit.v
|
| 57 |
|
|
../../../rtl/verilog/pci_io_mux_ad_load_crit.v
|
| 58 |
|
|
../../../rtl/verilog/pci_target32_sm.v
|
| 59 |
92 |
mihad |
../../../rtl/verilog/pci_serr_en_crit.v
|
| 60 |
|
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../../../rtl/verilog/pci_delayed_write_reg.v
|
| 61 |
|
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../../../rtl/verilog/pci_mas_ad_en_crit.v
|
| 62 |
|
|
../../../rtl/verilog/pci_mas_ad_load_crit.v
|
| 63 |
17 |
mihad |
../../../rtl/verilog/pci_master32_sm.v
|
| 64 |
|
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../../../rtl/verilog/pci_target32_stop_crit.v
|
| 65 |
|
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../../../rtl/verilog/synchronizer_flop.v
|
| 66 |
92 |
mihad |
../../../rtl/verilog/pci_async_reset_flop.v
|
| 67 |
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../../../rtl/verilog/pci_mas_ch_state_crit.v
|
| 68 |
17 |
mihad |
../../../rtl/verilog/pci_master32_sm_if.v
|
| 69 |
|
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../../../rtl/verilog/pci_target32_trdy_crit.v
|
| 70 |
|
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../../../rtl/verilog/top.v
|
| 71 |
|
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../../../rtl/verilog/pci_rst_int.v
|
| 72 |
92 |
mihad |
../../../rtl/verilog/pci_sync_module.v
|
| 73 |
|
|
../../../rtl/verilog/pci_wb_tpram.v
|
| 74 |
106 |
mihad |
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v
|
| 75 |
17 |
mihad |
../../../bench/verilog/wb_master32.v
|
| 76 |
|
|
../../../bench/verilog/wb_master_behavioral.v
|
| 77 |
|
|
../../../bench/verilog/system.v
|
| 78 |
|
|
../../../bench/verilog/pci_blue_arbiter.v
|
| 79 |
|
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../../../bench/verilog/pci_bus_monitor.v
|
| 80 |
|
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../../../bench/verilog/pci_behaviorial_device.v
|
| 81 |
|
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../../../bench/verilog/pci_behaviorial_master.v
|
| 82 |
|
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../../../bench/verilog/pci_behaviorial_target.v
|
| 83 |
|
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../../../bench/verilog/wb_slave_behavioral.v
|
| 84 |
|
|
../../../bench/verilog/wb_bus_mon.v
|
| 85 |
|
|
../../../bench/verilog/pci_unsupported_commands_master.v
|
| 86 |
92 |
mihad |
../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
|
| 87 |
26 |
mihad |
../../../../../../lib/xilinx/lib/glbl/glbl.v
|
| 88 |
|
|
../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
|
| 89 |
|
|
../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
|
| 90 |
92 |
mihad |
../../../rtl/verilog/pci_ram_16x40d.v
|
