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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_behavioral_pci2pci_bridge.v] - Blame information for rev 114

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_behavioral_iack_target"                      ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/03/06 09:10:56  mihad
// Added missing include statements
//
// Revision 1.1  2002/02/01 15:07:51  mihad
// *** empty log message ***
//
 
`include "pci_constants.v"
`include "timescale.v"
`include "bus_commands.v"
 
// module is provided just as target for responding to interrupt acknowledge commands, because
// other models don't support this command
module pci_behavioral_pci2pci_bridge
(
    CLK,
    AD,
    CBE,
    RST,
    FRAME,
    IRDY,
    DEVSEL,
    TRDY,
    STOP,
    PAR,
    response,
    data_in,
    data_out,
    devsel_speed,
    wait_states,
    bus_number
);
`include "pci_blue_constants.vh"
 
input CLK ;
 
inout   [31:0]  AD ;
reg     [31:0]  AD_out ;
reg             AD_en ;
 
input   [3:0]   CBE ;
input           RST ;
input           FRAME ;
input           IRDY ;
 
output          DEVSEL ;
reg             DEVSEL ;
 
output          TRDY ;
reg             TRDY ;
 
output          STOP ;
reg             STOP ;
 
inout           PAR ;
reg             PAR_out ;
reg             PAR_en ;
 
// posible responses:
//2'b00 - Normal
//2'b01 - Disconnect With Data
//2'b10 - Retry
//2'b11 - Abort
input  [1:0] response ;
 
input  [31:0] data_out ;
output [31:0] data_in ;
reg    [31:0] data_in ;
input  [1:0]  devsel_speed ;
input  [3:0]  wait_states ;
input  [7:0]  bus_number ;
 
reg frame_prev ;
reg read0_write1 ;
 
reg generate_par ;
reg busy ;
 
assign PAR = PAR_en ? PAR_out : 1'bz ;
assign AD  = AD_en  ? AD_out  : 32'hzzzz_zzzz ;
 
always@(posedge CLK or negedge RST)
begin
    if ( !RST )
    begin
        frame_prev   <= #1 1'b1 ;
        AD_out       <= #1 32'hDEAD_BEAF ;
        AD_en        <= #1 1'b0 ;
        DEVSEL       <= #1 1'bz ;
        TRDY         <= #1 1'bz ;
        STOP         <= #1 1'bz ;
        PAR_out      <= #1 1'b0 ;
        PAR_en       <= #1 1'b0 ;
        busy         = 1'b0 ;
    end
    else
    begin
        frame_prev <= #`FF_DELAY FRAME ;
    end
end
 
always@(posedge CLK)
begin
    if ( RST )
    begin
        if ( (frame_prev === 1) && (FRAME === 0) && (CBE[3:1] === `BC_CONF_RW) && (AD[1:0] === 2'b01) && (AD[23:16] === bus_number) )
        begin
            read0_write1 = CBE[0] ;
            busy = 1'b1 ;
            do_reference ;
        end
        else
        begin
            if (!busy)
            begin
                TRDY   <= #1 1'bz ;
                STOP   <= #1 1'bz ;
                DEVSEL <= #1 1'bz ;
            end
        end
    end
end
 
task do_reference ;
begin
    assert_devsel ;
    insert_waits_drive_ad_on_read ;
    terminate ;
    busy <= #1 1'b0 ;
end
endtask // do reference
 
task assert_devsel ;
    reg [1:0] num_of_cyc;
begin:main
    if (devsel_speed == `Test_Devsel_Fast)
    begin
        num_of_cyc = 0 ;
    end
 
    if (devsel_speed == `Test_Devsel_Medium)
    begin
        num_of_cyc = 1 ;
    end
 
    if (devsel_speed == `Test_Devsel_Slow)
    begin
        num_of_cyc = 2 ;
    end
 
    if (devsel_speed == `Test_Devsel_Subtractive)
    begin
        num_of_cyc = 3 ;
    end
 
    repeat(num_of_cyc)
        @(posedge CLK) ;
 
    DEVSEL <= #1 1'b0 ;
end
endtask // assert_devsel
 
task insert_waits_drive_ad_on_read ;
    reg [3:0] waits_left ;
begin
    if (((devsel_speed == `Test_Devsel_Fast) && (!read0_write1)) || (response == 2'b11))
    begin
        TRDY <= #1 1'b1 ;
        STOP <= #1 1'b1 ;
        @(posedge CLK) ;
        if (wait_states > 0)
            waits_left = wait_states - 1;
    end
    else
    begin
        waits_left = wait_states ;
    end
 
    if (!read0_write1)
        AD_en <= #1 1'b1 ;
 
    while (waits_left > 0)
    begin
        TRDY <= #1 1'b1 ;
        STOP <= #1 1'b1 ;
        @(posedge CLK) ;
        waits_left = waits_left - 1 ;
    end
end
endtask // insert_waits_drive_ad_on_read
 
task terminate ;
begin
 
    if (response)
    begin
        STOP <= #1 1'b0 ;
    end
 
    if (response == 2'b11)
        DEVSEL <= #1 1'b1 ;
 
    if (!response[1])
    begin
        TRDY <= #1 1'b0 ;
        if (!read0_write1)
        begin
            if (!CBE[3])
                AD_out[31:24] <= #1 data_out[31:24] ;
 
            if (!CBE[2])
                AD_out[23:16] <= #1 data_out[23:16] ;
 
            if (!CBE[1])
                AD_out[15:8] <= #1 data_out[15:8] ;
 
            if (!CBE[0])
                AD_out[7:0] <= #1 data_out[7:0] ;
        end
    end
 
    @(posedge CLK) ;
    while (IRDY !== 0)
        @(posedge CLK) ;
 
    if (read0_write1)
    begin
        if (!CBE[3])
            data_in[31:24] = AD[31:24] ;
        else
            data_in[31:24] = 8'hDE ;
 
        if (!CBE[2])
            data_in[23:16] = AD[23:16] ;
        else
            data_in[23:16] = 8'hAD ;
 
        if (!CBE[1])
            data_in[15:8] = AD[15:8] ;
        else
            data_in[15:8] = 8'hBE ;
 
        if (!CBE[0])
            data_in[7:0] = AD[7:0] ;
        else
            data_in[7:0] = 8'hAF ;
    end
 
    TRDY <= #1 1'b1 ;
 
    while (FRAME !== 1)
    begin
        STOP <= #1 1'b0 ;
        @(posedge CLK) ;
    end
 
    DEVSEL <= #1 1'b1 ;
    STOP   <= #1 1'b1 ;
    AD_en  <= #1 1'b0 ;
    AD_out <= #1 32'hDEAD_BEAF ;
end
endtask // terminate ;
 
always@(posedge CLK)
begin
    if (RST)
    begin
        PAR_en  <= #1 AD_en ;
        PAR_out <= #1 (^AD) ^ (^CBE) ;
    end
end
 
endmodule

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_behavioral_pci2pci_bridge.v] - Blame information for rev 114

Line No.	Rev	Author	Line
1	44	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_behavioral_iack_target" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`// Revision 1.2 2002/03/06 09:10:56 mihad`
43			`// Added missing include statements`
44			`//`
45			`// Revision 1.1 2002/02/01 15:07:51 mihad`
46			`// * empty log message *`
47			`//`
48
49			`include "pci_constants.v"
50			`include "timescale.v"
51			`include "bus_commands.v"
52
53			`// module is provided just as target for responding to interrupt acknowledge commands, because`
54			`// other models don't support this command`
55			`module pci_behavioral_pci2pci_bridge`
56			`(`
57			`CLK,`
58			`AD,`
59			`CBE,`
60			`RST,`
61			`FRAME,`
62			`IRDY,`
63			`DEVSEL,`
64			`TRDY,`
65			`STOP,`
66			`PAR,`
67			`response,`
68			`data_in,`
69			`data_out,`
70			`devsel_speed,`
71			`wait_states,`
72			`bus_number`
73			`);`
74			`include "pci_blue_constants.vh"
75
76			`input CLK ;`
77
78			`inout [31:0] AD ;`
79			`reg [31:0] AD_out ;`
80			`reg AD_en ;`
81
82			`input [3:0] CBE ;`
83			`input RST ;`
84			`input FRAME ;`
85			`input IRDY ;`
86
87			`output DEVSEL ;`
88			`reg DEVSEL ;`
89
90			`output TRDY ;`
91			`reg TRDY ;`
92
93			`output STOP ;`
94			`reg STOP ;`
95
96			`inout PAR ;`
97			`reg PAR_out ;`
98			`reg PAR_en ;`
99
100			`// posible responses:`
101			`//2'b00 - Normal`
102			`//2'b01 - Disconnect With Data`
103			`//2'b10 - Retry`
104			`//2'b11 - Abort`
105			`input [1:0] response ;`
106
107			`input [31:0] data_out ;`
108			`output [31:0] data_in ;`
109			`reg [31:0] data_in ;`
110			`input [1:0] devsel_speed ;`
111			`input [3:0] wait_states ;`
112			`input [7:0] bus_number ;`
113
114			`reg frame_prev ;`
115			`reg read0_write1 ;`
116
117			`reg generate_par ;`
118			`reg busy ;`
119
120			`assign PAR = PAR_en ? PAR_out : 1'bz ;`
121			`assign AD = AD_en ? AD_out : 32'hzzzz_zzzz ;`
122
123			`always@(posedge CLK or negedge RST)`
124			`begin`
125			`if ( !RST )`
126			`begin`
127			`frame_prev <= #1 1'b1 ;`
128			`AD_out <= #1 32'hDEAD_BEAF ;`
129			`AD_en <= #1 1'b0 ;`
130			`DEVSEL <= #1 1'bz ;`
131			`TRDY <= #1 1'bz ;`
132			`STOP <= #1 1'bz ;`
133			`PAR_out <= #1 1'b0 ;`
134			`PAR_en <= #1 1'b0 ;`
135			`busy = 1'b0 ;`
136			`end`
137			`else`
138			`begin`
139			frame_prev <= #`FF_DELAY FRAME ;
140			`end`
141			`end`
142
143			`always@(posedge CLK)`
144			`begin`
145			`if ( RST )`
146			`begin`
147			if ( (frame_prev === 1) && (FRAME === 0) && (CBE[3:1] === `BC_CONF_RW) && (AD[1:0] === 2'b01) && (AD[23:16] === bus_number) )
148			`begin`
149			`read0_write1 = CBE[0] ;`
150			`busy = 1'b1 ;`
151			`do_reference ;`
152			`end`
153			`else`
154			`begin`
155			`if (!busy)`
156			`begin`
157			`TRDY <= #1 1'bz ;`
158			`STOP <= #1 1'bz ;`
159			`DEVSEL <= #1 1'bz ;`
160			`end`
161			`end`
162			`end`
163			`end`
164
165			`task do_reference ;`
166			`begin`
167			`assert_devsel ;`
168			`insert_waits_drive_ad_on_read ;`
169			`terminate ;`
170			`busy <= #1 1'b0 ;`
171			`end`
172			`endtask // do reference`
173
174			`task assert_devsel ;`
175			`reg [1:0] num_of_cyc;`
176			`begin:main`
177			if (devsel_speed == `Test_Devsel_Fast)
178			`begin`
179			`num_of_cyc = 0 ;`
180			`end`
181
182			if (devsel_speed == `Test_Devsel_Medium)
183			`begin`
184			`num_of_cyc = 1 ;`
185			`end`
186
187			if (devsel_speed == `Test_Devsel_Slow)
188			`begin`
189			`num_of_cyc = 2 ;`
190			`end`
191
192			if (devsel_speed == `Test_Devsel_Subtractive)
193			`begin`
194			`num_of_cyc = 3 ;`
195			`end`
196
197			`repeat(num_of_cyc)`
198			`@(posedge CLK) ;`
199
200			`DEVSEL <= #1 1'b0 ;`
201			`end`
202			`endtask // assert_devsel`
203
204			`task insert_waits_drive_ad_on_read ;`
205			`reg [3:0] waits_left ;`
206			`begin`
207			if (((devsel_speed == `Test_Devsel_Fast) && (!read0_write1)) \|\| (response == 2'b11))
208			`begin`
209			`TRDY <= #1 1'b1 ;`
210			`STOP <= #1 1'b1 ;`
211			`@(posedge CLK) ;`
212			`if (wait_states > 0)`
213			`waits_left = wait_states - 1;`
214			`end`
215			`else`
216			`begin`
217			`waits_left = wait_states ;`
218			`end`
219
220			`if (!read0_write1)`
221			`AD_en <= #1 1'b1 ;`
222
223			`while (waits_left > 0)`
224			`begin`
225			`TRDY <= #1 1'b1 ;`
226			`STOP <= #1 1'b1 ;`
227			`@(posedge CLK) ;`
228			`waits_left = waits_left - 1 ;`
229			`end`
230			`end`
231			`endtask // insert_waits_drive_ad_on_read`
232
233			`task terminate ;`
234			`begin`
235
236			`if (response)`
237			`begin`
238			`STOP <= #1 1'b0 ;`
239			`end`
240
241			`if (response == 2'b11)`
242			`DEVSEL <= #1 1'b1 ;`
243
244			`if (!response[1])`
245			`begin`
246			`TRDY <= #1 1'b0 ;`
247			`if (!read0_write1)`
248			`begin`
249			`if (!CBE[3])`
250			`AD_out[31:24] <= #1 data_out[31:24] ;`
251
252			`if (!CBE[2])`
253			`AD_out[23:16] <= #1 data_out[23:16] ;`
254
255			`if (!CBE[1])`
256			`AD_out[15:8] <= #1 data_out[15:8] ;`
257
258			`if (!CBE[0])`
259			`AD_out[7:0] <= #1 data_out[7:0] ;`
260			`end`
261			`end`
262
263			`@(posedge CLK) ;`
264			`while (IRDY !== 0)`
265			`@(posedge CLK) ;`
266
267			`if (read0_write1)`
268			`begin`
269			`if (!CBE[3])`
270			`data_in[31:24] = AD[31:24] ;`
271			`else`
272			`data_in[31:24] = 8'hDE ;`
273
274			`if (!CBE[2])`
275			`data_in[23:16] = AD[23:16] ;`
276			`else`
277			`data_in[23:16] = 8'hAD ;`
278
279			`if (!CBE[1])`
280			`data_in[15:8] = AD[15:8] ;`
281			`else`
282			`data_in[15:8] = 8'hBE ;`
283
284			`if (!CBE[0])`
285			`data_in[7:0] = AD[7:0] ;`
286			`else`
287			`data_in[7:0] = 8'hAF ;`
288			`end`
289
290			`TRDY <= #1 1'b1 ;`
291
292			`while (FRAME !== 1)`
293			`begin`
294			`STOP <= #1 1'b0 ;`
295			`@(posedge CLK) ;`
296			`end`
297
298			`DEVSEL <= #1 1'b1 ;`
299			`STOP <= #1 1'b1 ;`
300			`AD_en <= #1 1'b0 ;`
301			`AD_out <= #1 32'hDEAD_BEAF ;`
302			`end`
303			`endtask // terminate ;`
304
305			`always@(posedge CLK)`
306			`begin`
307			`if (RST)`
308			`begin`
309			`PAR_en <= #1 AD_en ;`
310			`PAR_out <= #1 (^AD) ^ (^CBE) ;`
311			`end`
312			`end`
313
314			`endmodule`