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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_bench_common_tasks.v] - Blame information for rev 114

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_bench_common_tasks.v"                        ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
task pci_configure_pci_target_image ;
    input        use_bus ;   // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
    input [2:0]  image_num ; // image number
    input [31:0] ba ;        // base address
    input [31:0] am ;        // address mask
    input [31:0] ta ;        // translation address
    input        io_nmem ;   // io/mem mapping select
    input        pref_en ;   // prefetch enable
    input        at_en ;     // address translation enable
    output       ok ;        // finished succesfully
 
    reg          in_use ;
    reg   [11:0] ctrl_offset ;
    reg   [11:0] ba_offset ;
    reg   [11:0] am_offset ;
    reg   [11:0] ta_offset ;
begin:main
    if (in_use === 1'b1)
    begin
        $display("Time %t", $time) ;
        $display("pci_configure_pci_target_image task re-entered") ;
        ok = 0 ;
        disable main ;
    end
 
    in_use = 1'b1 ;
    if (use_bus !== 1'b0)
    begin
        if (image_num === 0)
        begin
            ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `P_BA0_ADDR, 2'b00} ;
            am_offset   = {4'h1, `P_AM0_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `P_TA0_ADDR, 2'b00} ;
        end
        else if (image_num === 1)
        begin
            ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `P_BA1_ADDR, 2'b00} ;
            am_offset   = {4'h1, `P_AM1_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `P_TA1_ADDR, 2'b00} ;
        end
        else if (image_num === 2)
        begin
            ctrl_offset = {4'h1, `P_IMG_CTRL2_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `P_BA2_ADDR, 2'b00} ;
            am_offset   = {4'h1, `P_AM2_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `P_TA2_ADDR, 2'b00} ;
        end
        else if (image_num === 3)
        begin
            ctrl_offset = {4'h1, `P_IMG_CTRL3_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `P_BA3_ADDR, 2'b00} ;
            am_offset   = {4'h1, `P_AM3_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `P_TA3_ADDR, 2'b00} ;
        end
        else if (image_num === 4)
        begin
            ctrl_offset = {4'h1, `P_IMG_CTRL4_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `P_BA4_ADDR, 2'b00} ;
            am_offset   = {4'h1, `P_AM4_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `P_TA4_ADDR, 2'b00} ;
        end
        else if (image_num === 5)
        begin
            ctrl_offset = {4'h1, `P_IMG_CTRL5_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `P_BA5_ADDR, 2'b00} ;
            am_offset   = {4'h1, `P_AM5_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `P_TA5_ADDR, 2'b00} ;
        end
 
        // Set Base Address of IMAGE
        config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
 
        // Set Address Mask of IMAGE
        config_write( am_offset, am, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
 
        // Set Translation Address of IMAGE
        config_write( ta_offset, ta, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
 
        // Set IMAGE Control Register
        config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
    end
    else
    begin
        if (image_num === 0)
        begin
        `ifdef  HOST
            `ifdef  NO_CNF_IMAGE
                `ifdef  PCI_IMAGE0  // if PCI bridge is HOST and IMAGE0 is assigned as general image space
                    // set base address
                    `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12     = ba[31:12] ;
                    // set control register
                    `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl0_bit2_1 = {at_en, pref_en} ;
                    // set memory map - part of base address
                    `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit0         = io_nmem ;
                    // set address mask
                    `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am0              = am[31:12] ;
                    // set translation address
                    `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta0              = ta[31:12] ;
                `endif
            `else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
                `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
            `endif
        `else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
        `endif
        end
        else if (image_num === 1)
        begin
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl1_bit2_1 = {at_en, pref_en} ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit31_12     = ba[31:12] ;
        `ifdef  HOST
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit0 = io_nmem ;
        `endif
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am1 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta1 = ta[31:12] ;
        end
        else if (image_num === 2)
        begin
        `ifdef PCI_IMAGE2
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl2_bit2_1 = {at_en, pref_en} ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit31_12     = ba[31:12] ;
            `ifdef  HOST
                `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit0     = io_nmem ;
            `endif
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am2 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta2 = ta[31:12] ;
        `endif
        end
        else if (image_num === 3)
        begin
        `ifdef      PCI_IMAGE3
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl3_bit2_1 = {at_en, pref_en} ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit31_12     = ba[31:12] ;
            `ifdef  HOST
                `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit0 = io_nmem ;
            `endif
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am3 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta3 = ta[31:12] ;
        `endif
        end
        else if (image_num === 4)
        begin
        `ifdef      PCI_IMAGE4
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl4_bit2_1 = {at_en, pref_en} ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit31_12     = ba[31:12] ;
            `ifdef  HOST
                `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit0 = io_nmem ;
            `endif
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am4 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta4 = ta[31:12] ;
        `endif
        end
        else if (image_num === 5)
        begin
        `ifdef      PCI_IMAGE5
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl5_bit2_1 = {at_en, pref_en} ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit31_12     = ba[31:12] ;
            `ifdef  HOST
                `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit0 = io_nmem ;
            `endif
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am5 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta5 = ta[31:12] ;
        `endif
        end
    end
 
    in_use = 1'b0 ;
end
endtask // pci_configure_pci_target_image
 
task pci_configure_wb_slave_image ;
    input        use_bus ;   // selects whether to configure image with bus accesses or directly with dot notation in the configuration space
    input [2:0]  image_num ; // image number
    input [31:0] ba ;        // base address
    input [31:0] am ;        // address mask
    input [31:0] ta ;        // translation address
    input        io_nmem ;   // io/mem mapping select
    input        pref_en ;   // prefetch enable
    input        at_en ;     // address translation enable
    input        mrl_en ;    // memory read line enable
    output       ok ;        // finished succesfully
 
    reg          in_use ;
    reg   [11:0] ctrl_offset ;
    reg   [11:0] ba_offset ;
    reg   [11:0] am_offset ;
    reg   [11:0] ta_offset ;
begin:main
    if (in_use === 1'b1)
    begin
        $display("Time %t", $time) ;
        $display("pci_configure_wb_slave_image task re-entered") ;
        ok = 0 ;
        disable main ;
    end
 
    in_use = 1'b1 ;
    if (use_bus !== 1'b0)
    begin
        if (image_num === 1)
        begin
            ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `W_BA1_ADDR, 2'b00} ;
            am_offset   = {4'h1, `W_AM1_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `W_TA1_ADDR, 2'b00} ;
        end
        else if (image_num === 2)
        begin
            ctrl_offset = {4'h1, `W_IMG_CTRL2_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `W_BA2_ADDR, 2'b00} ;
            am_offset   = {4'h1, `W_AM2_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `W_TA2_ADDR, 2'b00} ;
        end
        else if (image_num === 3)
        begin
            ctrl_offset = {4'h1, `W_IMG_CTRL3_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `W_BA3_ADDR, 2'b00} ;
            am_offset   = {4'h1, `W_AM3_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `W_TA3_ADDR, 2'b00} ;
        end
        else if (image_num === 4)
        begin
            ctrl_offset = {4'h1, `W_IMG_CTRL4_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `W_BA4_ADDR, 2'b00} ;
            am_offset   = {4'h1, `W_AM4_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `W_TA4_ADDR, 2'b00} ;
        end
        else if (image_num === 5)
        begin
            ctrl_offset = {4'h1, `W_IMG_CTRL5_ADDR, 2'b00} ;
            ba_offset   = {4'h1, `W_BA5_ADDR, 2'b00} ;
            am_offset   = {4'h1, `W_AM5_ADDR, 2'b00} ;
            ta_offset   = {4'h1, `W_TA5_ADDR, 2'b00} ;
        end
 
        // Set Base Address of IMAGE
        config_write( ba_offset, ba | {31'h0, io_nmem}, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
 
        // Set Address Mask of IMAGE
        config_write( am_offset, am, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
 
        // Set Translation Address of IMAGE
        config_write( ta_offset, ta, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
 
        // Set IMAGE Control Register
        config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;
        if ( ok !== 1 )
        begin
            in_use = 1'b0 ;
            disable main ;
        end
    end
    else
    begin
        if (image_num === 1)
        begin
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl1_bit2_0 = {at_en, pref_en, mrl_en} ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit31_12 = ba[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit0     = io_nmem ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am1 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta1 = ta[31:12] ;
        end
        else if (image_num === 2)
        begin
        `ifdef WB_IMAGE2
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl2_bit2_0 = {at_en, pref_en, mrl_en} ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit31_12 = ba[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit0     = io_nmem ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am2 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta2 = ta[31:12] ;
        `endif
        end
        else if (image_num === 3)
        begin
        `ifdef WB_IMAGE3
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl3_bit2_0 = {at_en, pref_en, mrl_en} ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit31_12 = ba[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit0     = io_nmem ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am3 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta3 = ta[31:12] ;
        `endif
        end
        else if (image_num === 4)
        begin
        `ifdef WB_IMAGE4
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl4_bit2_0 = {at_en, pref_en, mrl_en} ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit31_12 = ba[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit0     = io_nmem ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am4 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta4 = ta[31:12] ;
        `endif
        end
        else if (image_num === 5)
        begin
        `ifdef WB_IMAGE5
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl5_bit2_0 = {at_en, pref_en, mrl_en} ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit31_12 = ba[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit0     = io_nmem ;
 
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am5 = am[31:12] ;
            `PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta5 = ta[31:12] ;
        `endif
        end
    end
 
    in_use = 1'b0 ;
end
endtask // pci_configure_wb_slave_image

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_bench_common_tasks.v] - Blame information for rev 114

Line No.	Rev	Author	Line
1	73	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_bench_common_tasks.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//`
38			`// CVS Revision History`
39			`//`
40			`// $Log: not supported by cvs2svn $`
41			`//`
42
43			`task pci_configure_pci_target_image ;`
44			`input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space`
45			`input [2:0] image_num ; // image number`
46			`input [31:0] ba ; // base address`
47			`input [31:0] am ; // address mask`
48			`input [31:0] ta ; // translation address`
49			`input io_nmem ; // io/mem mapping select`
50			`input pref_en ; // prefetch enable`
51			`input at_en ; // address translation enable`
52			`output ok ; // finished succesfully`
53
54			`reg in_use ;`
55			`reg [11:0] ctrl_offset ;`
56			`reg [11:0] ba_offset ;`
57			`reg [11:0] am_offset ;`
58			`reg [11:0] ta_offset ;`
59			`begin:main`
60			`if (in_use === 1'b1)`
61			`begin`
62			`$display("Time %t", $time) ;`
63			`$display("pci_configure_pci_target_image task re-entered") ;`
64			`ok = 0 ;`
65			`disable main ;`
66			`end`
67
68			`in_use = 1'b1 ;`
69			`if (use_bus !== 1'b0)`
70			`begin`
71			`if (image_num === 0)`
72			`begin`
73			ctrl_offset = {4'h1, `P_IMG_CTRL0_ADDR, 2'b00} ;
74			ba_offset = {4'h1, `P_BA0_ADDR, 2'b00} ;
75			am_offset = {4'h1, `P_AM0_ADDR, 2'b00} ;
76			ta_offset = {4'h1, `P_TA0_ADDR, 2'b00} ;
77			`end`
78			`else if (image_num === 1)`
79			`begin`
80			ctrl_offset = {4'h1, `P_IMG_CTRL1_ADDR, 2'b00} ;
81			ba_offset = {4'h1, `P_BA1_ADDR, 2'b00} ;
82			am_offset = {4'h1, `P_AM1_ADDR, 2'b00} ;
83			ta_offset = {4'h1, `P_TA1_ADDR, 2'b00} ;
84			`end`
85			`else if (image_num === 2)`
86			`begin`
87			ctrl_offset = {4'h1, `P_IMG_CTRL2_ADDR, 2'b00} ;
88			ba_offset = {4'h1, `P_BA2_ADDR, 2'b00} ;
89			am_offset = {4'h1, `P_AM2_ADDR, 2'b00} ;
90			ta_offset = {4'h1, `P_TA2_ADDR, 2'b00} ;
91			`end`
92			`else if (image_num === 3)`
93			`begin`
94			ctrl_offset = {4'h1, `P_IMG_CTRL3_ADDR, 2'b00} ;
95			ba_offset = {4'h1, `P_BA3_ADDR, 2'b00} ;
96			am_offset = {4'h1, `P_AM3_ADDR, 2'b00} ;
97			ta_offset = {4'h1, `P_TA3_ADDR, 2'b00} ;
98			`end`
99			`else if (image_num === 4)`
100			`begin`
101			ctrl_offset = {4'h1, `P_IMG_CTRL4_ADDR, 2'b00} ;
102			ba_offset = {4'h1, `P_BA4_ADDR, 2'b00} ;
103			am_offset = {4'h1, `P_AM4_ADDR, 2'b00} ;
104			ta_offset = {4'h1, `P_TA4_ADDR, 2'b00} ;
105			`end`
106			`else if (image_num === 5)`
107			`begin`
108			ctrl_offset = {4'h1, `P_IMG_CTRL5_ADDR, 2'b00} ;
109			ba_offset = {4'h1, `P_BA5_ADDR, 2'b00} ;
110			am_offset = {4'h1, `P_AM5_ADDR, 2'b00} ;
111			ta_offset = {4'h1, `P_TA5_ADDR, 2'b00} ;
112			`end`
113
114			`// Set Base Address of IMAGE`
115			`config_write( ba_offset, ba \| {31'h0, io_nmem}, 4'hF, ok ) ;`
116			`if ( ok !== 1 )`
117			`begin`
118			`in_use = 1'b0 ;`
119			`disable main ;`
120			`end`
121
122			`// Set Address Mask of IMAGE`
123			`config_write( am_offset, am, 4'hF, ok ) ;`
124			`if ( ok !== 1 )`
125			`begin`
126			`in_use = 1'b0 ;`
127			`disable main ;`
128			`end`
129
130			`// Set Translation Address of IMAGE`
131			`config_write( ta_offset, ta, 4'hF, ok ) ;`
132			`if ( ok !== 1 )`
133			`begin`
134			`in_use = 1'b0 ;`
135			`disable main ;`
136			`end`
137
138			`// Set IMAGE Control Register`
139			`config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;`
140			`if ( ok !== 1 )`
141			`begin`
142			`in_use = 1'b0 ;`
143			`disable main ;`
144			`end`
145			`end`
146			`else`
147			`begin`
148			`if (image_num === 0)`
149			`begin`
150			`ifdef HOST
151			`ifdef NO_CNF_IMAGE
152			`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
153			`// set base address`
154			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
155			`// set control register`
156			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl0_bit2_1 = {at_en, pref_en} ;
157			`// set memory map - part of base address`
158			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit0 = io_nmem ;
159			`// set address mask`
160			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am0 = am[31:12] ;
161			`// set translation address`
162			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta0 = ta[31:12] ;
163			`endif
164			`else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space
165			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
166			`endif
167			`else // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space
168			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba0_bit31_12 = ba[31:12] ;
169			`endif
170			`end`
171			`else if (image_num === 1)`
172			`begin`
173			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl1_bit2_1 = {at_en, pref_en} ;
174			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit31_12 = ba[31:12] ;
175			`ifdef HOST
176			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba1_bit0 = io_nmem ;
177			`endif
178			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am1 = am[31:12] ;
179			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta1 = ta[31:12] ;
180			`end`
181			`else if (image_num === 2)`
182			`begin`
183			`ifdef PCI_IMAGE2
184			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl2_bit2_1 = {at_en, pref_en} ;
185			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit31_12 = ba[31:12] ;
186			`ifdef HOST
187			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba2_bit0 = io_nmem ;
188			`endif
189			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am2 = am[31:12] ;
190			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta2 = ta[31:12] ;
191			`endif
192			`end`
193			`else if (image_num === 3)`
194			`begin`
195			`ifdef PCI_IMAGE3
196			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl3_bit2_1 = {at_en, pref_en} ;
197			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit31_12 = ba[31:12] ;
198			`ifdef HOST
199			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba3_bit0 = io_nmem ;
200			`endif
201			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am3 = am[31:12] ;
202			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta3 = ta[31:12] ;
203			`endif
204			`end`
205			`else if (image_num === 4)`
206			`begin`
207			`ifdef PCI_IMAGE4
208			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl4_bit2_1 = {at_en, pref_en} ;
209			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit31_12 = ba[31:12] ;
210			`ifdef HOST
211			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba4_bit0 = io_nmem ;
212			`endif
213			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am4 = am[31:12] ;
214			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta4 = ta[31:12] ;
215			`endif
216			`end`
217			`else if (image_num === 5)`
218			`begin`
219			`ifdef PCI_IMAGE5
220			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_img_ctrl5_bit2_1 = {at_en, pref_en} ;
221			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit31_12 = ba[31:12] ;
222			`ifdef HOST
223			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ba5_bit0 = io_nmem ;
224			`endif
225			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_am5 = am[31:12] ;
226			`PCI_BRIDGE_INSTANCE.bridge.configuration.pci_ta5 = ta[31:12] ;
227			`endif
228			`end`
229			`end`
230
231			`in_use = 1'b0 ;`
232			`end`
233			`endtask // pci_configure_pci_target_image`
234
235			`task pci_configure_wb_slave_image ;`
236			`input use_bus ; // selects whether to configure image with bus accesses or directly with dot notation in the configuration space`
237			`input [2:0] image_num ; // image number`
238			`input [31:0] ba ; // base address`
239			`input [31:0] am ; // address mask`
240			`input [31:0] ta ; // translation address`
241			`input io_nmem ; // io/mem mapping select`
242			`input pref_en ; // prefetch enable`
243			`input at_en ; // address translation enable`
244			`input mrl_en ; // memory read line enable`
245			`output ok ; // finished succesfully`
246
247			`reg in_use ;`
248			`reg [11:0] ctrl_offset ;`
249			`reg [11:0] ba_offset ;`
250			`reg [11:0] am_offset ;`
251			`reg [11:0] ta_offset ;`
252			`begin:main`
253			`if (in_use === 1'b1)`
254			`begin`
255			`$display("Time %t", $time) ;`
256			`$display("pci_configure_wb_slave_image task re-entered") ;`
257			`ok = 0 ;`
258			`disable main ;`
259			`end`
260
261			`in_use = 1'b1 ;`
262			`if (use_bus !== 1'b0)`
263			`begin`
264			`if (image_num === 1)`
265			`begin`
266			ctrl_offset = {4'h1, `W_IMG_CTRL1_ADDR, 2'b00} ;
267			ba_offset = {4'h1, `W_BA1_ADDR, 2'b00} ;
268			am_offset = {4'h1, `W_AM1_ADDR, 2'b00} ;
269			ta_offset = {4'h1, `W_TA1_ADDR, 2'b00} ;
270			`end`
271			`else if (image_num === 2)`
272			`begin`
273			ctrl_offset = {4'h1, `W_IMG_CTRL2_ADDR, 2'b00} ;
274			ba_offset = {4'h1, `W_BA2_ADDR, 2'b00} ;
275			am_offset = {4'h1, `W_AM2_ADDR, 2'b00} ;
276			ta_offset = {4'h1, `W_TA2_ADDR, 2'b00} ;
277			`end`
278			`else if (image_num === 3)`
279			`begin`
280			ctrl_offset = {4'h1, `W_IMG_CTRL3_ADDR, 2'b00} ;
281			ba_offset = {4'h1, `W_BA3_ADDR, 2'b00} ;
282			am_offset = {4'h1, `W_AM3_ADDR, 2'b00} ;
283			ta_offset = {4'h1, `W_TA3_ADDR, 2'b00} ;
284			`end`
285			`else if (image_num === 4)`
286			`begin`
287			ctrl_offset = {4'h1, `W_IMG_CTRL4_ADDR, 2'b00} ;
288			ba_offset = {4'h1, `W_BA4_ADDR, 2'b00} ;
289			am_offset = {4'h1, `W_AM4_ADDR, 2'b00} ;
290			ta_offset = {4'h1, `W_TA4_ADDR, 2'b00} ;
291			`end`
292			`else if (image_num === 5)`
293			`begin`
294			ctrl_offset = {4'h1, `W_IMG_CTRL5_ADDR, 2'b00} ;
295			ba_offset = {4'h1, `W_BA5_ADDR, 2'b00} ;
296			am_offset = {4'h1, `W_AM5_ADDR, 2'b00} ;
297			ta_offset = {4'h1, `W_TA5_ADDR, 2'b00} ;
298			`end`
299
300			`// Set Base Address of IMAGE`
301			`config_write( ba_offset, ba \| {31'h0, io_nmem}, 4'hF, ok ) ;`
302			`if ( ok !== 1 )`
303			`begin`
304			`in_use = 1'b0 ;`
305			`disable main ;`
306			`end`
307
308			`// Set Address Mask of IMAGE`
309			`config_write( am_offset, am, 4'hF, ok ) ;`
310			`if ( ok !== 1 )`
311			`begin`
312			`in_use = 1'b0 ;`
313			`disable main ;`
314			`end`
315
316			`// Set Translation Address of IMAGE`
317			`config_write( ta_offset, ta, 4'hF, ok ) ;`
318			`if ( ok !== 1 )`
319			`begin`
320			`in_use = 1'b0 ;`
321			`disable main ;`
322			`end`
323
324			`// Set IMAGE Control Register`
325			`config_write( ctrl_offset, {29'd0, at_en, pref_en, 1'b0}, 4'hF, ok ) ;`
326			`if ( ok !== 1 )`
327			`begin`
328			`in_use = 1'b0 ;`
329			`disable main ;`
330			`end`
331			`end`
332			`else`
333			`begin`
334			`if (image_num === 1)`
335			`begin`
336			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl1_bit2_0 = {at_en, pref_en, mrl_en} ;
337
338			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit31_12 = ba[31:12] ;
339			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba1_bit0 = io_nmem ;
340
341			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am1 = am[31:12] ;
342			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta1 = ta[31:12] ;
343			`end`
344			`else if (image_num === 2)`
345			`begin`
346			`ifdef WB_IMAGE2
347			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl2_bit2_0 = {at_en, pref_en, mrl_en} ;
348
349			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit31_12 = ba[31:12] ;
350			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba2_bit0 = io_nmem ;
351
352			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am2 = am[31:12] ;
353			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta2 = ta[31:12] ;
354			`endif
355			`end`
356			`else if (image_num === 3)`
357			`begin`
358			`ifdef WB_IMAGE3
359			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl3_bit2_0 = {at_en, pref_en, mrl_en} ;
360
361			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit31_12 = ba[31:12] ;
362			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba3_bit0 = io_nmem ;
363
364			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am3 = am[31:12] ;
365			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta3 = ta[31:12] ;
366			`endif
367			`end`
368			`else if (image_num === 4)`
369			`begin`
370			`ifdef WB_IMAGE4
371			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl4_bit2_0 = {at_en, pref_en, mrl_en} ;
372
373			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit31_12 = ba[31:12] ;
374			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba4_bit0 = io_nmem ;
375
376			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am4 = am[31:12] ;
377			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta4 = ta[31:12] ;
378			`endif
379			`end`
380			`else if (image_num === 5)`
381			`begin`
382			`ifdef WB_IMAGE5
383			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_img_ctrl5_bit2_0 = {at_en, pref_en, mrl_en} ;
384
385			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit31_12 = ba[31:12] ;
386			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ba5_bit0 = io_nmem ;
387
388			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_am5 = am[31:12] ;
389			`PCI_BRIDGE_INSTANCE.bridge.configuration.wb_ta5 = ta[31:12] ;
390			`endif
391			`end`
392			`end`
393
394			`in_use = 1'b0 ;`
395			`end`
396			`endtask // pci_configure_wb_slave_image`