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mihad |
//===========================================================================
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mihad |
// $Id: pci_blue_options.vh,v 1.2 2002-08-13 11:03:51 mihad Exp $
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mihad |
//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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// Summary: Constants which select various configuration options used
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// throughout the pci_blue_interface. The user will have to
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// make several choices to select these options for each
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// particular use of this IP.
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//
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// This library is free software; you can distribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this library. If not, write to
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// Free Software Foundation, Inc.
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// 59 Temple Place, Suite 330
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// Boston, MA 02111-1307 USA
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//
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// Author's note about this license: The intention of the Author and of
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// the Gnu Lesser General Public License is that users should be able to
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// use this code for any purpose, including combining it with other source
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// code, combining it with other logic, translated it into a gate-level
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// representation, or projected it into gates in a programmable or
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// hardwired chip, as long as the users of the resulting source, compiled
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// source, or chip are given the means to get a copy of this source code
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// with no new restrictions on redistribution of this source.
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//
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// If you make changes, even substantial changes, to this code, or use
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// substantial parts of this code as an inseparable part of another work
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// of authorship, the users of the resulting IP must be given the means
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// to get a copy of the modified or combined source code, with no new
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// restrictions on redistribution of the resulting source.
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//
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// Seperate parts of the combined source code, compiled code, or chip,
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// which are NOT derived from this source code do NOT need to be offered
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// to the final user of the chip merely because they are used in
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// combination with this code. Other code is not forced to fall under
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// the GNU Lesser General Public License when it is linked to this code.
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// The license terms of other source code linked to this code might require
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// that it NOT be made available to users. The GNU Lesser General Public
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// License does not prevent this code from being used in such a situation,
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// as long as the user of the resulting IP is given the means to get a
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// copy of this component of the IP with no new restrictions on
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// redistribution of this source.
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//
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// This code was developed using VeriLogger Pro, by Synapticad.
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// Their support is greatly appreciated.
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//
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// NOTE: This code has only been tested and might be functional with the
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// following set of options:
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//
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//===========================================================================
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// Include to cause the Monitor Device to report activity.
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//`define VERBOSE_MONITOR_DEVICE
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// define this to get the PCI model to do normal consistency checking
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// undefine this if simulation speed is more important than correctness.
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`define NORMAL_PCI_CHECKS
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// define this to get the monitor to create a PCI Bus Activity Transcript
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`define MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
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// define to cause the Test Device to report top-level activity.
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`define REPORT_TEST_DEVICE
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// define in addition to the above to cause the Test Device to
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// report detailed activity.
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//`define VERBOSE_TEST_DEVICE
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// Indicate whether the PCI Bus will be 64-bit or 32-bit
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// Comment this out if the bus size is 32 bits
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// `define PCI_BUS_SIZE_64
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// Indicate whether the PCI Blue Interface FIFOs are 64-bit or 32-bit
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// Comment this out of the FIFO size is 32 bits
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// `define PCI_FIFO_SIZE_64
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// Indicate whether the intended application is 33 MHz or 66 MHz.
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// If 33 MHz is desired, simply comment out the define line.
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//`define PCI_CLK_66
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// These are the delays that the PCI Pad Drivers in the Test verilog exhibit.
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// They delays are from the PCI Local Bus Spec Revision 2.2 section 7.6.4.2
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`ifdef PCI_CLK_66
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`define PCI_CLK_PERIOD 15.0
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`define PAD_MIN_DATA_DLY 2.0
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`define PAD_MAX_DATA_DLY 6.0
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`define PAD_MIN_OE_DLY 2.0
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`define PAD_MAX_OE_DLY 14.0
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`define PAD_DATA_SETUP 3.0
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`define PAD_DATA_HOLD 0.0
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`define PROP_PLUS_SKEW 6.0
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`else // PCI_CLK_66
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`define PCI_CLK_PERIOD 30.0
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`define PAD_MIN_DATA_DLY 2.0
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`define PAD_MAX_DATA_DLY 11.0
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`define PAD_MIN_OE_DLY 2.0
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`define PAD_MAX_OE_DLY 11.0
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`define PAD_DATA_SETUP 7.0
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`define PAD_DATA_HOLD 0.0
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`define PROP_PLUS_SKEW 12.0
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`endif // PCI_CLK_66
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// Derive Bus Definitions based on declared interface sizes
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// The FIFOs and the PCI Bus are the same width.
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`ifdef PCI_BUS_SIZE_64
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parameter PCI_BUS_DATA_RANGE = 63;
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`define PCI_BUS_DATA_X 64'hXXXXXXXX_XXXXXXXX
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`define PCI_BUS_DATA_Z 64'hZZZZZZZZ_ZZZZZZZZ
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`define PCI_BUS_DATA_ZERO 64'h00000000_00000000
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parameter PCI_BUS_CBE_RANGE = 7;
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`define PCI_BUS_CBE_X 8'hXX
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`define PCI_BUS_CBE_Z 8'hZZ
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`define PCI_BUS_CBE_ZERO 8'h00
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`define PCI_BUS_Address_Mask 64'hFFFFFFFF_FFFFFFF8
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`define PCI_BUS_Address_Step 64'h00000000_00000008
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`else // PCI_BUS_SIZE_64
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parameter PCI_BUS_DATA_RANGE = 31;
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`define PCI_BUS_DATA_X 32'hXXXXXXXX
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`define PCI_BUS_DATA_Z 32'hZZZZZZZZ
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`define PCI_BUS_DATA_ZERO 32'h00000000
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parameter PCI_BUS_CBE_RANGE = 3;
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`define PCI_BUS_CBE_X 4'hX
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`define PCI_BUS_CBE_Z 4'hZ
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`define PCI_BUS_CBE_ZERO 4'h0
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`define PCI_BUS_CBE_F 4'hF
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`define PCI_BUS_Address_Mask 32'hFFFFFFFC
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`define PCI_BUS_Address_Step 32'h00000004
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`endif // PCI_BUS_SIZE_64
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// Define SIMULTANEOUS_MASTER_TARGET if a single interface needs
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// do master references to it's own target interface.
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// Also define SIMULTANEOUS_MASTER_TARGET if there will be several
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// PCI interfaces sharing a single set of IO pads.
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// See the PCI Local Bus Spec Revision 2.2 section 3.10 item 9.
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// Do NOT need to be defined if there is only a single PCI
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// interface or a single multi-function PCI interface on-chip
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// which never talks from it's master to it's target. This
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// paramater makes it harder to meet PCI timing, and makes it
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// impossible to use the nice Xilinx IO pads.
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// NOTE: NOT DEBUGGED. MAYBE SHOULD BE DONE ABOVE IO PADS
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`define SIMULTANEOUS_MASTER_TARGET
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// Define SUPPORT_MULTIPLE_ONCHIP_INTERFACES if several totally
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// independent PCI interfaces will exist on-chip which will take
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// turns using a single set of IO pads. When this option is selected,
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// it is necessary to also define SIMULTANEOUS_MASTER_TARGET. The
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// interface assumes that one master may want to talk to another target.
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// `define SUPPORT_MULTIPLE_ONCHIP_INTERFACES
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// The PCI Controller communicates with the Host Controller bu sending
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// and receiving data through 3 FIFOs. These FIFOs are all the same depth,
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// set here. Allowable depths are 3 entries, 5 entries, 7 entries, and
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// 15 entries. Only one define should be uncommented to choose the size.
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// `define HOST_FIFO_DEPTH_3
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`define HOST_FIFO_DEPTH_5
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// `define HOST_FIFO_DEPTH_7
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// `define HOST_FIFO_DEPTH_15
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// The user also gets to specify here whether the FIFOs are made out of
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// individual Flip-Flops, or whether they use a vendor-supplied Dual Port
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// SRAM primitive.
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// If the FIFOs are 15 entries deep, the FIFOs MUST be made out of SRAMs.
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`define HOST_FIFOS_ARE_MADE_FROM_FLOPS
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// Events made in the PCI Interface are synchronized into the Host clock domain.
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// Synchronizer Flops are prone to metastability, and these Flops are no exception.
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// In order to cross between clock domains, signals must be latched and then have
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// enough time to settle to a safe value.
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// This interface assumes that the Host Clock is significantly faster than the
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// PCI Clock. It is possible that the Host Clock is SO FAST that it is
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// difficult to sychronize a PCI Signal and have it settle to a safe value
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// in 1 Host clock period.
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// This interface tries to assure that the control information has plenty of
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// time to settle by having special constraints on the signals which cross
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// the clock barrier. The target is to have the clock-to-data, plus the
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// delay through any following combinational logic, plus the setup to
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// the next flops, together add up to AT LEAST 2 nSec less than the Host
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// clock period.
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// If the Synchronizers will need more than 1 clock to settle, then the
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// interface has to be compiled with DOUBLE_SYNC_PCI_HOST_SYNCHRONIZERS
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// defined to have the value 1'b1.
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// If the Synchronizers have enough time to settle, define it to 1'b0
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`define DOUBLE_SYNC_PCI_HOST_SYNCHRONIZERS (1'b0)
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// Defines to connect up specific AD lines to IDSEL inputs. Note that
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// the only valid address lines are AD[31:25], because the lower
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// addresses down through AD11 are used to tell the target how to behave.
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`define NO_DEVICE_IDSEL_ADDR (32'h00000000)
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`define REAL_DEVICE_IDSEL_INDEX 24 // NOT used,see SYSTEM.V file
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`define REAL_DEVICE_CONFIG_ADDR (32'h01000000) // NOT used,see SYSTEM.V file
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`define TEST_DEVICE_0_IDSEL_INDEX 25 // NOT used,see SYSTEM.V file
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`define TEST_DEVICE_0_CONFIG_ADDR (32'h02000000) // NOT used,see SYSTEM.V file
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`define TEST_DEVICE_1_IDSEL_INDEX 26 // NOT used,see SYSTEM.V file
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`define TEST_DEVICE_1_CONFIG_ADDR (32'h04000000) // NOT used,see SYSTEM.V file
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// Config Register Area consists of:
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// 31 24 23 16 15 8 7 0
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// | Device ID | Vendor ID | 0x00
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// | Status | Command | 0x04
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// | Class Code | Rev | 0x08
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// | BIST | HEAD | LTCY | CSize| 0x0C
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// | Base Address 0 | 0x10
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// | Base Address 1 | 0x14
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// | Unused | 0x18
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// | Unused | 0x1C
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// | Unused | 0x20
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// | Unused | 0x24
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// | Cardbus Pointer | 0x28
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// | SubSys ID | SubVnd ID | 0x2C
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// | Expansion ROM Pointer | 0x30
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// | Reserved | Cap | 0x34
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// | Reserved | 0x38
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// | MLat | MGnt | IPin | ILine| 0x3C
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//
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// Device ID's are allocated by a particular Vendor.
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// See the PCI Local Bus Spec Revision 2.2 section 6.2.1.
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parameter PCI_DEVICE_ID = 16'h1234;
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// Vendor Types are allocated by the PCI SIG.
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// See the PCI Local Bus Spec Revision 2.2 section 6.2.1.
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parameter PCI_VENDOR_ID = 16'h5678;
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// Header Type says Normal, Single Function.
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// See the PCI Local Bus Spec Revision 2.2 Appendix D.
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parameter PCI_CLASS_CODE = 24'hFF_00_00;
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// Revision Numbers are allocated by a particular Vendor.
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// See the PCI Local Bus Spec Revision 2.2 section 6.2.1.
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parameter PCI_REV_NUM = 8'h00;
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// Header Type says Normal, Single Function.
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// See the PCI Local Bus Spec Revision 2.2 section 6.2.1.
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parameter PCI_HEAD_TYPE = 8'h00;
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// Minimum Grane and Maximum Latency need to be set based
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// on the expected activity of the device. The unit of
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// time is 1/4th uSeconds.
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// See the PCI Local Bus Spec Revision 2.2 section 6.2.4.
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parameter PCI_MIN_GRANT = 8'h01;
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parameter PCI_MAX_LATENCY = 8'h0C;
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// The code to support multiple Base Address Registers is in pci_blue_target.v
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// Match as few bits as needed. This example maps 16 MBytes.
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`define PCI_BASE_ADDR0_MATCH_RANGE 31:20
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`define PCI_BASE_ADDR0_ALL_ZEROS 8'h00
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// Match plus Fill plus Qual must together be 32 bits
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mihad |
`define PCI_BASE_ADDR0_FILL (16'h0000)
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mihad |
// Address Map Qualifier, described in the PCI specification,
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// Revision 2.2, section 6.2.5.1. The value 0x8 indicates
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// that the Base Address size is 32 bits, that it is a Memory
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// mapped Base Address Register, and that data is pre-fetchable
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`define PCI_BASE_ADDR0_MAP_QUAL (4'h8 )
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// Undefine if a second Base Register is not needed
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`define PCI_BASE_ADDR1_MATCH_ENABLE
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`ifdef PCI_BASE_ADDR1_MATCH_ENABLE
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// Match as few bits as needed. This example maps 32 MBytes.
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`define PCI_BASE_ADDR1_MATCH_RANGE 31:20
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`define PCI_BASE_ADDR1_ALL_ZEROS 7'h00
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// Match plus Fill plus Qual must together be 32 bits
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mihad |
`define PCI_BASE_ADDR1_FILL (16'h0000)
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15 |
mihad |
// Address Map Qualifier, described in the PCI specification,
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// Revision 2.2, section 6.2.5.1. The value 0x8 indicates
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// that the Base Address size is 32 bits, that it is a Memory
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// mapped Base Address Register, and that data is pre-fetchable
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mihad |
`define PCI_BASE_ADDR1_MAP_QUAL (4'h1)
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mihad |
`endif // PCI_BASE_ADDR1_MATCH_ENABLE
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// nothing checked after this point
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// PCI_CONFIG_MASTER is defined if this PCI Code is going to be the root
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// of the PCI bus during the configuration process.
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// The result of this define is that an internal wire will be used as the
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// IDSEL wire. If this verilog is configured to not be the PCI Config
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// Master, an external IO Pin will be allocated to serve as the IDSEL pin.
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// In both cases, several values in the Config Data block will need to be
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// initialized before the interface can be initialized for use in a PCI
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// environment. The variables TODO help set up the Config Data.
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// `define PCI_CONFIG_MASTER 1
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// PCI_MASTER is defined if this code is going to serve as a PCI Master as
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// well as a PCI Slave.
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// The result of this define is that a pair of signals used for Request and
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// Grant will be made available. If the interface is designalted the PCI
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// Config Master, these two signals will be internal signals. Otherwise
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// they will go to external IO pads.
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// `define PCI_MASTER 1
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// define?
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// `define PCI_EXTERNAL_IDSEL 1 // define if IDSEL wire driven from offchip
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`define PCI_EXTERNAL_MASTER 1 // define if off-chip PCI arbiter to be used
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// `define PCI_EXTERNAL_INT 1
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// `define PCI_EXTERNAL_CLOCK 1
|
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// `define PCI_MASTER 1
|
305 |
|
|
|
306 |
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// The Host_Command Fifo and the Host_Reply Fifo have entries which
|
307 |
|
|
// contain addresses or data. In addition, each entry contains a
|
308 |
|
|
// tag which explains the meaning of the entry.
|
309 |
|
|
|
310 |
|
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