| 1 |
15 |
mihad |
//===========================================================================
|
| 2 |
106 |
mihad |
// $Id: pci_bus_monitor.v,v 1.4 2003-08-03 18:04:44 mihad Exp $
|
| 3 |
15 |
mihad |
//
|
| 4 |
|
|
// Copyright 2001 Blue Beaver. All Rights Reserved.
|
| 5 |
|
|
//
|
| 6 |
|
|
// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
|
| 7 |
|
|
// This module also has access to the individual PCI Bus OE
|
| 8 |
|
|
// signals for each interface (either through extra output
|
| 9 |
|
|
// ports or through "." notation), and it can see when more
|
| 10 |
|
|
// than one interface is driving the bus, even if the values
|
| 11 |
|
|
// are the same.
|
| 12 |
|
|
// A future version of this module should write out a transcript
|
| 13 |
|
|
// of the activity seen on the PCI Bus.
|
| 14 |
|
|
//
|
| 15 |
|
|
// This library is free software; you can distribute it and/or modify it
|
| 16 |
|
|
// under the terms of the GNU Lesser General Public License as published
|
| 17 |
|
|
// by the Free Software Foundation; either version 2.1 of the License, or
|
| 18 |
|
|
// (at your option) any later version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// This library is distributed in the hope that it will be useful, but
|
| 21 |
|
|
// WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 22 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
| 23 |
|
|
// See the GNU Lesser General Public License for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU Lesser General Public License
|
| 26 |
|
|
// along with this library. If not, write to
|
| 27 |
|
|
// Free Software Foundation, Inc.
|
| 28 |
|
|
// 59 Temple Place, Suite 330
|
| 29 |
|
|
// Boston, MA 02111-1307 USA
|
| 30 |
|
|
//
|
| 31 |
|
|
// Author's note about this license: The intention of the Author and of
|
| 32 |
|
|
// the Gnu Lesser General Public License is that users should be able to
|
| 33 |
|
|
// use this code for any purpose, including combining it with other source
|
| 34 |
|
|
// code, combining it with other logic, translated it into a gate-level
|
| 35 |
|
|
// representation, or projected it into gates in a programmable or
|
| 36 |
|
|
// hardwired chip, as long as the users of the resulting source, compiled
|
| 37 |
|
|
// source, or chip are given the means to get a copy of this source code
|
| 38 |
|
|
// with no new restrictions on redistribution of this source.
|
| 39 |
|
|
//
|
| 40 |
|
|
// If you make changes, even substantial changes, to this code, or use
|
| 41 |
|
|
// substantial parts of this code as an inseparable part of another work
|
| 42 |
|
|
// of authorship, the users of the resulting IP must be given the means
|
| 43 |
|
|
// to get a copy of the modified or combined source code, with no new
|
| 44 |
|
|
// restrictions on redistribution of the resulting source.
|
| 45 |
|
|
//
|
| 46 |
|
|
// Separate parts of the combined source code, compiled code, or chip,
|
| 47 |
|
|
// which are NOT derived from this source code do NOT need to be offered
|
| 48 |
|
|
// to the final user of the chip merely because they are used in
|
| 49 |
|
|
// combination with this code. Other code is not forced to fall under
|
| 50 |
|
|
// the GNU Lesser General Public License when it is linked to this code.
|
| 51 |
|
|
// The license terms of other source code linked to this code might require
|
| 52 |
|
|
// that it NOT be made available to users. The GNU Lesser General Public
|
| 53 |
|
|
// License does not prevent this code from being used in such a situation,
|
| 54 |
|
|
// as long as the user of the resulting IP is given the means to get a
|
| 55 |
|
|
// copy of this component of the IP with no new restrictions on
|
| 56 |
|
|
// redistribution of this source.
|
| 57 |
|
|
//
|
| 58 |
|
|
// This code was developed using VeriLogger Pro, by Synapticad.
|
| 59 |
|
|
// Their support is greatly appreciated.
|
| 60 |
|
|
//
|
| 61 |
|
|
// NOTE: This module watches the PCI bus and gives commentary about what
|
| 62 |
|
|
// it sees.
|
| 63 |
|
|
// I hope that this can get a parameter which says whether to put
|
| 64 |
|
|
// its log in a file, on the terminal, or both.
|
| 65 |
|
|
//
|
| 66 |
|
|
// TO DO: create code to act on MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
|
| 67 |
|
|
//
|
| 68 |
|
|
//===========================================================================
|
| 69 |
|
|
|
| 70 |
|
|
// Note that master aborts are the norm on Special Cycles!
|
| 71 |
|
|
|
| 72 |
35 |
mihad |
// synopsys translate_off
|
| 73 |
|
|
`include "timescale.v"
|
| 74 |
|
|
// synopsys translate_on
|
| 75 |
|
|
//`timescale 1ns/10ps
|
| 76 |
15 |
mihad |
|
| 77 |
|
|
module pci_bus_monitor (
|
| 78 |
|
|
pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
|
| 79 |
|
|
pci_ext_frame_l, pci_ext_irdy_l,
|
| 80 |
|
|
pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
|
| 81 |
|
|
pci_ext_perr_l, pci_ext_serr_l,
|
| 82 |
|
|
pci_real_req_l, pci_real_gnt_l,
|
| 83 |
|
|
pci_ext_req_l, pci_ext_gnt_l,
|
| 84 |
|
|
test_error_event, test_observe_r_oe_sigs,
|
| 85 |
|
|
test_observe_0_oe_sigs, test_observe_1_oe_sigs,
|
| 86 |
|
|
test_observe_2_oe_sigs, test_observe_3_oe_sigs,
|
| 87 |
|
|
pci_ext_reset_l, pci_ext_clk,
|
| 88 |
|
|
log_file_desc
|
| 89 |
|
|
);
|
| 90 |
|
|
|
| 91 |
|
|
`include "pci_blue_options.vh"
|
| 92 |
|
|
`include "pci_blue_constants.vh"
|
| 93 |
|
|
|
| 94 |
|
|
input [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
|
| 95 |
|
|
input [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
|
| 96 |
|
|
input pci_ext_par;
|
| 97 |
|
|
input pci_ext_frame_l, pci_ext_irdy_l;
|
| 98 |
|
|
input pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
|
| 99 |
|
|
input pci_ext_perr_l, pci_ext_serr_l;
|
| 100 |
|
|
input pci_real_req_l, pci_real_gnt_l;
|
| 101 |
|
|
input [3:0] pci_ext_req_l;
|
| 102 |
|
|
input [3:0] pci_ext_gnt_l;
|
| 103 |
|
|
output test_error_event;
|
| 104 |
|
|
input [5:0] test_observe_r_oe_sigs;
|
| 105 |
|
|
input [5:0] test_observe_0_oe_sigs;
|
| 106 |
|
|
input [5:0] test_observe_1_oe_sigs;
|
| 107 |
|
|
input [5:0] test_observe_2_oe_sigs;
|
| 108 |
|
|
input [5:0] test_observe_3_oe_sigs;
|
| 109 |
|
|
|
| 110 |
|
|
input pci_ext_reset_l, pci_ext_clk;
|
| 111 |
|
|
|
| 112 |
|
|
input [31:0] log_file_desc ;
|
| 113 |
|
|
// Make temporary Bip every time an error is detected
|
| 114 |
|
|
reg test_error_event;
|
| 115 |
|
|
initial test_error_event <= 1'bZ;
|
| 116 |
|
|
reg error_detected;
|
| 117 |
|
|
initial error_detected <= 1'b0;
|
| 118 |
|
|
always @(error_detected)
|
| 119 |
|
|
begin
|
| 120 |
|
|
test_error_event <= 1'b0;
|
| 121 |
|
|
#2;
|
| 122 |
|
|
test_error_event <= 1'bZ;
|
| 123 |
|
|
end
|
| 124 |
|
|
|
| 125 |
|
|
// watch for the PCI Clock going X
|
| 126 |
|
|
always @(pci_ext_clk)
|
| 127 |
|
|
begin
|
| 128 |
|
|
if (($time > 0) && ((pci_ext_clk ^ pci_ext_clk) === 1'bx))
|
| 129 |
|
|
begin
|
| 130 |
|
|
$display ("*** monitor - PCI External Clock invalid 'h%x, at %t",
|
| 131 |
|
|
pci_ext_clk, $time);
|
| 132 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External Clock invalid 'h%x, at %t",
|
| 133 |
|
|
pci_ext_clk, $time);
|
| 134 |
|
|
error_detected <= ~error_detected;
|
| 135 |
|
|
end
|
| 136 |
|
|
`NO_ELSE;
|
| 137 |
|
|
end
|
| 138 |
|
|
|
| 139 |
|
|
// watch for the Reset signal going X
|
| 140 |
|
|
always @(pci_ext_reset_l)
|
| 141 |
|
|
begin
|
| 142 |
|
|
if (($time > 0) & ((pci_ext_reset_l ^ pci_ext_reset_l) === 1'bx))
|
| 143 |
|
|
begin
|
| 144 |
|
|
$display ("*** monitor - PCI External RESET_L invalid 'h%x, at %t",
|
| 145 |
|
|
pci_ext_reset_l, $time);
|
| 146 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External RESET_L invalid 'h%x, at %t",
|
| 147 |
|
|
pci_ext_reset_l, $time);
|
| 148 |
|
|
error_detected <= ~error_detected;
|
| 149 |
|
|
end
|
| 150 |
|
|
`NO_ELSE;
|
| 151 |
|
|
end
|
| 152 |
|
|
|
| 153 |
|
|
// Make sure all PCI signals are HIGH-Z or Deasserted HIGH as needed
|
| 154 |
|
|
// when the external PCI bus leaves reset.
|
| 155 |
|
|
// The values of some signals are set by pullups on the PC board
|
| 156 |
|
|
always @(posedge pci_ext_reset_l)
|
| 157 |
|
|
begin
|
| 158 |
|
|
if ($time > 0)
|
| 159 |
|
|
begin
|
| 160 |
|
|
if (pci_ext_ad[PCI_BUS_DATA_RANGE:0] !== `PCI_BUS_DATA_Z)
|
| 161 |
|
|
begin
|
| 162 |
|
|
$display ("*** monitor - PCI External AD not high-Z 'h%x, at %t",
|
| 163 |
|
|
pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
|
| 164 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External AD not high-Z 'h%x, at %t",
|
| 165 |
|
|
pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
|
| 166 |
|
|
error_detected <= ~error_detected;
|
| 167 |
|
|
end
|
| 168 |
|
|
`NO_ELSE;
|
| 169 |
|
|
if (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] !== `PCI_BUS_CBE_Z)
|
| 170 |
|
|
begin
|
| 171 |
|
|
$display ("*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
|
| 172 |
|
|
pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
|
| 173 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
|
| 174 |
|
|
pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
|
| 175 |
|
|
error_detected <= ~error_detected;
|
| 176 |
|
|
end
|
| 177 |
|
|
`NO_ELSE;
|
| 178 |
|
|
if (pci_ext_par !== 1'bz)
|
| 179 |
|
|
begin
|
| 180 |
|
|
$display ("*** monitor - PCI External PAR not high-Z 'h%x, at %t",
|
| 181 |
|
|
pci_ext_par, $time);
|
| 182 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External PAR not high-Z 'h%x, at %t",
|
| 183 |
|
|
pci_ext_par, $time);
|
| 184 |
|
|
error_detected <= ~error_detected;
|
| 185 |
|
|
end
|
| 186 |
|
|
`NO_ELSE;
|
| 187 |
|
|
if (pci_ext_frame_l !== 1'b1)
|
| 188 |
|
|
begin
|
| 189 |
|
|
$display ("*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
|
| 190 |
|
|
pci_ext_frame_l, $time);
|
| 191 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
|
| 192 |
|
|
pci_ext_frame_l, $time);
|
| 193 |
|
|
error_detected <= ~error_detected;
|
| 194 |
|
|
end
|
| 195 |
|
|
`NO_ELSE;
|
| 196 |
|
|
if (pci_ext_irdy_l !== 1'b1)
|
| 197 |
|
|
begin
|
| 198 |
|
|
$display ("*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
|
| 199 |
|
|
pci_ext_irdy_l, $time);
|
| 200 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
|
| 201 |
|
|
pci_ext_irdy_l, $time);
|
| 202 |
|
|
error_detected <= ~error_detected;
|
| 203 |
|
|
end
|
| 204 |
|
|
`NO_ELSE;
|
| 205 |
|
|
if (pci_ext_devsel_l !== 1'b1)
|
| 206 |
|
|
begin
|
| 207 |
|
|
$display ("*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
|
| 208 |
|
|
pci_ext_devsel_l, $time);
|
| 209 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
|
| 210 |
|
|
pci_ext_devsel_l, $time);
|
| 211 |
|
|
error_detected <= ~error_detected;
|
| 212 |
|
|
end
|
| 213 |
|
|
`NO_ELSE;
|
| 214 |
|
|
if (pci_ext_trdy_l !== 1'b1)
|
| 215 |
|
|
begin
|
| 216 |
|
|
$display ("*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
|
| 217 |
|
|
pci_ext_trdy_l, $time);
|
| 218 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
|
| 219 |
|
|
pci_ext_trdy_l, $time);
|
| 220 |
|
|
error_detected <= ~error_detected;
|
| 221 |
|
|
end
|
| 222 |
|
|
`NO_ELSE;
|
| 223 |
|
|
if (pci_ext_stop_l !== 1'b1)
|
| 224 |
|
|
begin
|
| 225 |
|
|
$display ("*** monitor - PCI External STOP_L invalid 'h%x, at %t",
|
| 226 |
|
|
pci_ext_stop_l, $time);
|
| 227 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External STOP_L invalid 'h%x, at %t",
|
| 228 |
|
|
pci_ext_stop_l, $time);
|
| 229 |
|
|
error_detected <= ~error_detected;
|
| 230 |
|
|
end
|
| 231 |
|
|
`NO_ELSE;
|
| 232 |
|
|
if (pci_ext_perr_l !== 1'b1)
|
| 233 |
|
|
begin
|
| 234 |
|
|
$display ("*** monitor - PCI External PERR_L invalid 'h%x, at %t",
|
| 235 |
|
|
pci_ext_perr_l, $time);
|
| 236 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External PERR_L invalid 'h%x, at %t",
|
| 237 |
|
|
pci_ext_perr_l, $time);
|
| 238 |
|
|
error_detected <= ~error_detected;
|
| 239 |
|
|
end
|
| 240 |
|
|
`NO_ELSE;
|
| 241 |
|
|
if (pci_ext_serr_l !== 1'b1)
|
| 242 |
|
|
begin
|
| 243 |
|
|
$display ("*** monitor - PCI External SERR_L invalid 'h%x, at %t",
|
| 244 |
|
|
pci_ext_serr_l, $time);
|
| 245 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External SERR_L invalid 'h%x, at %t",
|
| 246 |
|
|
pci_ext_serr_l, $time);
|
| 247 |
|
|
error_detected <= ~error_detected;
|
| 248 |
|
|
end
|
| 249 |
|
|
`NO_ELSE;
|
| 250 |
|
|
if (pci_real_req_l !== 1'b1)
|
| 251 |
|
|
begin
|
| 252 |
|
|
$display ("*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
|
| 253 |
|
|
pci_real_req_l, $time);
|
| 254 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
|
| 255 |
|
|
pci_real_req_l, $time);
|
| 256 |
|
|
error_detected <= ~error_detected;
|
| 257 |
|
|
end
|
| 258 |
|
|
`NO_ELSE;
|
| 259 |
|
|
if (pci_real_gnt_l !== 1'b1)
|
| 260 |
|
|
begin
|
| 261 |
|
|
$display ("*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
|
| 262 |
|
|
pci_real_gnt_l, $time);
|
| 263 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
|
| 264 |
|
|
pci_real_gnt_l, $time);
|
| 265 |
|
|
error_detected <= ~error_detected;
|
| 266 |
|
|
end
|
| 267 |
|
|
`NO_ELSE;
|
| 268 |
|
|
if (pci_ext_req_l[3:0] !== 4'hF)
|
| 269 |
|
|
begin
|
| 270 |
|
|
$display ("*** monitor - PCI External REQ_L invalid 'h%x, at %t",
|
| 271 |
|
|
pci_ext_req_l[3:0], $time);
|
| 272 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External REQ_L invalid 'h%x, at %t",
|
| 273 |
|
|
pci_ext_req_l[3:0], $time);
|
| 274 |
|
|
error_detected <= ~error_detected;
|
| 275 |
|
|
end
|
| 276 |
|
|
`NO_ELSE;
|
| 277 |
|
|
if (pci_ext_gnt_l[3:0] !== 4'hF)
|
| 278 |
|
|
begin
|
| 279 |
|
|
$display ("*** monitor - PCI External GNT_L invalid 'h%x, at %t",
|
| 280 |
|
|
pci_ext_gnt_l[3:0], $time);
|
| 281 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI External GNT_L invalid 'h%x, at %t",
|
| 282 |
|
|
pci_ext_gnt_l[3:0], $time);
|
| 283 |
|
|
error_detected <= ~error_detected;
|
| 284 |
|
|
end
|
| 285 |
|
|
`NO_ELSE;
|
| 286 |
|
|
end
|
| 287 |
|
|
`NO_ELSE;
|
| 288 |
|
|
end
|
| 289 |
|
|
|
| 290 |
|
|
task Watch_For_X_On_OE_Sigs;
|
| 291 |
|
|
input [2:0] signal_source;
|
| 292 |
|
|
input [5:0] oe_signals;
|
| 293 |
|
|
begin
|
| 294 |
|
|
if ((^oe_signals[5:0]) === 1'bX)
|
| 295 |
|
|
begin
|
| 296 |
|
|
if (signal_source[2:0] == `Test_Master_Real)
|
| 297 |
|
|
begin
|
| 298 |
|
|
$display ("*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
| 299 |
|
|
oe_signals[5:0], $time);
|
| 300 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
| 301 |
|
|
oe_signals[5:0], $time);
|
| 302 |
|
|
end
|
| 303 |
|
|
else
|
| 304 |
|
|
begin
|
| 305 |
|
|
$display ("*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
| 306 |
|
|
signal_source[2:0], oe_signals[5:0], $time);
|
| 307 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
| 308 |
|
|
signal_source[2:0], oe_signals[5:0], $time);
|
| 309 |
|
|
error_detected <= ~error_detected;
|
| 310 |
|
|
end
|
| 311 |
|
|
end
|
| 312 |
|
|
`NO_ELSE;
|
| 313 |
|
|
end
|
| 314 |
|
|
endtask
|
| 315 |
|
|
|
| 316 |
|
|
task Watch_For_Simultaneous_Drive_Of_OE_Sigs;
|
| 317 |
|
|
input [2:0] signal_source_0;
|
| 318 |
|
|
input [2:0] signal_source_1;
|
| 319 |
|
|
input [5:0] oe_signals_0;
|
| 320 |
|
|
input [5:0] oe_signals_1;
|
| 321 |
|
|
begin
|
| 322 |
|
|
if ((oe_signals_0 & oe_signals_1) !== 6'h00)
|
| 323 |
|
|
begin
|
| 324 |
|
|
if (signal_source_0[2:0] == `Test_Master_Real)
|
| 325 |
|
|
begin
|
| 326 |
|
|
$display ("*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 327 |
|
|
signal_source_1[2:0], oe_signals_0[5:0],
|
| 328 |
|
|
oe_signals_1[5:0], $time);
|
| 329 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 330 |
|
|
signal_source_1[2:0], oe_signals_0[5:0],
|
| 331 |
|
|
oe_signals_1[5:0], $time);
|
| 332 |
|
|
end
|
| 333 |
|
|
else if (signal_source_1[2:0] == `Test_Master_Real)
|
| 334 |
|
|
begin
|
| 335 |
|
|
$display ("*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 336 |
|
|
signal_source_0[2:0], oe_signals_0[5:0],
|
| 337 |
|
|
oe_signals_1[5:0], $time);
|
| 338 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 339 |
|
|
signal_source_0[2:0], oe_signals_0[5:0],
|
| 340 |
|
|
oe_signals_1[5:0], $time);
|
| 341 |
|
|
end
|
| 342 |
|
|
else
|
| 343 |
|
|
begin
|
| 344 |
|
|
$display ("*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 345 |
|
|
signal_source_0[2:0], signal_source_1[1:0],
|
| 346 |
|
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
| 347 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 348 |
|
|
signal_source_0[2:0], signal_source_1[1:0],
|
| 349 |
|
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
| 350 |
|
|
end
|
| 351 |
|
|
error_detected <= ~error_detected;
|
| 352 |
|
|
end
|
| 353 |
|
|
`NO_ELSE;
|
| 354 |
|
|
end
|
| 355 |
|
|
endtask
|
| 356 |
|
|
|
| 357 |
|
|
task Watch_For_Deassert_Before_Tristate ;
|
| 358 |
|
|
input [2:0] signal_source ;
|
| 359 |
|
|
input [5:0] prev_oe_sigs ;
|
| 360 |
|
|
input [5:0] current_oe_sigs ;
|
| 361 |
|
|
input prev_perr ;
|
| 362 |
|
|
input prev_frame ;
|
| 363 |
|
|
input prev_irdy ;
|
| 364 |
|
|
input prev_trdy ;
|
| 365 |
|
|
input prev_stop ;
|
| 366 |
|
|
input prev_devsel ;
|
| 367 |
|
|
reg do_error ;
|
| 368 |
|
|
begin
|
| 369 |
|
|
do_error = 0 ;
|
| 370 |
|
|
if ( prev_oe_sigs[0] && !current_oe_sigs[0] && prev_perr )
|
| 371 |
|
|
begin
|
| 372 |
|
|
do_error = 1 ;
|
| 373 |
|
|
if ( signal_source == `Test_Master_Real )
|
| 374 |
|
|
begin
|
| 375 |
|
|
$display("*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
|
| 376 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
|
| 377 |
|
|
end
|
| 378 |
|
|
else
|
| 379 |
|
|
begin
|
| 380 |
|
|
$display("*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 381 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 382 |
|
|
end
|
| 383 |
|
|
end
|
| 384 |
|
|
|
| 385 |
|
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_stop )
|
| 386 |
|
|
begin
|
| 387 |
|
|
do_error = 1 ;
|
| 388 |
|
|
if ( signal_source == `Test_Master_Real )
|
| 389 |
|
|
begin
|
| 390 |
|
|
$display("*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
|
| 391 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
|
| 392 |
|
|
end
|
| 393 |
|
|
else
|
| 394 |
|
|
begin
|
| 395 |
|
|
$display("*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 396 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 397 |
|
|
end
|
| 398 |
|
|
end
|
| 399 |
|
|
|
| 400 |
|
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_trdy )
|
| 401 |
|
|
begin
|
| 402 |
|
|
do_error = 1 ;
|
| 403 |
|
|
if ( signal_source == `Test_Master_Real )
|
| 404 |
|
|
begin
|
| 405 |
|
|
$display("*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
|
| 406 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
|
| 407 |
|
|
end
|
| 408 |
|
|
else
|
| 409 |
|
|
begin
|
| 410 |
|
|
$display("*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 411 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 412 |
|
|
end
|
| 413 |
|
|
end
|
| 414 |
|
|
|
| 415 |
|
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_devsel )
|
| 416 |
|
|
begin
|
| 417 |
|
|
do_error = 1 ;
|
| 418 |
|
|
if ( signal_source == `Test_Master_Real )
|
| 419 |
|
|
begin
|
| 420 |
|
|
$display("*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
|
| 421 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
|
| 422 |
|
|
end
|
| 423 |
|
|
else
|
| 424 |
|
|
begin
|
| 425 |
|
|
$display("*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 426 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 427 |
|
|
end
|
| 428 |
|
|
end
|
| 429 |
|
|
|
| 430 |
|
|
if ( prev_oe_sigs[4] && !current_oe_sigs[4] && prev_irdy )
|
| 431 |
|
|
begin
|
| 432 |
|
|
do_error = 1 ;
|
| 433 |
|
|
if ( signal_source == `Test_Master_Real )
|
| 434 |
|
|
begin
|
| 435 |
|
|
$display("*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
|
| 436 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
|
| 437 |
|
|
end
|
| 438 |
|
|
else
|
| 439 |
|
|
begin
|
| 440 |
|
|
$display("*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 441 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 442 |
|
|
end
|
| 443 |
|
|
end
|
| 444 |
|
|
|
| 445 |
|
|
if ( prev_oe_sigs[5] && !current_oe_sigs[5] && prev_frame )
|
| 446 |
|
|
begin
|
| 447 |
|
|
do_error = 1 ;
|
| 448 |
|
|
if ( signal_source == `Test_Master_Real )
|
| 449 |
|
|
begin
|
| 450 |
|
|
$display("*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
|
| 451 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
|
| 452 |
|
|
end
|
| 453 |
|
|
else
|
| 454 |
|
|
begin
|
| 455 |
|
|
$display("*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 456 |
|
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
| 457 |
|
|
end
|
| 458 |
|
|
end
|
| 459 |
|
|
|
| 460 |
|
|
if ( do_error )
|
| 461 |
|
|
error_detected <= ~error_detected ;
|
| 462 |
|
|
end
|
| 463 |
|
|
endtask
|
| 464 |
|
|
|
| 465 |
|
|
task Watch_For_Back_To_Back_Drive_Of_OE_Sigs;
|
| 466 |
|
|
input [2:0] signal_source_0;
|
| 467 |
|
|
input [2:0] signal_source_1;
|
| 468 |
|
|
input [5:0] oe_signals_0;
|
| 469 |
|
|
input [5:0] oe_signals_1;
|
| 470 |
|
|
begin
|
| 471 |
|
|
if ((oe_signals_0 & oe_signals_1) !== 6'h00)
|
| 472 |
|
|
begin
|
| 473 |
|
|
if (signal_source_0[2:0] == `Test_Master_Real)
|
| 474 |
|
|
begin
|
| 475 |
|
|
$display ("*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 476 |
|
|
signal_source_1[2:0], oe_signals_0[5:0],
|
| 477 |
|
|
oe_signals_1[5:0], $time);
|
| 478 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 479 |
|
|
signal_source_1[2:0], oe_signals_0[5:0],
|
| 480 |
|
|
oe_signals_1[5:0], $time);
|
| 481 |
|
|
end
|
| 482 |
|
|
else if (signal_source_1[2:0] == `Test_Master_Real)
|
| 483 |
|
|
begin
|
| 484 |
|
|
$display ("*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 485 |
|
|
signal_source_0[2:0], oe_signals_0[5:0],
|
| 486 |
|
|
oe_signals_1[5:0], $time);
|
| 487 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 488 |
|
|
signal_source_0[2:0], oe_signals_0[5:0],
|
| 489 |
|
|
oe_signals_1[5:0], $time);
|
| 490 |
|
|
end
|
| 491 |
|
|
else
|
| 492 |
|
|
begin
|
| 493 |
|
|
$display ("*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 494 |
|
|
signal_source_0[2:0], signal_source_1[1:0],
|
| 495 |
|
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
| 496 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
| 497 |
|
|
signal_source_0[2:0], signal_source_1[1:0],
|
| 498 |
|
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
| 499 |
|
|
end
|
| 500 |
|
|
error_detected <= ~error_detected;
|
| 501 |
|
|
end
|
| 502 |
|
|
`NO_ELSE;
|
| 503 |
|
|
end
|
| 504 |
|
|
endtask
|
| 505 |
|
|
|
| 506 |
|
|
// watch for PCI devices simultaneously driving PCI wires
|
| 507 |
|
|
// OE Observation signals are
|
| 508 |
|
|
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
|
| 509 |
|
|
// Unused ports should be wired to 0
|
| 510 |
|
|
reg [5:0] prev_real_oe_sigs;
|
| 511 |
|
|
reg [5:0] prev_test_0_oe_sigs;
|
| 512 |
|
|
reg [5:0] prev_test_1_oe_sigs;
|
| 513 |
|
|
reg [5:0] prev_test_2_oe_sigs;
|
| 514 |
|
|
reg [5:0] prev_test_3_oe_sigs;
|
| 515 |
|
|
|
| 516 |
|
|
// Make Asserted HIGH signals to prevent (cause?) confusion
|
| 517 |
|
|
wire frame_now = ~pci_ext_frame_l;
|
| 518 |
|
|
wire irdy_now = ~pci_ext_irdy_l;
|
| 519 |
|
|
wire devsel_now = ~pci_ext_devsel_l;
|
| 520 |
|
|
wire trdy_now = ~pci_ext_trdy_l;
|
| 521 |
|
|
wire stop_now = ~pci_ext_stop_l;
|
| 522 |
|
|
wire perr_now = ~pci_ext_perr_l;
|
| 523 |
|
|
// Delay PCI bus signals, used by several tests below.
|
| 524 |
|
|
// Detect Address Phases on the bus.
|
| 525 |
|
|
// Ignore Dual Access Cycle, as mentioned in the PCI Local Bus Spec
|
| 526 |
|
|
// Revision 2.2 section 3.1.1.
|
| 527 |
|
|
reg [4:0] grant_prev;
|
| 528 |
|
|
reg [PCI_BUS_DATA_RANGE:0] ad_prev;
|
| 529 |
|
|
reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
|
| 530 |
|
|
reg frame_prev, irdy_prev, devsel_prev, trdy_prev, stop_prev, perr_prev;
|
| 531 |
|
|
reg address_phase_prev, read_operation_prev;
|
| 532 |
|
|
|
| 533 |
|
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
| 534 |
|
|
begin
|
| 535 |
|
|
if (pci_ext_reset_l == 1'b0)
|
| 536 |
|
|
begin
|
| 537 |
|
|
prev_real_oe_sigs <= 6'h00;
|
| 538 |
|
|
prev_test_0_oe_sigs <= 6'h00;
|
| 539 |
|
|
prev_test_1_oe_sigs <= 6'h00;
|
| 540 |
|
|
prev_test_2_oe_sigs <= 6'h00;
|
| 541 |
|
|
prev_test_3_oe_sigs <= 6'h00;
|
| 542 |
|
|
end
|
| 543 |
|
|
else
|
| 544 |
|
|
begin
|
| 545 |
|
|
prev_real_oe_sigs <= test_observe_r_oe_sigs[5:0];
|
| 546 |
|
|
prev_test_0_oe_sigs <= test_observe_0_oe_sigs[5:0];
|
| 547 |
|
|
prev_test_1_oe_sigs <= test_observe_1_oe_sigs[5:0];
|
| 548 |
|
|
prev_test_2_oe_sigs <= test_observe_2_oe_sigs[5:0];
|
| 549 |
|
|
prev_test_3_oe_sigs <= test_observe_3_oe_sigs[5:0];
|
| 550 |
|
|
end
|
| 551 |
|
|
end
|
| 552 |
|
|
|
| 553 |
|
|
always @(posedge pci_ext_clk)
|
| 554 |
|
|
begin
|
| 555 |
|
|
if (($time > 0) & (pci_ext_reset_l == 1'b1))
|
| 556 |
|
|
begin
|
| 557 |
|
|
Watch_For_X_On_OE_Sigs (`Test_Master_Real, test_observe_r_oe_sigs[5:0]);
|
| 558 |
|
|
Watch_For_X_On_OE_Sigs (3'h0, test_observe_0_oe_sigs[5:0]);
|
| 559 |
|
|
Watch_For_X_On_OE_Sigs (3'h1, test_observe_1_oe_sigs[5:0]);
|
| 560 |
|
|
Watch_For_X_On_OE_Sigs (3'h2, test_observe_2_oe_sigs[5:0]);
|
| 561 |
|
|
Watch_For_X_On_OE_Sigs (3'h3, test_observe_3_oe_sigs[5:0]);
|
| 562 |
|
|
|
| 563 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
|
| 564 |
|
|
test_observe_r_oe_sigs[5:0], test_observe_0_oe_sigs[5:0]);
|
| 565 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
|
| 566 |
|
|
test_observe_r_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
|
| 567 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
|
| 568 |
|
|
test_observe_r_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
| 569 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
|
| 570 |
|
|
test_observe_r_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
| 571 |
|
|
|
| 572 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h1,
|
| 573 |
|
|
test_observe_0_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
|
| 574 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h2,
|
| 575 |
|
|
test_observe_0_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
| 576 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h3,
|
| 577 |
|
|
test_observe_0_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
| 578 |
|
|
|
| 579 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h2,
|
| 580 |
|
|
test_observe_1_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
| 581 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h3,
|
| 582 |
|
|
test_observe_1_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
| 583 |
|
|
|
| 584 |
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h2, 3'h3,
|
| 585 |
|
|
test_observe_2_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
| 586 |
|
|
|
| 587 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
|
| 588 |
|
|
test_observe_r_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
| 589 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
|
| 590 |
|
|
test_observe_r_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
| 591 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
|
| 592 |
|
|
test_observe_r_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
| 593 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
|
| 594 |
|
|
test_observe_r_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
| 595 |
|
|
|
| 596 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, `Test_Master_Real,
|
| 597 |
|
|
test_observe_0_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
| 598 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h1,
|
| 599 |
|
|
test_observe_0_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
| 600 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h2,
|
| 601 |
|
|
test_observe_0_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
| 602 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h3,
|
| 603 |
|
|
test_observe_0_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
| 604 |
|
|
|
| 605 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h0,
|
| 606 |
|
|
test_observe_1_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
| 607 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, `Test_Master_Real,
|
| 608 |
|
|
test_observe_1_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
| 609 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h2,
|
| 610 |
|
|
test_observe_1_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
| 611 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h3,
|
| 612 |
|
|
test_observe_1_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
| 613 |
|
|
|
| 614 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h0,
|
| 615 |
|
|
test_observe_2_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
| 616 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h1,
|
| 617 |
|
|
test_observe_2_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
| 618 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, `Test_Master_Real,
|
| 619 |
|
|
test_observe_2_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
| 620 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h3,
|
| 621 |
|
|
test_observe_2_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
| 622 |
|
|
|
| 623 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h0,
|
| 624 |
|
|
test_observe_3_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
| 625 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h1,
|
| 626 |
|
|
test_observe_3_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
| 627 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h2,
|
| 628 |
|
|
test_observe_3_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
| 629 |
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, `Test_Master_Real,
|
| 630 |
|
|
test_observe_3_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
| 631 |
|
|
|
| 632 |
|
|
Watch_For_Deassert_Before_Tristate(`Test_Master_Real, prev_real_oe_sigs, test_observe_r_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
| 633 |
|
|
Watch_For_Deassert_Before_Tristate(3'h0, prev_test_0_oe_sigs, test_observe_0_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
| 634 |
|
|
Watch_For_Deassert_Before_Tristate(3'h1, prev_test_1_oe_sigs, test_observe_1_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
| 635 |
|
|
Watch_For_Deassert_Before_Tristate(3'h2, prev_test_2_oe_sigs, test_observe_2_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
| 636 |
|
|
Watch_For_Deassert_Before_Tristate(3'h3, prev_test_3_oe_sigs, test_observe_3_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
| 637 |
|
|
|
| 638 |
|
|
end
|
| 639 |
|
|
`NO_ELSE;
|
| 640 |
|
|
end
|
| 641 |
|
|
|
| 642 |
106 |
mihad |
wire [4:0] grant_now = {pci_ext_gnt_l[3:0], pci_real_gnt_l} ;
|
| 643 |
|
|
|
| 644 |
15 |
mihad |
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
| 645 |
|
|
begin
|
| 646 |
|
|
if (pci_ext_reset_l == 1'b0)
|
| 647 |
|
|
begin
|
| 648 |
|
|
grant_prev <= 5'h00;
|
| 649 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_X;
|
| 650 |
|
|
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_X;
|
| 651 |
|
|
frame_prev <= 1'b0;
|
| 652 |
|
|
irdy_prev <= 1'b0;
|
| 653 |
|
|
devsel_prev <= 1'b0;
|
| 654 |
|
|
trdy_prev <= 1'b0;
|
| 655 |
|
|
stop_prev <= 1'b0;
|
| 656 |
|
|
address_phase_prev <= 1'b0;
|
| 657 |
|
|
read_operation_prev <= 1'b0;
|
| 658 |
|
|
end
|
| 659 |
|
|
else
|
| 660 |
|
|
begin
|
| 661 |
106 |
mihad |
grant_prev <= grant_now ;
|
| 662 |
15 |
mihad |
ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
|
| 663 |
|
|
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
|
| 664 |
|
|
frame_prev <= frame_now;
|
| 665 |
|
|
irdy_prev <= irdy_now;
|
| 666 |
|
|
devsel_prev <= devsel_now;
|
| 667 |
|
|
trdy_prev <= trdy_now;
|
| 668 |
|
|
stop_prev <= stop_now;
|
| 669 |
|
|
perr_prev <= perr_now ;
|
| 670 |
|
|
|
| 671 |
45 |
mihad |
if (frame_now & ~frame_prev)
|
| 672 |
15 |
mihad |
begin
|
| 673 |
|
|
address_phase_prev <= 1'b1;
|
| 674 |
|
|
read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
|
| 675 |
|
|
end
|
| 676 |
45 |
mihad |
else if(address_phase_prev && (cbe_l_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_DUAL_ADDRESS_CYCLE))
|
| 677 |
|
|
begin
|
| 678 |
|
|
address_phase_prev <= 1'b1;
|
| 679 |
|
|
read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
|
| 680 |
|
|
end
|
| 681 |
15 |
mihad |
else
|
| 682 |
|
|
begin
|
| 683 |
|
|
address_phase_prev <= 1'b0;
|
| 684 |
|
|
read_operation_prev <= read_operation_prev;
|
| 685 |
|
|
end
|
| 686 |
|
|
end
|
| 687 |
|
|
end
|
| 688 |
|
|
|
| 689 |
|
|
// Track the behavior of the PCI Arbiter. Rules:
|
| 690 |
|
|
// 1) No grant during reset
|
| 691 |
|
|
// 2) At most 1 grant at any time
|
| 692 |
|
|
// 3) One non-grant cycle on any grant transition when the bus is idle
|
| 693 |
|
|
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
|
| 694 |
|
|
always @(posedge pci_ext_clk)
|
| 695 |
|
|
begin
|
| 696 |
|
|
if ($time > 0)
|
| 697 |
|
|
begin
|
| 698 |
|
|
if ((^{pci_ext_gnt_l[3:0], pci_real_gnt_l}) === 1'bX)
|
| 699 |
|
|
begin
|
| 700 |
|
|
$display ("*** monitor - PCI GNT_L unknown 'h%x, at %t",
|
| 701 |
|
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 702 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI GNT_L unknown 'h%x, at %t",
|
| 703 |
|
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 704 |
|
|
error_detected <= ~error_detected;
|
| 705 |
|
|
end
|
| 706 |
|
|
`NO_ELSE;
|
| 707 |
|
|
if ((pci_ext_reset_l == 1'b0)
|
| 708 |
|
|
&& ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F))
|
| 709 |
|
|
begin
|
| 710 |
|
|
$display ("*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
|
| 711 |
|
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 712 |
|
|
$fdisplay (log_file_desc, "*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
|
| 713 |
|
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 714 |
|
|
error_detected <= ~error_detected;
|
| 715 |
|
|
end
|
| 716 |
|
|
`NO_ELSE;
|
| 717 |
|
|
if ( (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[2])
|
| 718 |
|
|
|| (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[1])
|
| 719 |
|
|
|| (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[0])
|
| 720 |
|
|
|| (~pci_ext_gnt_l[3] & ~pci_real_gnt_l)
|
| 721 |
|
|
|| (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[1])
|
| 722 |
|
|
|| (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[0])
|
| 723 |
|
|
|| (~pci_ext_gnt_l[2] & ~pci_real_gnt_l)
|
| 724 |
|
|
|| (~pci_ext_gnt_l[1] & ~pci_ext_gnt_l[0])
|
| 725 |
|
|
|| (~pci_ext_gnt_l[1] & ~pci_real_gnt_l)
|
| 726 |
|
|
|| (~pci_ext_gnt_l[0] & ~pci_real_gnt_l) )
|
| 727 |
|
|
begin
|
| 728 |
|
|
$display ("*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
|
| 729 |
|
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 730 |
|
|
$fdisplay (log_file_desc, "*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
|
| 731 |
|
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 732 |
|
|
error_detected <= ~error_detected;
|
| 733 |
|
|
end
|
| 734 |
|
|
`NO_ELSE;
|
| 735 |
|
|
if ( (pci_ext_reset_l == 1'b1)
|
| 736 |
|
|
&& (~frame_prev & ~irdy_prev) // bus idle
|
| 737 |
|
|
&& (grant_prev != 5'h1F) && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F)
|
| 738 |
|
|
&& ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != grant_prev))
|
| 739 |
|
|
begin
|
| 740 |
|
|
$display ("*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
|
| 741 |
|
|
grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 742 |
|
|
$fdisplay (log_file_desc, "*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
|
| 743 |
|
|
grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
| 744 |
|
|
error_detected <= ~error_detected;
|
| 745 |
|
|
end
|
| 746 |
|
|
`NO_ELSE;
|
| 747 |
|
|
end
|
| 748 |
|
|
`NO_ELSE;
|
| 749 |
|
|
end
|
| 750 |
|
|
|
| 751 |
|
|
// Classify bus activity and notice slow or dead devices.
|
| 752 |
|
|
// See the PCI Local Bus Spec Revision 2.2 section 3.5
|
| 753 |
|
|
reg master_activity_seen, target_activity_seen, target_subsequently_seen;
|
| 754 |
|
|
reg [2:0] master_initial_latency_counter;
|
| 755 |
|
|
reg [3:0] target_initial_latency_counter;
|
| 756 |
|
|
reg [2:0] target_subsequent_latency_counter;
|
| 757 |
|
|
reg [3:0] master_abort_timer;
|
| 758 |
|
|
reg master_abort;
|
| 759 |
|
|
|
| 760 |
|
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
| 761 |
|
|
begin
|
| 762 |
|
|
if (pci_ext_reset_l == 1'b0)
|
| 763 |
|
|
begin
|
| 764 |
|
|
master_activity_seen <= 1'b0;
|
| 765 |
|
|
master_initial_latency_counter <= 3'h0;
|
| 766 |
|
|
target_activity_seen <= 1'b0;
|
| 767 |
|
|
target_initial_latency_counter <= 4'h0;
|
| 768 |
|
|
target_subsequently_seen <= 1'b0;
|
| 769 |
|
|
target_subsequent_latency_counter <= 3'h0;
|
| 770 |
|
|
master_abort_timer <= 4'h0;
|
| 771 |
|
|
master_abort <= 1'b0;
|
| 772 |
|
|
end
|
| 773 |
|
|
else
|
| 774 |
|
|
begin
|
| 775 |
|
|
if ((address_phase_prev) | (~frame_prev & ~irdy_prev)) // address or idle
|
| 776 |
|
|
begin
|
| 777 |
|
|
master_abort_timer <= 4'h0;
|
| 778 |
|
|
master_abort <= 1'b0;
|
| 779 |
|
|
master_activity_seen <= 1'b0;
|
| 780 |
|
|
master_initial_latency_counter <= 3'h0;
|
| 781 |
|
|
target_activity_seen <= 1'b0;
|
| 782 |
|
|
target_initial_latency_counter <= 4'h0;
|
| 783 |
|
|
target_subsequently_seen <= 1'b0;
|
| 784 |
|
|
target_subsequent_latency_counter <= 3'h0;
|
| 785 |
|
|
end
|
| 786 |
|
|
else
|
| 787 |
|
|
begin
|
| 788 |
|
|
// NOTE WORKING not debugged yet.
|
| 789 |
|
|
master_initial_latency_counter <= master_initial_latency_counter + 3'h1;
|
| 790 |
|
|
master_activity_seen <= master_activity_seen | irdy_now;
|
| 791 |
|
|
if ((master_initial_latency_counter == 3'h7) & ~master_activity_seen)
|
| 792 |
|
|
begin
|
| 793 |
|
|
$display ("*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
|
| 794 |
|
|
$time);
|
| 795 |
|
|
$fdisplay (log_file_desc, "*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
|
| 796 |
|
|
$time);
|
| 797 |
|
|
error_detected <= ~error_detected;
|
| 798 |
|
|
master_activity_seen <= 1'b1;
|
| 799 |
|
|
end
|
| 800 |
|
|
`NO_ELSE;
|
| 801 |
|
|
|
| 802 |
|
|
target_initial_latency_counter <= target_initial_latency_counter
|
| 803 |
|
|
+ (devsel_now ? 4'h1 : 4'h0);
|
| 804 |
|
|
target_activity_seen <= target_activity_seen | trdy_now;
|
| 805 |
|
|
if ((target_initial_latency_counter == 4'hF) & ~target_activity_seen)
|
| 806 |
|
|
begin
|
| 807 |
|
|
$display ("*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
|
| 808 |
|
|
$time);
|
| 809 |
|
|
$fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
|
| 810 |
|
|
$time);
|
| 811 |
|
|
error_detected <= ~error_detected;
|
| 812 |
|
|
target_activity_seen <= 1'b1;
|
| 813 |
|
|
end
|
| 814 |
|
|
`NO_ELSE;
|
| 815 |
|
|
|
| 816 |
|
|
// NOTE This only detects Target misbehavior on the FIRST subsequent transfer!!!
|
| 817 |
|
|
target_subsequent_latency_counter <= target_subsequent_latency_counter
|
| 818 |
|
|
+ (target_activity_seen ? 3'h1 : 3'h0);
|
| 819 |
|
|
target_subsequently_seen <= target_subsequently_seen
|
| 820 |
|
|
| (target_activity_seen & trdy_now);
|
| 821 |
|
|
if ((target_subsequent_latency_counter == 3'h7) & ~target_subsequently_seen)
|
| 822 |
|
|
begin
|
| 823 |
|
|
$display ("*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
|
| 824 |
|
|
$time);
|
| 825 |
|
|
$fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
|
| 826 |
|
|
$time);
|
| 827 |
|
|
error_detected <= ~error_detected;
|
| 828 |
|
|
target_subsequently_seen <= 1'b1;
|
| 829 |
|
|
end
|
| 830 |
|
|
`NO_ELSE;
|
| 831 |
|
|
|
| 832 |
|
|
master_abort_timer <= master_abort_timer + 4'h1;
|
| 833 |
|
|
master_abort <= (master_abort_timer >= 4'h2) ? 1'b1 : master_abort;
|
| 834 |
|
|
end
|
| 835 |
|
|
end
|
| 836 |
|
|
end
|
| 837 |
|
|
|
| 838 |
|
|
// Track the parity bit status on the bus. The rules are:
|
| 839 |
|
|
// 1) parity has to be correct whenever FRAME is asserted to be a valid address
|
| 840 |
|
|
// 2) parity has to be correct whenever IRDY is asserted on writes
|
| 841 |
|
|
// 3) parity has to be correct whenever TRDY is asserted on reads
|
| 842 |
|
|
// parity covers the ad bus, and the cbe wires. The PCI bus is even parity.
|
| 843 |
|
|
// The number of bits set to 1 in AD plus CBE plus PAR is an EVEN number.
|
| 844 |
|
|
// This code will notice an error, but will only complain if the PERR and SERR
|
| 845 |
|
|
// bits don't match,
|
| 846 |
|
|
reg prev_calculated_ad_cbe_parity;
|
| 847 |
|
|
reg prev_prev_calculated_ad_cbe_parity, read_operation_prev_prev;
|
| 848 |
|
|
reg prev_prev_devsel, prev_prev_trdy, prev_prev_irdy, prev_pci_ext_par;
|
| 849 |
|
|
reg ad_prev_address_phase;
|
| 850 |
|
|
reg [PCI_BUS_DATA_RANGE:0] ad_prev_prev;
|
| 851 |
|
|
reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev_prev;
|
| 852 |
|
|
always @(posedge pci_ext_clk)
|
| 853 |
|
|
begin
|
| 854 |
|
|
// calculate 1 if an odd number of bits is set, 0 if an even number is set
|
| 855 |
|
|
prev_calculated_ad_cbe_parity <= (^pci_ext_ad[PCI_BUS_DATA_RANGE:0])
|
| 856 |
|
|
^ (^pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0]);
|
| 857 |
|
|
prev_prev_calculated_ad_cbe_parity <= prev_calculated_ad_cbe_parity;
|
| 858 |
|
|
read_operation_prev_prev <= read_operation_prev;
|
| 859 |
|
|
ad_prev_address_phase <= address_phase_prev;
|
| 860 |
|
|
prev_prev_devsel <= devsel_prev;
|
| 861 |
|
|
prev_prev_trdy <= trdy_prev;
|
| 862 |
|
|
prev_prev_irdy <= irdy_prev;
|
| 863 |
|
|
prev_pci_ext_par <= pci_ext_par;
|
| 864 |
|
|
ad_prev_prev[PCI_BUS_DATA_RANGE:0] <= ad_prev[PCI_BUS_DATA_RANGE:0];
|
| 865 |
|
|
cbe_l_prev_prev[PCI_BUS_CBE_RANGE:0] <= cbe_l_prev[PCI_BUS_CBE_RANGE:0];
|
| 866 |
|
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
| 867 |
|
|
begin
|
| 868 |
|
|
if (ad_prev_address_phase)
|
| 869 |
|
|
begin
|
| 870 |
|
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| 871 |
|
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| 872 |
|
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_serr_l))
|
| 873 |
|
|
begin
|
| 874 |
|
|
$display ("*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 875 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 876 |
|
|
$fdisplay (log_file_desc, "*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 877 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 878 |
|
|
error_detected <= ~error_detected;
|
| 879 |
|
|
end
|
| 880 |
|
|
`NO_ELSE;
|
| 881 |
|
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| 882 |
|
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| 883 |
|
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_serr_l))
|
| 884 |
|
|
begin
|
| 885 |
|
|
$display ("*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 886 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 887 |
|
|
$fdisplay (log_file_desc, "*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 888 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 889 |
|
|
error_detected <= ~error_detected;
|
| 890 |
|
|
end
|
| 891 |
|
|
`NO_ELSE;
|
| 892 |
|
|
end
|
| 893 |
|
|
`NO_ELSE;
|
| 894 |
|
|
if (read_operation_prev_prev & prev_prev_trdy)
|
| 895 |
|
|
begin
|
| 896 |
|
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| 897 |
|
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| 898 |
|
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
|
| 899 |
|
|
begin
|
| 900 |
|
|
$display ("*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 901 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 902 |
|
|
$fdisplay (log_file_desc, "*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 903 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 904 |
|
|
error_detected <= ~error_detected;
|
| 905 |
|
|
end
|
| 906 |
|
|
`NO_ELSE;
|
| 907 |
|
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| 908 |
|
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| 909 |
|
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
|
| 910 |
|
|
begin
|
| 911 |
|
|
$display ("*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 912 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 913 |
|
|
$fdisplay (log_file_desc, "*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 914 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 915 |
|
|
error_detected <= ~error_detected;
|
| 916 |
|
|
end
|
| 917 |
|
|
`NO_ELSE;
|
| 918 |
|
|
end
|
| 919 |
|
|
`NO_ELSE;
|
| 920 |
|
|
if (~read_operation_prev_prev & prev_prev_irdy & prev_prev_devsel)
|
| 921 |
|
|
begin
|
| 922 |
|
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| 923 |
|
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| 924 |
|
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
|
| 925 |
|
|
begin
|
| 926 |
|
|
$display ("*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 927 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 928 |
|
|
$fdisplay (log_file_desc, "*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 929 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 930 |
|
|
error_detected <= ~error_detected;
|
| 931 |
|
|
end
|
| 932 |
|
|
`NO_ELSE;
|
| 933 |
|
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| 934 |
|
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| 935 |
|
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
|
| 936 |
|
|
begin
|
| 937 |
|
|
$display ("*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 938 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 939 |
|
|
$fdisplay (log_file_desc, "*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
| 940 |
|
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
| 941 |
|
|
error_detected <= ~error_detected;
|
| 942 |
|
|
end
|
| 943 |
|
|
`NO_ELSE;
|
| 944 |
|
|
end
|
| 945 |
|
|
`NO_ELSE;
|
| 946 |
|
|
end
|
| 947 |
|
|
end
|
| 948 |
|
|
|
| 949 |
|
|
// Verify some of the state transitions observed on the bus.
|
| 950 |
|
|
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
|
| 951 |
|
|
// In general, transition tests should look at one present signal, and
|
| 952 |
|
|
// a bunch of previous signals.
|
| 953 |
|
|
// In general, simultaneous transition tests should look at two present
|
| 954 |
|
|
// signals, and a bunch of previous signals.
|
| 955 |
|
|
always @(posedge pci_ext_clk)
|
| 956 |
|
|
begin
|
| 957 |
|
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
| 958 |
|
|
begin
|
| 959 |
|
|
if (irdy_prev & ~read_operation_prev & ~(trdy_prev | stop_prev) & (pci_ext_ad != ad_prev))
|
| 960 |
|
|
begin // Appendix C line 2C
|
| 961 |
|
|
$display ("*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
|
| 962 |
|
|
$time);
|
| 963 |
|
|
$fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
|
| 964 |
|
|
$time);
|
| 965 |
|
|
error_detected <= ~error_detected;
|
| 966 |
|
|
end
|
| 967 |
|
|
`NO_ELSE;
|
| 968 |
|
|
if (trdy_prev & read_operation_prev & ~irdy_prev & (pci_ext_ad != ad_prev))
|
| 969 |
|
|
begin // Appendix C line 2C
|
| 970 |
|
|
$display ("*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
|
| 971 |
|
|
$time);
|
| 972 |
|
|
$fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
|
| 973 |
|
|
$time);
|
| 974 |
|
|
error_detected <= ~error_detected;
|
| 975 |
|
|
end
|
| 976 |
|
|
`NO_ELSE;
|
| 977 |
|
|
if (frame_prev & (frame_now | irdy_now) & ~address_phase_prev & ~trdy_now
|
| 978 |
|
|
& (pci_ext_cbe_l != cbe_l_prev))
|
| 979 |
|
|
begin // Appendix C line 3B
|
| 980 |
|
|
$display ("*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
|
| 981 |
|
|
$time);
|
| 982 |
|
|
$fdisplay (log_file_desc, "*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
|
| 983 |
|
|
$time);
|
| 984 |
|
|
error_detected <= ~error_detected;
|
| 985 |
|
|
end
|
| 986 |
|
|
`NO_ELSE;
|
| 987 |
|
|
if (~frame_prev & frame_now & irdy_now)
|
| 988 |
|
|
begin // Section 3.3.3.1 rule 2, Appendix C line 7B
|
| 989 |
|
|
$display ("*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
|
| 990 |
|
|
$time);
|
| 991 |
|
|
$fdisplay (log_file_desc, "*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
|
| 992 |
|
|
$time);
|
| 993 |
|
|
error_detected <= ~error_detected;
|
| 994 |
|
|
end
|
| 995 |
|
|
`NO_ELSE;
|
| 996 |
|
|
if (~irdy_prev & irdy_now & ~frame_prev)
|
| 997 |
|
|
begin // Appendix C line ? not in there!
|
| 998 |
|
|
$display ("*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
|
| 999 |
|
|
$time);
|
| 1000 |
|
|
$fdisplay (log_file_desc, "*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
|
| 1001 |
|
|
$time);
|
| 1002 |
|
|
error_detected <= ~error_detected;
|
| 1003 |
|
|
end
|
| 1004 |
|
|
`NO_ELSE;
|
| 1005 |
|
|
if (frame_prev & ~frame_now & ~irdy_now)
|
| 1006 |
|
|
begin // Section 3.3.3.1 rule 3, Appendix C line 7C
|
| 1007 |
|
|
$display ("*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
|
| 1008 |
|
|
$time);
|
| 1009 |
|
|
$fdisplay (log_file_desc, "*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
|
| 1010 |
|
|
$time);
|
| 1011 |
|
|
error_detected <= ~error_detected;
|
| 1012 |
|
|
end
|
| 1013 |
|
|
`NO_ELSE;
|
| 1014 |
|
|
if (irdy_prev & ~(trdy_prev | stop_prev | master_abort)
|
| 1015 |
|
|
& (frame_now != frame_prev))
|
| 1016 |
|
|
begin // Section 3.3.3.1 rule 4, Appendix C line 7D
|
| 1017 |
|
|
$display ("*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
|
| 1018 |
|
|
$time);
|
| 1019 |
|
|
$fdisplay (log_file_desc, "*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
|
| 1020 |
|
|
$time);
|
| 1021 |
|
|
error_detected <= ~error_detected;
|
| 1022 |
|
|
end
|
| 1023 |
|
|
`NO_ELSE;
|
| 1024 |
|
|
if (irdy_prev & ~(trdy_prev | stop_prev | master_abort) & ~irdy_now)
|
| 1025 |
|
|
begin // Section 3.3.3.1 rule 5, Appendix C line 7E
|
| 1026 |
|
|
$display ("*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
|
| 1027 |
|
|
$time);
|
| 1028 |
|
|
$fdisplay (log_file_desc, "*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
|
| 1029 |
|
|
$time);
|
| 1030 |
|
|
error_detected <= ~error_detected;
|
| 1031 |
|
|
end
|
| 1032 |
|
|
`NO_ELSE;
|
| 1033 |
|
|
// NOTE WORKING section 3.3.3.2.2, Appendix C line 10, REQ must be removed for
|
| 1034 |
|
|
// NOTE WORKING IDLE and one clock on either side of IDLE upon retry or disconnect
|
| 1035 |
|
|
if (stop_prev & frame_prev & frame_now & ~stop_now)
|
| 1036 |
|
|
begin // Section 3.3.3.2.1 rule 3, Appendix C line 12C
|
| 1037 |
|
|
$display ("*** monitor - STOP Deasserted while FRAME Asserted, at %t",
|
| 1038 |
|
|
$time);
|
| 1039 |
|
|
$fdisplay (log_file_desc, "*** monitor - STOP Deasserted while FRAME Asserted, at %t",
|
| 1040 |
|
|
$time);
|
| 1041 |
|
|
error_detected <= ~error_detected;
|
| 1042 |
|
|
end
|
| 1043 |
|
|
`NO_ELSE;
|
| 1044 |
|
|
if (stop_prev & ~frame_prev & frame_now & stop_now)
|
| 1045 |
|
|
begin // Section 3.3.3.2.1 rule 3, Appendix C line 12C, author addition
|
| 1046 |
|
|
$display ("*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
|
| 1047 |
|
|
$time);
|
| 1048 |
|
|
$fdisplay (log_file_desc, "*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
|
| 1049 |
|
|
$time);
|
| 1050 |
|
|
error_detected <= ~error_detected;
|
| 1051 |
|
|
end
|
| 1052 |
|
|
`NO_ELSE;
|
| 1053 |
|
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (devsel_prev != devsel_now))
|
| 1054 |
|
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
| 1055 |
|
|
$display ("*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
| 1056 |
|
|
$time);
|
| 1057 |
|
|
$fdisplay (log_file_desc, "*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
| 1058 |
|
|
$time);
|
| 1059 |
|
|
error_detected <= ~error_detected;
|
| 1060 |
|
|
end
|
| 1061 |
|
|
`NO_ELSE;
|
| 1062 |
|
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (trdy_prev != trdy_now))
|
| 1063 |
|
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
| 1064 |
|
|
$display ("*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
| 1065 |
|
|
$time);
|
| 1066 |
|
|
$fdisplay (log_file_desc, "*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
| 1067 |
|
|
$time);
|
| 1068 |
|
|
error_detected <= ~error_detected;
|
| 1069 |
|
|
end
|
| 1070 |
|
|
`NO_ELSE;
|
| 1071 |
|
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (stop_prev != stop_now))
|
| 1072 |
|
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
| 1073 |
|
|
$display ("*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
| 1074 |
|
|
$time);
|
| 1075 |
|
|
$fdisplay (log_file_desc, "*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
| 1076 |
|
|
$time);
|
| 1077 |
|
|
error_detected <= ~error_detected;
|
| 1078 |
|
|
end
|
| 1079 |
|
|
`NO_ELSE;
|
| 1080 |
|
|
if (~trdy_prev & trdy_now & ~devsel_now)
|
| 1081 |
|
|
begin // Appendix C line 14
|
| 1082 |
|
|
$display ("*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
|
| 1083 |
|
|
$time);
|
| 1084 |
|
|
$fdisplay (log_file_desc, "*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
|
| 1085 |
|
|
$time);
|
| 1086 |
|
|
error_detected <= ~error_detected;
|
| 1087 |
|
|
end
|
| 1088 |
|
|
`NO_ELSE;
|
| 1089 |
|
|
if (~stop_prev & stop_now & ~(devsel_prev | devsel_now))
|
| 1090 |
|
|
begin // Appendix C line 14
|
| 1091 |
|
|
$display ("*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
|
| 1092 |
|
|
$time);
|
| 1093 |
|
|
$fdisplay (log_file_desc, "*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
|
| 1094 |
|
|
$time);
|
| 1095 |
|
|
error_detected <= ~error_detected;
|
| 1096 |
|
|
end
|
| 1097 |
|
|
`NO_ELSE;
|
| 1098 |
|
|
if (~frame_prev & frame_now & (grant_prev == 5'h1F))
|
| 1099 |
|
|
begin // Appendix C line 21
|
| 1100 |
|
|
$display ("*** monitor - FRAME Asserted when no GNT Asserted, at %t",
|
| 1101 |
|
|
$time);
|
| 1102 |
|
|
$fdisplay (log_file_desc, "*** monitor - FRAME Asserted when no GNT Asserted, at %t",
|
| 1103 |
|
|
$time);
|
| 1104 |
|
|
error_detected <= ~error_detected;
|
| 1105 |
|
|
end
|
| 1106 |
|
|
`NO_ELSE;
|
| 1107 |
|
|
if (devsel_prev & ~devsel_now & frame_prev & ~(stop_now & ~trdy_now))
|
| 1108 |
|
|
begin // Appendix C line 30
|
| 1109 |
|
|
$display ("*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
|
| 1110 |
|
|
$time);
|
| 1111 |
|
|
$fdisplay (log_file_desc, "*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
|
| 1112 |
|
|
$time);
|
| 1113 |
|
|
error_detected <= ~error_detected;
|
| 1114 |
|
|
end
|
| 1115 |
|
|
`NO_ELSE;
|
| 1116 |
|
|
end
|
| 1117 |
|
|
`NO_ELSE;
|
| 1118 |
|
|
end
|
| 1119 |
|
|
|
| 1120 |
|
|
// Verify some of the state transitions observed on the bus. See the
|
| 1121 |
|
|
// PCI Local Bus Spec Revision 2.2 section 3.2.1, plus Appendix C.
|
| 1122 |
|
|
`ifdef VERBOSE_MONITOR_DEVICE
|
| 1123 |
|
|
reg prev_pci_ext_reset_l;
|
| 1124 |
|
|
always @(pci_ext_reset_l)
|
| 1125 |
|
|
begin
|
| 1126 |
|
|
prev_pci_ext_reset_l <= pci_ext_reset_l;
|
| 1127 |
|
|
|
| 1128 |
|
|
if (($time > 0) && (pci_ext_reset_l !== prev_pci_ext_reset_l))
|
| 1129 |
|
|
begin
|
| 1130 |
|
|
if (pci_ext_reset_l == 1'b0)
|
| 1131 |
|
|
begin
|
| 1132 |
|
|
$display (" monitor - PCI External RESET_L asserted LOW at %t", $time);
|
| 1133 |
|
|
end
|
| 1134 |
|
|
`NO_ELSE;
|
| 1135 |
|
|
|
| 1136 |
|
|
if (pci_ext_reset_l == 1'b1)
|
| 1137 |
|
|
begin
|
| 1138 |
|
|
$display (" monitor - PCI External RESET_L deasserted HIGH at %t", $time);
|
| 1139 |
|
|
end
|
| 1140 |
|
|
`NO_ELSE;
|
| 1141 |
|
|
end
|
| 1142 |
|
|
end
|
| 1143 |
|
|
|
| 1144 |
|
|
always @(posedge pci_ext_clk)
|
| 1145 |
|
|
begin
|
| 1146 |
|
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
| 1147 |
|
|
begin
|
| 1148 |
|
|
// report a Master Abort, which is not an error
|
| 1149 |
|
|
if ((irdy_prev & ~irdy_now) & (~trdy_prev & ~stop_prev & master_abort))
|
| 1150 |
|
|
begin
|
| 1151 |
|
|
$display (" monitor - IRDY Deasserted due to Master Abort, at %t", $time);
|
| 1152 |
|
|
end
|
| 1153 |
|
|
`NO_ELSE;
|
| 1154 |
|
|
|
| 1155 |
|
|
if (~frame_prev & frame_now & irdy_prev & ~irdy_now)
|
| 1156 |
|
|
begin
|
| 1157 |
|
|
$display (" Fast Back-to-Back reference with no Idle cycle started at %t",
|
| 1158 |
|
|
$time);
|
| 1159 |
|
|
end
|
| 1160 |
|
|
`NO_ELSE;
|
| 1161 |
|
|
end
|
| 1162 |
|
|
`NO_ELSE;
|
| 1163 |
|
|
end
|
| 1164 |
|
|
`endif // VERBOSE_MONITOR_DEVICE
|
| 1165 |
|
|
|
| 1166 |
|
|
`ifdef VERBOSE_MONITOR_DEVICE
|
| 1167 |
|
|
always @(posedge pci_ext_clk)
|
| 1168 |
|
|
begin
|
| 1169 |
|
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0) && address_phase_prev)
|
| 1170 |
|
|
begin
|
| 1171 |
|
|
// command list taken from PCI Local Bus Spec Revision 2.2 section 3.1.1.
|
| 1172 |
|
|
case (cbe_l_prev[PCI_BUS_CBE_RANGE:0])
|
| 1173 |
|
|
PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
|
| 1174 |
|
|
$display (" monitor - Interrupt Acknowledge started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1175 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);,
|
| 1176 |
|
|
PCI_COMMAND_SPECIAL_CYCLE:
|
| 1177 |
|
|
$display (" monitor - Special Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1178 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1179 |
|
|
PCI_COMMAND_IO_READ:
|
| 1180 |
|
|
$display (" monitor - IO Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1181 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1182 |
|
|
PCI_COMMAND_IO_WRITE:
|
| 1183 |
|
|
$display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1184 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1185 |
|
|
PCI_COMMAND_RESERVED_READ_4:
|
| 1186 |
|
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1187 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1188 |
|
|
PCI_COMMAND_RESERVED_WRITE_5:
|
| 1189 |
|
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1190 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1191 |
|
|
PCI_COMMAND_MEMORY_READ:
|
| 1192 |
|
|
$display (" monitor - Memory Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1193 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1194 |
|
|
PCI_COMMAND_MEMORY_WRITE:
|
| 1195 |
|
|
$display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1196 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1197 |
|
|
PCI_COMMAND_RESERVED_READ_8:
|
| 1198 |
|
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1199 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1200 |
|
|
PCI_COMMAND_RESERVED_WRITE_9:
|
| 1201 |
|
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1202 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1203 |
|
|
PCI_COMMAND_CONFIG_READ:
|
| 1204 |
|
|
$display (" monitor - Configuration Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1205 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1206 |
|
|
PCI_COMMAND_CONFIG_WRITE:
|
| 1207 |
|
|
$display (" monitor - Configuration Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1208 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1209 |
|
|
PCI_COMMAND_MEMORY_READ_MULTIPLE:
|
| 1210 |
|
|
$display (" monitor - Memory Read Multiple started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1211 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1212 |
|
|
PCI_COMMAND_DUAL_ADDRESS_CYCLE:
|
| 1213 |
|
|
$display (" monitor - Dual Address Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1214 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1215 |
|
|
PCI_COMMAND_MEMORY_READ_LINE:
|
| 1216 |
|
|
$display (" monitor - Memory Read Line started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1217 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1218 |
|
|
PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
|
| 1219 |
|
|
$display (" monitor - Memory Write and Invalidate started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1220 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1221 |
|
|
default:
|
| 1222 |
|
|
begin
|
| 1223 |
|
|
$display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
|
| 1224 |
|
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
| 1225 |
|
|
error_detected <= ~error_detected;
|
| 1226 |
|
|
end
|
| 1227 |
|
|
endcase
|
| 1228 |
|
|
end
|
| 1229 |
|
|
`NO_ELSE;
|
| 1230 |
|
|
end
|
| 1231 |
|
|
`endif // VERBOSE_MONITOR_DEVICE
|
| 1232 |
|
|
|
| 1233 |
106 |
mihad |
initial get_pci_op.timeout_val = 32'hffff ;
|
| 1234 |
|
|
|
| 1235 |
|
|
reg [4:0] cur_transaction_owner ;
|
| 1236 |
|
|
|
| 1237 |
|
|
initial cur_transaction_owner = 5'h1F ;
|
| 1238 |
|
|
|
| 1239 |
|
|
task get_pci_op ;
|
| 1240 |
|
|
output [31:0] address_o ;
|
| 1241 |
|
|
output [3:0 ] bus_command_o ;
|
| 1242 |
|
|
reg [31:0] timeout_val ;
|
| 1243 |
|
|
reg in_use ;
|
| 1244 |
|
|
begin:main
|
| 1245 |
|
|
if (in_use === 1'b1)
|
| 1246 |
|
|
begin
|
| 1247 |
|
|
$display("%m re-entered!") ;
|
| 1248 |
|
|
$fdisplay(log_file_desc, "%m re-entered!") ;
|
| 1249 |
|
|
error_detected <= ~error_detected;
|
| 1250 |
|
|
disable main ;
|
| 1251 |
|
|
end
|
| 1252 |
|
|
|
| 1253 |
|
|
in_use = 1'b1 ;
|
| 1254 |
|
|
|
| 1255 |
|
|
fork
|
| 1256 |
|
|
begin:get_op_blk
|
| 1257 |
|
|
wait(pci_ext_reset_l === 1'b1) ;
|
| 1258 |
|
|
|
| 1259 |
|
|
@(posedge pci_ext_clk) ;
|
| 1260 |
|
|
|
| 1261 |
|
|
while ((frame_now !== 1'b1) | (frame_prev !== 1'b0) )
|
| 1262 |
|
|
@(posedge pci_ext_clk) ;
|
| 1263 |
|
|
|
| 1264 |
|
|
disable timeout_blk ;
|
| 1265 |
|
|
|
| 1266 |
|
|
address_o = pci_ext_ad ;
|
| 1267 |
|
|
bus_command_o = pci_ext_cbe_l ;
|
| 1268 |
|
|
cur_transaction_owner = grant_now ;
|
| 1269 |
|
|
|
| 1270 |
|
|
end
|
| 1271 |
|
|
begin:timeout_blk
|
| 1272 |
|
|
#(timeout_val) ;
|
| 1273 |
|
|
disable get_op_blk ;
|
| 1274 |
|
|
address_o = 32'hxxxx_xxxx ;
|
| 1275 |
|
|
bus_command_o = 4'hx ;
|
| 1276 |
|
|
end
|
| 1277 |
|
|
join
|
| 1278 |
|
|
|
| 1279 |
|
|
in_use = 1'b0 ;
|
| 1280 |
|
|
|
| 1281 |
|
|
end
|
| 1282 |
|
|
endtask // get_pci_op
|
| 1283 |
|
|
|
| 1284 |
|
|
task get_pci_op_num_of_transfers ;
|
| 1285 |
|
|
output [31:0] num_of_transfers_o ;
|
| 1286 |
|
|
output gnt_deasserted_o ;
|
| 1287 |
|
|
reg [7:0] num_of_cycles_without_transfer ;
|
| 1288 |
|
|
reg in_use ;
|
| 1289 |
|
|
begin:main
|
| 1290 |
|
|
|
| 1291 |
|
|
if (in_use === 1'b1)
|
| 1292 |
|
|
begin
|
| 1293 |
|
|
$display("%m re-entered!") ;
|
| 1294 |
|
|
$fdisplay(log_file_desc, "%m re-entered!") ;
|
| 1295 |
|
|
error_detected <= ~error_detected;
|
| 1296 |
|
|
disable main ;
|
| 1297 |
|
|
end
|
| 1298 |
|
|
|
| 1299 |
|
|
in_use = 1'b1 ;
|
| 1300 |
|
|
|
| 1301 |
|
|
num_of_transfers_o = 0 ;
|
| 1302 |
|
|
num_of_cycles_without_transfer = 0 ;
|
| 1303 |
|
|
|
| 1304 |
|
|
@(posedge pci_ext_clk) ;
|
| 1305 |
|
|
while( (frame_now === 1'b1) & (num_of_cycles_without_transfer < 128) )
|
| 1306 |
|
|
begin
|
| 1307 |
|
|
if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
|
| 1308 |
|
|
begin
|
| 1309 |
|
|
num_of_transfers_o = num_of_transfers_o + 1'b1 ;
|
| 1310 |
|
|
num_of_cycles_without_transfer = 0 ;
|
| 1311 |
|
|
end
|
| 1312 |
|
|
else
|
| 1313 |
|
|
begin
|
| 1314 |
|
|
num_of_cycles_without_transfer = num_of_cycles_without_transfer + 1'b1 ;
|
| 1315 |
|
|
end
|
| 1316 |
|
|
|
| 1317 |
|
|
@(posedge pci_ext_clk) ;
|
| 1318 |
|
|
|
| 1319 |
|
|
end
|
| 1320 |
|
|
|
| 1321 |
|
|
if (num_of_cycles_without_transfer === 128)
|
| 1322 |
|
|
begin
|
| 1323 |
|
|
$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
|
| 1324 |
|
|
$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
|
| 1325 |
|
|
error_detected <= ~error_detected ;
|
| 1326 |
|
|
num_of_transfers_o = 32'hxxxx_xxxx ;
|
| 1327 |
|
|
gnt_deasserted_o = 1'bx ;
|
| 1328 |
|
|
end
|
| 1329 |
|
|
else
|
| 1330 |
|
|
begin
|
| 1331 |
|
|
gnt_deasserted_o = ( cur_transaction_owner != grant_now ) ;
|
| 1332 |
|
|
|
| 1333 |
|
|
while ( (irdy_now === 1'b1) & (trdy_now === 1'b0) & (stop_now === 1'b0) )
|
| 1334 |
|
|
@(posedge pci_ext_clk) ;
|
| 1335 |
|
|
|
| 1336 |
|
|
if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
|
| 1337 |
|
|
num_of_transfers_o = num_of_transfers_o + 1'b1 ;
|
| 1338 |
|
|
end
|
| 1339 |
|
|
|
| 1340 |
|
|
in_use = 1'b0 ;
|
| 1341 |
|
|
end
|
| 1342 |
|
|
endtask // get_pci_op_num_of_transfers
|
| 1343 |
|
|
|
| 1344 |
|
|
task get_pci_op_num_of_cycles ;
|
| 1345 |
|
|
output [31:0] frame_asserted_cycles_o ;
|
| 1346 |
|
|
reg [31:0] num_of_cycles_after_last_data_phase_termination ;
|
| 1347 |
|
|
reg in_use ;
|
| 1348 |
|
|
begin:main
|
| 1349 |
|
|
if (in_use === 1'b1)
|
| 1350 |
|
|
begin
|
| 1351 |
|
|
$display("%m re-entered!") ;
|
| 1352 |
|
|
$fdisplay(log_file_desc, "%m re-entered!") ;
|
| 1353 |
|
|
error_detected <= ~error_detected;
|
| 1354 |
|
|
disable main ;
|
| 1355 |
|
|
end
|
| 1356 |
|
|
|
| 1357 |
|
|
in_use = 1'b1 ;
|
| 1358 |
|
|
|
| 1359 |
|
|
frame_asserted_cycles_o = 1 ;
|
| 1360 |
|
|
num_of_cycles_after_last_data_phase_termination = 1 ;
|
| 1361 |
|
|
|
| 1362 |
|
|
@(posedge pci_ext_clk) ;
|
| 1363 |
|
|
while( (frame_now === 1'b1) & (num_of_cycles_after_last_data_phase_termination < 128) )
|
| 1364 |
|
|
begin
|
| 1365 |
|
|
|
| 1366 |
|
|
if (irdy_prev & trdy_prev & devsel_prev )
|
| 1367 |
|
|
begin
|
| 1368 |
|
|
|
| 1369 |
|
|
frame_asserted_cycles_o = frame_asserted_cycles_o + num_of_cycles_after_last_data_phase_termination ;
|
| 1370 |
|
|
|
| 1371 |
|
|
num_of_cycles_after_last_data_phase_termination = 1 ;
|
| 1372 |
|
|
end
|
| 1373 |
|
|
else
|
| 1374 |
|
|
num_of_cycles_after_last_data_phase_termination = num_of_cycles_after_last_data_phase_termination + 1'b1 ;
|
| 1375 |
|
|
|
| 1376 |
|
|
@(posedge pci_ext_clk) ;
|
| 1377 |
|
|
|
| 1378 |
|
|
end
|
| 1379 |
|
|
|
| 1380 |
|
|
if ( num_of_cycles_after_last_data_phase_termination === 128)
|
| 1381 |
|
|
begin
|
| 1382 |
|
|
$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
|
| 1383 |
|
|
$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
|
| 1384 |
|
|
error_detected <= ~error_detected ;
|
| 1385 |
|
|
frame_asserted_cycles_o = 32'hxxxx_xxxx ;
|
| 1386 |
|
|
end
|
| 1387 |
|
|
|
| 1388 |
|
|
in_use = 1'b0 ;
|
| 1389 |
|
|
end
|
| 1390 |
|
|
endtask // get_pci_op_num_of_cycles
|
| 1391 |
|
|
|
| 1392 |
|
|
task get_pci_master_abort ;
|
| 1393 |
|
|
output [31:0 ] ret_adr_o ;
|
| 1394 |
|
|
output [ 3:0 ] ret_bc_o ;
|
| 1395 |
|
|
output ret_mabort_detected_o ;
|
| 1396 |
|
|
begin:main
|
| 1397 |
|
|
ret_mabort_detected_o = 1'b0 ;
|
| 1398 |
|
|
get_pci_op(ret_adr_o, ret_bc_o) ;
|
| 1399 |
|
|
|
| 1400 |
|
|
if ( (ret_adr_o ^ ret_adr_o) !== 0 )
|
| 1401 |
|
|
disable main ;
|
| 1402 |
|
|
|
| 1403 |
|
|
if ( (ret_bc_o ^ ret_bc_o) !== 0 )
|
| 1404 |
|
|
disable main ;
|
| 1405 |
|
|
|
| 1406 |
|
|
while (frame_now !== 1'b0)
|
| 1407 |
|
|
begin
|
| 1408 |
|
|
if (devsel_now !== 1'b0)
|
| 1409 |
|
|
begin
|
| 1410 |
|
|
// exit immediately on target response detection
|
| 1411 |
|
|
ret_mabort_detected_o = 1'b0 ;
|
| 1412 |
|
|
disable main ;
|
| 1413 |
|
|
end
|
| 1414 |
|
|
|
| 1415 |
|
|
@(posedge pci_ext_clk) ;
|
| 1416 |
|
|
end
|
| 1417 |
|
|
|
| 1418 |
|
|
while(irdy_now !== 1'b0)
|
| 1419 |
|
|
begin
|
| 1420 |
|
|
|
| 1421 |
|
|
if (devsel_now !== 1'b0)
|
| 1422 |
|
|
begin
|
| 1423 |
|
|
// exit immediately on target response detection
|
| 1424 |
|
|
ret_mabort_detected_o = 1'b0 ;
|
| 1425 |
|
|
disable main ;
|
| 1426 |
|
|
end
|
| 1427 |
|
|
|
| 1428 |
|
|
@(posedge pci_ext_clk) ;
|
| 1429 |
|
|
end
|
| 1430 |
|
|
|
| 1431 |
|
|
ret_mabort_detected_o = 1'b1 ;
|
| 1432 |
|
|
end
|
| 1433 |
|
|
endtask // get_pci_master_abort
|
| 1434 |
|
|
endmodule
|
