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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_regression_constants.v"                      ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////      - Tadej Markovic (tadej@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/08/13 11:03:51  mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.2  2002/02/19 16:32:29  mihad
// Modified testbench and fixed some bugs
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
//
 
///////////////////////////////////////////////////////////////////////////////
//// ===================================================================== ////
//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////
////   (script for running regression is prepared for NC-Sim)              ////
////                                                                       ////
////   For description of defines see pci_user_constants.v file !          ////
//// ===================================================================== ////
///////////////////////////////////////////////////////////////////////////////
 
    // Fifo implementation defines:
    // If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
    // 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
    // then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
    // If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
    // If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
    // width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
    // in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
    // If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
    // WB_FIFO_RAM_ADDR_LENGTH.
 
`ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only
    `define WBW_ADDR_LENGTH 3
    `define WBR_ADDR_LENGTH 4
    `define PCIW_ADDR_LENGTH 4
    `define PCIR_ADDR_LENGTH 3
 
    `define FPGA
    `define XILINX
 
    `define WB_RAM_DONT_SHARE
    `define PCI_RAM_DONT_SHARE
 
    `define PCI_FIFO_RAM_ADDR_LENGTH 4      // PCI target unit fifo storage definition
    `define WB_FIFO_RAM_ADDR_LENGTH 4       // WB slave unit fifo storage definition
    `define PCI_XILINX_DIST_RAM
    `define WB_XILINX_DIST_RAM
`endif
 
`ifdef REGR_FIFO_MEDIUM_XILINX
    `define WBW_ADDR_LENGTH 8
    `define WBR_ADDR_LENGTH 8
    `define PCIW_ADDR_LENGTH 8
    `define PCIR_ADDR_LENGTH 8
 
    `define FPGA
    `define XILINX
 
    `define WB_RAM_DONT_SHARE
    `define PCI_RAM_DONT_SHARE
 
    `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
    `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
    `define PCI_XILINX_RAMB4
    `define WB_XILINX_RAMB4
`endif
 
`ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only
    `define WBW_ADDR_LENGTH 7
    `define WBR_ADDR_LENGTH 6
    `define PCIW_ADDR_LENGTH 7
    `define PCIR_ADDR_LENGTH 8
 
    `define PCI_RAM_DONT_SHARE
 
    `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
    `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
    `define WB_ARTISAN_SDP
    `define PCI_ARTISAN_SDP
`endif
 
`ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic)
    `define WBW_ADDR_LENGTH 3
    `define WBR_ADDR_LENGTH 4
    `define PCIW_ADDR_LENGTH 4
    `define PCIR_ADDR_LENGTH 3
 
    `define WB_RAM_DONT_SHARE
 
    `define PCI_FIFO_RAM_ADDR_LENGTH 5      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
    `define WB_FIFO_RAM_ADDR_LENGTH 4       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
 
`endif
 
`ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic)
    `define WBW_ADDR_LENGTH 7
    `define WBR_ADDR_LENGTH 6
    `define PCIW_ADDR_LENGTH 7
    `define PCIR_ADDR_LENGTH 8
 
    `define PCI_RAM_DONT_SHARE
 
    `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
    `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`endif
 
`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
        `define WBW_ADDR_LENGTH 9
        `define WBR_ADDR_LENGTH 9
        `define PCIW_ADDR_LENGTH 9
        `define PCIR_ADDR_LENGTH 9
 
        `define PCI_FIFO_RAM_ADDR_LENGTH 10      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
        `define WB_FIFO_RAM_ADDR_LENGTH 10       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`endif
 
    // number defined here specifies how many MS bits in PCI address are compared with base address, to decode
    // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
    // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
    // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
    // smaller the number here, faster the decoder operation
 
    // initial value for PCI image address masks. Address masks can be defined in enabled state,
    // to allow device independent software to detect size of image and map base addresses to
    // memory space. If initial mask for an image is defined as 0, then device independent software
    // won't detect base address implemented and device dependent software will have to configure
    // address masks as well as base addresses!
 
    // initial value for PCI image maping to MEMORY or IO spaces.  If initial define is set to 0,
    // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
    // Device independent software sets the base addresses acording to MEMORY or IO maping!
 
`ifdef PCI_DECODE_MIN
 
        `define PCI_NUM_OF_DEC_ADDR_LINES 3
 
 
    // don't disable AM0 if GUEST bridge, otherwise there is no other way of accesing configuration space
    `ifdef HOST
        `define PCI_AM0 20'h0000_0
    `else
        `define PCI_AM0 20'hE000_0
    `endif
 
    `define PCI_AM1 20'hE000_0
    `define PCI_AM2 20'h0000_0
    `define PCI_AM3 20'hE000_0
    `define PCI_AM4 20'h0000_0
    `define PCI_AM5 20'hE000_0
 
    `define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
    `define PCI_BA1_MEM_IO 1'b0
    `define PCI_BA2_MEM_IO 1'b1
    `define PCI_BA3_MEM_IO 1'b0
    `define PCI_BA4_MEM_IO 1'b1
    `define PCI_BA5_MEM_IO 1'b0
 
`endif
 
`ifdef PCI_DECODE_MED
 
        `define PCI_NUM_OF_DEC_ADDR_LINES 12
 
        `define PCI_AM0 20'hfff0_0
        `define PCI_AM1 20'h0000_0
        `define PCI_AM2 20'hfff0_0
        `define PCI_AM3 20'h0000_0
        `define PCI_AM4 20'hfff0_0
        `define PCI_AM5 20'h0000_0
 
        `define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
        `define PCI_BA1_MEM_IO 1'b0
        `define PCI_BA2_MEM_IO 1'b1
        `define PCI_BA3_MEM_IO 1'b0
        `define PCI_BA4_MEM_IO 1'b1
        `define PCI_BA5_MEM_IO 1'b0
 
`endif
 
`ifdef PCI_DECODE_MAX
 
    `define PCI_NUM_OF_DEC_ADDR_LINES 20
 
    `define PCI_AM0 20'hffff_e
    `define PCI_AM1 20'hffff_c
    `define PCI_AM2 20'hffff_8
    `define PCI_AM3 20'hfffe_0
    `define PCI_AM4 20'hfffc_0
    `define PCI_AM5 20'hfff8_0
 
    `define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
    `define PCI_BA1_MEM_IO 1'b0
    `define PCI_BA2_MEM_IO 1'b1
    `define PCI_BA3_MEM_IO 1'b1
    `define PCI_BA4_MEM_IO 1'b0
    `define PCI_BA5_MEM_IO 1'b0
 
`endif
 
    // number defined here specifies how many MS bits in WB address are compared with base address, to decode
    // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
    // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
    // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
    // smaller the number here, faster the decoder operation
`ifdef WB_DECODE_MIN
        `define WB_NUM_OF_DEC_ADDR_LINES 4
`endif
 
`ifdef WB_DECODE_MED
        `define WB_NUM_OF_DEC_ADDR_LINES 12
`endif
 
`ifdef WB_DECODE_MAX
        `define WB_NUM_OF_DEC_ADDR_LINES 20
`endif
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`ifdef WB_CNF_BASE_ZERO
    `define WB_CONFIGURATION_BASE 20'h0000_0
`else
    `define WB_CONFIGURATION_BASE 20'hB000_0
`endif
 
    /*-----------------------------------------------------------------------------------------------------------
    [000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
        Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
        Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
        together by application.
    -----------------------------------------------------------------------------------------------------------*/
    `define HEADER_VENDOR_ID    16'h2321
    `define HEADER_DEVICE_ID    16'h0001
    `define HEADER_REVISION_ID  8'h01
 
    // MAX Retry counter value for WISHBONE Master state-machine
    //  This value is 8-bit because of 8-bit retry counter !!!
    `define WB_RTY_CNT_MAX          8'hff
 
/////////////////////////////////////////////////////////////////////////////////
//// ======================================================================= ////
//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////
////   (script for running regression is prepared for NC-Sim)                ////
////                                                                         ////
////   For description of defines see pci_testbench_defines.v file !         ////
//// ======================================================================= ////
/////////////////////////////////////////////////////////////////////////////////
 
    // wishbone frequncy in GHz
    `ifdef WB_CLK10
        `define WB_PERIOD 100.0
    `endif
    `ifdef WB_CLK66
        `define WB_PERIOD 15.0
    `endif
    `ifdef WB_CLK220
        `define WB_PERIOD 4.5
    `endif
 
    // values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
    `define TAR0_BASE_ADDR_0    32'h1000_0000
    `define TAR0_BASE_ADDR_1    32'h2000_0000
    `define TAR0_BASE_ADDR_2    32'h4000_0000
    `define TAR0_BASE_ADDR_3    32'h6000_0000
    `define TAR0_BASE_ADDR_4    32'h8000_0000
    `define TAR0_BASE_ADDR_5    32'hA000_0000
 
    `define TAR0_ADDR_MASK_0    32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_ADDR_MASK_1    32'hFFFF_F000
    `define TAR0_ADDR_MASK_2    32'hFFFF_F000
    `define TAR0_ADDR_MASK_3    32'hFFFF_F000
    `define TAR0_ADDR_MASK_4    32'hFFFF_F000
    `define TAR0_ADDR_MASK_5    32'hFFFF_F000
 
    `define TAR0_TRAN_ADDR_0    32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_TRAN_ADDR_1    32'hA000_0000
    `define TAR0_TRAN_ADDR_2    32'h8000_0000
    `define TAR0_TRAN_ADDR_3    32'h6000_0000
    `define TAR0_TRAN_ADDR_4    32'h4000_0000
    `define TAR0_TRAN_ADDR_5    32'h2000_0000
 
    // values of image registers of PCI behavioral target devices !
    `define BEH_TAR1_MEM_START 32'hC000_0000
    `define BEH_TAR1_MEM_END   32'hC000_0FFF
    `define BEH_TAR1_IO_START  32'hD000_0001
    `define BEH_TAR1_IO_END    32'hD000_0FFF
 
    `define BEH_TAR2_MEM_START 32'hE000_0000
    `define BEH_TAR2_MEM_END   32'hE000_0FFF
    `define BEH_TAR2_IO_START  32'hF000_0001
    `define BEH_TAR2_IO_END    32'hF000_0FFF
 
    // IDSEL lines of each individual Target is connected to one address line
    // following defines set the address line IDSEL is connected to
    // TAR0 = DUT - bridge
    // TAR1 = behavioral target 1
    // TAR2 = behavioral target 2
 
    `define TAR0_IDSEL_INDEX    31
    `define TAR1_IDSEL_INDEX    29
    `define TAR2_IDSEL_INDEX    30
 
    // next 3 defines are derived from previous three defines
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
/*=======================================================================================
  Following defines are used in a script file for regression testing !!!
=========================================================================================
 
  REGRESSION
    HOST                        GUEST
    REGR_FIFO_SMALL_XILINX      REGR_FIFO_MEDIUM_ARTISAN        REGR_FIFO_LARGE_GENERIC
    (REGR_FIFO_SMALL_GENERIC)   (REGR_FIFO_MEDIUM_GENERIC)
    ADDR_TRAN_IMPL
    WB_RETRY_MAX
    WB_CNF_BASE_ZERO
    NO_CNF_IMAGE
    PCI_IMAGE0 // `ifdef HOST `ifdef NO_CNF_IMAGE `define PCI_IMAGE0
    PCI_IMAGE2
    PCI_IMAGE3
    PCI_IMAGE4
    PCI_IMAGE5
    WB_IMAGE2
    WB_IMAGE3
    WB_IMAGE4
    WB_IMAGE5
    WB_DECODE_FAST              WB_DECODE_MEDIUM                WB_DECODE_SLOW
    REGISTER_WBM_OUTPUTS
    REGISTER_WBS_OUTPUTS
    PCI_DECODE_MIN              PCI_DECODE_MED                  PCI_DECODE_MAX
    WB_DECODE_MIN               WB_DECODE_MED                   WB_DECODE_MAX
    PCI33                       PCI66
    WB_CLK10                    WB_CLK66                        WB_CLK100
    ACTIVE_LOW_OE               ACTIVE_HIGH_OE
 
-----------------------------------------------------------------------------------------
  Follows combinations of defines used in a script file for regression testing !!!
-----------------------------------------------------------------------------------------
 
  "REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI33+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2"
  "REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI33+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE5"
  "REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_IMAGE5"
  "REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE5+WB_IMAGE4"
  "REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+PCI_IMAGE0+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4"
  "REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL"
  "REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE4"
  "REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"
  "REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE3"
  "REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI33+WB_CLK66+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE3"
  "REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2"
  "REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI33+WB_CLK10+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"
  ""
 
=========================================================================================
*/
 
 
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_regression_constants.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// - Tadej Markovic (tadej@opencores.org) ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42	104	mihad	`// Revision 1.3 2002/08/13 11:03:51 mihad`
43			`// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image`
44			`//`
45	45	mihad	`// Revision 1.2 2002/02/19 16:32:29 mihad`
46			`// Modified testbench and fixed some bugs`
47			`//`
48	26	mihad	`// Revision 1.1 2002/02/01 13:39:43 mihad`
49			`// Initial testbench import. Still under development`
50	15	mihad	`//`
51	26	mihad	`//`
52	15	mihad
53			`///////////////////////////////////////////////////////////////////////////////`
54			`//// ===================================================================== ////`
55			`//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////`
56			`//// (script for running regression is prepared for NC-Sim) ////`
57			`//// ////`
58			`//// For description of defines see pci_user_constants.v file ! ////`
59			`//// ===================================================================== ////`
60			`///////////////////////////////////////////////////////////////////////////////`
61
62			`// Fifo implementation defines:`
63			`// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.`
64			`// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),`
65			`// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used`
66			`// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )`
67			`// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with`
68			`// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port`
69			`// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).`
70			`// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and`
71			`// WB_FIFO_RAM_ADDR_LENGTH.`
72
73	104	mihad	`ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only
74			`define WBW_ADDR_LENGTH 3
75			`define WBR_ADDR_LENGTH 4
76			`define PCIW_ADDR_LENGTH 4
77			`define PCIR_ADDR_LENGTH 3
78
79			`define FPGA
80			`define XILINX
81
82			`define WB_RAM_DONT_SHARE
83			`define PCI_RAM_DONT_SHARE
84	15	mihad
85	104	mihad	`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
86			`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition
87			`define PCI_XILINX_DIST_RAM
88			`define WB_XILINX_DIST_RAM
89			`endif
90
91			`ifdef REGR_FIFO_MEDIUM_XILINX
92			`define WBW_ADDR_LENGTH 8
93			`define WBR_ADDR_LENGTH 8
94			`define PCIW_ADDR_LENGTH 8
95			`define PCIR_ADDR_LENGTH 8
96
97			`define FPGA
98			`define XILINX
99
100			`define WB_RAM_DONT_SHARE
101			`define PCI_RAM_DONT_SHARE
102	15	mihad
103	104	mihad	`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
104			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
105			`define PCI_XILINX_RAMB4
106			`define WB_XILINX_RAMB4
107			`endif
108	15	mihad
109	104	mihad	`ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only
110			`define WBW_ADDR_LENGTH 7
111			`define WBR_ADDR_LENGTH 6
112			`define PCIW_ADDR_LENGTH 7
113			`define PCIR_ADDR_LENGTH 8
114
115			`define PCI_RAM_DONT_SHARE
116
117			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
118			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
119			`define WB_ARTISAN_SDP
120			`define PCI_ARTISAN_SDP
121			`endif
122
123			`ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic)
124			`define WBW_ADDR_LENGTH 3
125			`define WBR_ADDR_LENGTH 4
126			`define PCIW_ADDR_LENGTH 4
127			`define PCIR_ADDR_LENGTH 3
128
129			`define WB_RAM_DONT_SHARE
130	15	mihad
131	104	mihad	`define PCI_FIFO_RAM_ADDR_LENGTH 5 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
132			`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
133
134			`endif
135
136			`ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic)
137			`define WBW_ADDR_LENGTH 7
138			`define WBR_ADDR_LENGTH 6
139			`define PCIW_ADDR_LENGTH 7
140			`define PCIR_ADDR_LENGTH 8
141
142			`define PCI_RAM_DONT_SHARE
143
144			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
145			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
146			`endif
147
148			`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
149	26	mihad	`define WBW_ADDR_LENGTH 9
150			`define WBR_ADDR_LENGTH 9
151			`define PCIW_ADDR_LENGTH 9
152			`define PCIR_ADDR_LENGTH 9
153	15	mihad
154	104	mihad	`define PCI_FIFO_RAM_ADDR_LENGTH 10 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
155			`define WB_FIFO_RAM_ADDR_LENGTH 10 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
156			`endif
157	15	mihad
158			`// number defined here specifies how many MS bits in PCI address are compared with base address, to decode`
159			`// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number`
160			`// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,`
161			`// you have to define a number of minimum sized image and enlarge others by specifying different address mask.`
162			`// smaller the number here, faster the decoder operation`
163	45	mihad
164			`// initial value for PCI image address masks. Address masks can be defined in enabled state,`
165			`// to allow device independent software to detect size of image and map base addresses to`
166			`// memory space. If initial mask for an image is defined as 0, then device independent software`
167			`// won't detect base address implemented and device dependent software will have to configure`
168			`// address masks as well as base addresses!`
169
170			`// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,`
171			`// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D`
172			`// Device independent software sets the base addresses acording to MEMORY or IO maping!`
173
174	104	mihad	`ifdef PCI_DECODE_MIN
175	45	mihad
176	104	mihad	`define PCI_NUM_OF_DEC_ADDR_LINES 3
177	45	mihad
178
179	104	mihad	`// don't disable AM0 if GUEST bridge, otherwise there is no other way of accesing configuration space`
180			`ifdef HOST
181			`define PCI_AM0 20'h0000_0
182			`else
183			`define PCI_AM0 20'hE000_0
184			`endif
185	45	mihad
186	104	mihad	`define PCI_AM1 20'hE000_0
187			`define PCI_AM2 20'h0000_0
188			`define PCI_AM3 20'hE000_0
189			`define PCI_AM4 20'h0000_0
190			`define PCI_AM5 20'hE000_0
191	45	mihad
192	104	mihad	`define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
193			`define PCI_BA1_MEM_IO 1'b0
194			`define PCI_BA2_MEM_IO 1'b1
195			`define PCI_BA3_MEM_IO 1'b0
196			`define PCI_BA4_MEM_IO 1'b1
197			`define PCI_BA5_MEM_IO 1'b0
198	45	mihad
199	104	mihad	`endif
200	45	mihad
201	104	mihad	`ifdef PCI_DECODE_MED
202	45	mihad
203	104	mihad	`define PCI_NUM_OF_DEC_ADDR_LINES 12
204
205	45	mihad	`define PCI_AM0 20'hfff0_0
206			`define PCI_AM1 20'h0000_0
207			`define PCI_AM2 20'hfff0_0
208			`define PCI_AM3 20'h0000_0
209			`define PCI_AM4 20'hfff0_0
210			`define PCI_AM5 20'h0000_0
211
212			`define PCI_BA0_MEM_IO 1'b1 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
213			`define PCI_BA1_MEM_IO 1'b0
214			`define PCI_BA2_MEM_IO 1'b1
215			`define PCI_BA3_MEM_IO 1'b0
216			`define PCI_BA4_MEM_IO 1'b1
217			`define PCI_BA5_MEM_IO 1'b0
218
219	104	mihad	`endif
220	45	mihad
221	104	mihad	`ifdef PCI_DECODE_MAX
222	45	mihad
223	104	mihad	`define PCI_NUM_OF_DEC_ADDR_LINES 20
224	45	mihad
225	104	mihad	`define PCI_AM0 20'hffff_e
226			`define PCI_AM1 20'hffff_c
227			`define PCI_AM2 20'hffff_8
228			`define PCI_AM3 20'hfffe_0
229			`define PCI_AM4 20'hfffc_0
230			`define PCI_AM5 20'hfff8_0
231	45	mihad
232	104	mihad	`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
233			`define PCI_BA1_MEM_IO 1'b0
234			`define PCI_BA2_MEM_IO 1'b1
235			`define PCI_BA3_MEM_IO 1'b1
236			`define PCI_BA4_MEM_IO 1'b0
237			`define PCI_BA5_MEM_IO 1'b0
238
239			`endif
240	15	mihad
241			`// number defined here specifies how many MS bits in WB address are compared with base address, to decode`
242			`// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number`
243			`// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,`
244			`// you have to define a number of minimum sized image and enlarge others by specifying different address mask.`
245			`// smaller the number here, faster the decoder operation`
246	104	mihad	`ifdef WB_DECODE_MIN
247			`define WB_NUM_OF_DEC_ADDR_LINES 4
248			`endif
249
250			`ifdef WB_DECODE_MED
251			`define WB_NUM_OF_DEC_ADDR_LINES 12
252			`endif
253	15	mihad
254	104	mihad	`ifdef WB_DECODE_MAX
255			`define WB_NUM_OF_DEC_ADDR_LINES 20
256			`endif
257	15	mihad
258	104	mihad	`// Base address for Configuration space access from WB bus. This value cannot be changed during runtime`
259			`ifdef WB_CNF_BASE_ZERO
260			`define WB_CONFIGURATION_BASE 20'h0000_0
261			`else
262			`define WB_CONFIGURATION_BASE 20'hB000_0
263			`endif
264
265	15	mihad	`/*-----------------------------------------------------------------------------------------------------------`
266			`[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !`
267	104	mihad	`Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.`
268			`Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used`
269			`together by application.`
270	15	mihad	`-----------------------------------------------------------------------------------------------------------*/`
271			`define HEADER_VENDOR_ID 16'h2321
272			`define HEADER_DEVICE_ID 16'h0001
273			`define HEADER_REVISION_ID 8'h01
274
275			`// MAX Retry counter value for WISHBONE Master state-machine`
276	104	mihad	`// This value is 8-bit because of 8-bit retry counter !!!`
277			`define WB_RTY_CNT_MAX 8'hff
278	15	mihad
279			`/////////////////////////////////////////////////////////////////////////////////`
280			`//// ======================================================================= ////`
281			`//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////`
282			`//// (script for running regression is prepared for NC-Sim) ////`
283			`//// ////`
284			`//// For description of defines see pci_testbench_defines.v file ! ////`
285			`//// ======================================================================= ////`
286			`/////////////////////////////////////////////////////////////////////////////////`
287
288			`// wishbone frequncy in GHz`
289			`ifdef WB_CLK10
290	104	mihad	`define WB_PERIOD 100.0
291	15	mihad	`endif
292	104	mihad	`ifdef WB_CLK66
293			`define WB_PERIOD 15.0
294			`endif
295			`ifdef WB_CLK220
296			`define WB_PERIOD 4.5
297			`endif
298	15	mihad
299			`// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !`
300	104	mihad	`define TAR0_BASE_ADDR_0 32'h1000_0000
301			`define TAR0_BASE_ADDR_1 32'h2000_0000
302			`define TAR0_BASE_ADDR_2 32'h4000_0000
303			`define TAR0_BASE_ADDR_3 32'h6000_0000
304			`define TAR0_BASE_ADDR_4 32'h8000_0000
305			`define TAR0_BASE_ADDR_5 32'hA000_0000
306	15	mihad
307	104	mihad	`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
308			`define TAR0_ADDR_MASK_1 32'hFFFF_F000
309			`define TAR0_ADDR_MASK_2 32'hFFFF_F000
310			`define TAR0_ADDR_MASK_3 32'hFFFF_F000
311			`define TAR0_ADDR_MASK_4 32'hFFFF_F000
312			`define TAR0_ADDR_MASK_5 32'hFFFF_F000
313	15	mihad
314	104	mihad	`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
315			`define TAR0_TRAN_ADDR_1 32'hA000_0000
316			`define TAR0_TRAN_ADDR_2 32'h8000_0000
317			`define TAR0_TRAN_ADDR_3 32'h6000_0000
318			`define TAR0_TRAN_ADDR_4 32'h4000_0000
319			`define TAR0_TRAN_ADDR_5 32'h2000_0000
320	15	mihad
321			`// values of image registers of PCI behavioral target devices !`
322	26	mihad	`define BEH_TAR1_MEM_START 32'hC000_0000
323			`define BEH_TAR1_MEM_END 32'hC000_0FFF
324			`define BEH_TAR1_IO_START 32'hD000_0001
325			`define BEH_TAR1_IO_END 32'hD000_0FFF
326	15	mihad
327	26	mihad	`define BEH_TAR2_MEM_START 32'hE000_0000
328			`define BEH_TAR2_MEM_END 32'hE000_0FFF
329			`define BEH_TAR2_IO_START 32'hF000_0001
330			`define BEH_TAR2_IO_END 32'hF000_0FFF
331	15	mihad
332	45	mihad	`// IDSEL lines of each individual Target is connected to one address line`
333			`// following defines set the address line IDSEL is connected to`
334			`// TAR0 = DUT - bridge`
335			`// TAR1 = behavioral target 1`
336			`// TAR2 = behavioral target 2`
337
338			`define TAR0_IDSEL_INDEX 31
339			`define TAR1_IDSEL_INDEX 29
340			`define TAR2_IDSEL_INDEX 30
341
342			`// next 3 defines are derived from previous three defines`
343			`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
344			`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
345			`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
346	15	mihad	`/*=======================================================================================`
347			`Following defines are used in a script file for regression testing !!!`
348			`=========================================================================================`
349
350			`REGRESSION`
351	104	mihad	`HOST GUEST`
352			`REGR_FIFO_SMALL_XILINX REGR_FIFO_MEDIUM_ARTISAN REGR_FIFO_LARGE_GENERIC`
353			`(REGR_FIFO_SMALL_GENERIC) (REGR_FIFO_MEDIUM_GENERIC)`
354	15	mihad	`ADDR_TRAN_IMPL`
355			`WB_RETRY_MAX`
356			`WB_CNF_BASE_ZERO`
357			`NO_CNF_IMAGE`
358			PCI_IMAGE0 // `ifdef HOST `ifdef NO_CNF_IMAGE `define PCI_IMAGE0
359			`PCI_IMAGE2`
360			`PCI_IMAGE3`
361			`PCI_IMAGE4`
362			`PCI_IMAGE5`
363			`WB_IMAGE2`
364			`WB_IMAGE3`
365			`WB_IMAGE4`
366			`WB_IMAGE5`
367	104	mihad	`WB_DECODE_FAST WB_DECODE_MEDIUM WB_DECODE_SLOW`
368	15	mihad	`REGISTER_WBM_OUTPUTS`
369			`REGISTER_WBS_OUTPUTS`
370	104	mihad	`PCI_DECODE_MIN PCI_DECODE_MED PCI_DECODE_MAX`
371			`WB_DECODE_MIN WB_DECODE_MED WB_DECODE_MAX`
372			`PCI33 PCI66`
373			`WB_CLK10 WB_CLK66 WB_CLK100`
374			`ACTIVE_LOW_OE ACTIVE_HIGH_OE`
375	15	mihad
376			`-----------------------------------------------------------------------------------------`
377			`Follows combinations of defines used in a script file for regression testing !!!`
378			`-----------------------------------------------------------------------------------------`
379
380			`"REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI33+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2"`
381			`"REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI33+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE5"`
382			`"REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_IMAGE5"`
383			`"REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE5+WB_IMAGE4"`
384			`"REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+PCI_IMAGE0+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4"`
385			`"REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL"`
386			`"REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE4"`
387			`"REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"`
388			`"REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE3"`
389			`"REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI33+WB_CLK66+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE3"`
390			`"REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2"`
391			`"REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI33+WB_CLK10+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"`
392			`""`
393
394			`=========================================================================================`
395			`*/`
396
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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_regression_constants.v] - Blame information for rev 154