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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_regression_constants.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_regression_constants.v"                      ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////      - Tadej Markovic (tadej@opencores.org)                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
///////////////////////////////////////////////////////////////////////////////
//// ===================================================================== ////
//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////
////   (script for running regression is prepared for NC-Sim)              ////
////                                                                       ////
////   For description of defines see pci_user_constants.v file !          ////
//// ===================================================================== ////
///////////////////////////////////////////////////////////////////////////////
 
    // Fifo implementation defines:
    // If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
    // 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
    // then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
    // If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
    // If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
    // width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
    // in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
    // If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
    // WB_FIFO_RAM_ADDR_LENGTH.
 
    `ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only
        `define WBW_ADDR_LENGTH 3
        `define WBR_ADDR_LENGTH 4
        `define PCIW_ADDR_LENGTH 4
        `define PCIR_ADDR_LENGTH 3
 
        `define FPGA
        `define XILINX
 
        `define WB_RAM_DONT_SHARE
        //`define PCI_RAM_DONT_SHARE
 
        `ifdef FPGA
            `ifdef XILINX
                `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
                `define WB_FIFO_RAM_ADDR_LENGTH 4       // WB slave unit fifo storage definition
                `define PCI_XILINX_RAMB4
                //`define WB_XILINX_RAMB4
                //`define PCI_XILINX_DIST_RAM
                `define WB_XILINX_DIST_RAM
            `endif
        `else
            `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
            `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
            `define WB_ARTISAN_SDP
            `define PCI_ARTISAN_SDP
        `endif
    `else
    `ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only
        `define WBW_ADDR_LENGTH 7
        `define WBR_ADDR_LENGTH 6
        `define PCIW_ADDR_LENGTH 7
        `define PCIR_ADDR_LENGTH 8
 
        //`define FPGA
        //`define XILINX
 
        //`define WB_RAM_DONT_SHARE
        `define PCI_RAM_DONT_SHARE
 
        `ifdef FPGA
            `ifdef XILINX
                `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
                `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
                `define PCI_XILINX_RAMB4
                `define WB_XILINX_RAMB4
                //`define PCI_XILINX_DIST_RAM
                //`define WB_XILINX_DIST_RAM
            `endif
        `else
            `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
            `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
            `define WB_ARTISAN_SDP
            `define PCI_ARTISAN_SDP
        `endif
    `else
    `ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic)
        `define WBW_ADDR_LENGTH 3
        `define WBR_ADDR_LENGTH 4
        `define PCIW_ADDR_LENGTH 4
        `define PCIR_ADDR_LENGTH 3
 
        //`define FPGA
        //`define XILINX
 
        `define WB_RAM_DONT_SHARE
        //`define PCI_RAM_DONT_SHARE
 
        `ifdef FPGA
            `ifdef XILINX
                `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
                `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
                `define PCI_XILINX_RAMB4
                `define WB_XILINX_RAMB4
                //`define PCI_XILINX_DIST_RAM
                //`define WB_XILINX_DIST_RAM
            `endif
        `else
            `define PCI_FIFO_RAM_ADDR_LENGTH 5      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
            `define WB_FIFO_RAM_ADDR_LENGTH 4       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
            //`define WB_ARTISAN_SDP
            //`define PCI_ARTISAN_SDP
        `endif
    `else
    `ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic)
        `define WBW_ADDR_LENGTH 7
        `define WBR_ADDR_LENGTH 6
        `define PCIW_ADDR_LENGTH 7
        `define PCIR_ADDR_LENGTH 8
 
        //`define FPGA
        //`define XILINX
 
        //`define WB_RAM_DONT_SHARE
        `define PCI_RAM_DONT_SHARE
 
        `ifdef FPGA
            `ifdef XILINX
                `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
                `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
                `define PCI_XILINX_RAMB4
                `define WB_XILINX_RAMB4
                //`define PCI_XILINX_DIST_RAM
                //`define WB_XILINX_DIST_RAM
            `endif
        `else
            `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
            `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
            //`define WB_ARTISAN_SDP
            //`define PCI_ARTISAN_SDP
        `endif
    `else
    `ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
        `define WBW_ADDR_LENGTH 10
        `define WBR_ADDR_LENGTH 10
        `define PCIW_ADDR_LENGTH 10
        `define PCIR_ADDR_LENGTH 10
 
        //`define FPGA
        //`define XILINX
 
        //`define WB_RAM_DONT_SHARE
        //`define PCI_RAM_DONT_SHARE
 
        `ifdef FPGA
            `ifdef XILINX
                `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
                `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
                `define PCI_XILINX_RAMB4
                `define WB_XILINX_RAMB4
                //`define PCI_XILINX_DIST_RAM
                //`define WB_XILINX_DIST_RAM
            `endif
        `else
            `define PCI_FIFO_RAM_ADDR_LENGTH 11      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
            `define WB_FIFO_RAM_ADDR_LENGTH 11       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
            //`define WB_ARTISAN_SDP
            //`define PCI_ARTISAN_SDP
        `endif
    `else
    `endif
    `endif
    `endif
    `endif
    `endif
 
    // number defined here specifies how many MS bits in PCI address are compared with base address, to decode
    // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
    // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
    // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
    // smaller the number here, faster the decoder operation
    `ifdef PCI_DECODE_MIN
        `define PCI_NUM_OF_DEC_ADDR_LINES 3
    `else
     `ifdef PCI_DECODE_MED
        `define PCI_NUM_OF_DEC_ADDR_LINES 12
     `else
      `ifdef PCI_DECODE_MAX
        `define PCI_NUM_OF_DEC_ADDR_LINES 20
      `endif
     `endif
    `endif
 
    // initial value for PCI image address masks. Address masks can be defined in enabled state,
    // to allow device independent software to detect size of image and map base addresses to
    // memory space. If initial mask for an image is defined as 0, then device independent software
    // won't detect base address implemented and device dependent software will have to configure
    // address masks as well as base addresses!
    `define PCI_AM0 20'hffff_f
    `define PCI_AM1 20'hffff_f
    `define PCI_AM2 20'hffff_f
    `define PCI_AM3 20'hffff_f
    `define PCI_AM4 20'hffff_f
    `define PCI_AM5 20'hffff_f
 
    // initial value for PCI image maping to MEMORY or IO spaces.  If initial define is set to 0,
    // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
    // Device independent software sets the base addresses acording to MEMORY or IO maping!
    `define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
    `define PCI_BA1_MEM_IO 1'b0
    `define PCI_BA2_MEM_IO 1'b0
    `define PCI_BA3_MEM_IO 1'b0
    `define PCI_BA4_MEM_IO 1'b1
    `define PCI_BA5_MEM_IO 1'b1
 
    // number defined here specifies how many MS bits in WB address are compared with base address, to decode
    // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
    // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
    // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
    // smaller the number here, faster the decoder operation
    `ifdef WB_DECODE_MIN
        `define WB_NUM_OF_DEC_ADDR_LINES 3
    `else
     `ifdef WB_DECODE_MED
        `define WB_NUM_OF_DEC_ADDR_LINES 12
     `else
      `ifdef WB_DECODE_MAX
        `define WB_NUM_OF_DEC_ADDR_LINES 20
      `endif
     `endif
    `endif
 
    // Base address for Configuration space access from WB bus. This value cannot be changed during runtime
    `ifdef WB_CNF_BASE_ZERO
        `define WB_CONFIGURATION_BASE 20'h0000_0
    `else
        `define WB_CONFIGURATION_BASE 20'hF000_0
    `endif
 
    /*-----------------------------------------------------------------------------------------------------------
    [000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
        Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
        Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
        together by application.
    -----------------------------------------------------------------------------------------------------------*/
    `define HEADER_VENDOR_ID    16'h2321
    `define HEADER_DEVICE_ID    16'h0001
    `define HEADER_REVISION_ID  8'h01
 
    // MAX Retry counter value for WISHBONE Master state-machine
    //  This value is 8-bit because of 8-bit retry counter !!!
    `ifdef WB_RETRY_MAX
        `define WB_RTY_CNT_MAX                  8'hff
        `else
        `define WB_RTY_CNT_MAX                  8'h1c
    `endif
 
/////////////////////////////////////////////////////////////////////////////////
//// ======================================================================= ////
//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////
////   (script for running regression is prepared for NC-Sim)                ////
////                                                                         ////
////   For description of defines see pci_testbench_defines.v file !         ////
//// ======================================================================= ////
/////////////////////////////////////////////////////////////////////////////////
 
    // wishbone frequncy in GHz
    `ifdef WB_CLK10
        `define WB_FREQ 0.01
    `else
     `ifdef WB_CLK66
        `define WB_FREQ 0.066
     `else
      `ifdef WB_CLK100
        `define WB_FREQ 0.1
      `endif
     `endif
    `endif
 
    // values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
    `define TAR0_BASE_ADDR_0    32'h1000_0000
    `define TAR0_BASE_ADDR_1    32'h2000_0000
    `define TAR0_BASE_ADDR_2    32'h3000_0000
    `define TAR0_BASE_ADDR_3    32'h4000_0000
    `define TAR0_BASE_ADDR_4    32'h5000_0000
    `define TAR0_BASE_ADDR_5    32'h6000_0000
 
    `define TAR0_ADDR_MASK_0    32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_ADDR_MASK_1    32'hFFFF_F000
    `define TAR0_ADDR_MASK_2    32'hFFFF_F000
    `define TAR0_ADDR_MASK_3    32'hFFFF_F000
    `define TAR0_ADDR_MASK_4    32'hFFFF_F000
    `define TAR0_ADDR_MASK_5    32'hFFFF_F000
 
    `define TAR0_TRAN_ADDR_0    32'h5000_0000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_TRAN_ADDR_1    32'h4000_0000
    `define TAR0_TRAN_ADDR_2    32'h3000_0000
    `define TAR0_TRAN_ADDR_3    32'h2000_0000
    `define TAR0_TRAN_ADDR_4    32'h1000_0000
    `define TAR0_TRAN_ADDR_5    32'h0000_0000
 
    // values of image registers of PCI behavioral target devices !
    `define BEH_TAR1_MEM_START 32'h7000_0000
    `define BEH_TAR1_MEM_END   32'h7000_0FFF
    `define BEH_TAR1_IO_START  32'h8000_0001
    `define BEH_TAR1_IO_END    32'h8000_0FFF
 
    `define BEH_TAR2_MEM_START 32'h9000_0000
    `define BEH_TAR2_MEM_END   32'h9000_0FFF
    `define BEH_TAR2_IO_START  32'hA000_0001
    `define BEH_TAR2_IO_END    32'hA000_0FFF
 
/*=======================================================================================
  Following defines are used in a script file for regression testing !!!
=========================================================================================
 
  REGRESSION
    HOST                                                GUEST
    REGR_FIFO_SMALL_XILINX              REGR_FIFO_MEDIUM_ARTISAN                REGR_FIFO_LARGE_GENERIC
    (REGR_FIFO_SMALL_GENERIC)   (REGR_FIFO_MEDIUM_GENERIC)
    ADDR_TRAN_IMPL
    WB_RETRY_MAX
    WB_CNF_BASE_ZERO
    NO_CNF_IMAGE
    PCI_IMAGE0 // `ifdef HOST `ifdef NO_CNF_IMAGE `define PCI_IMAGE0
    PCI_IMAGE2
    PCI_IMAGE3
    PCI_IMAGE4
    PCI_IMAGE5
    WB_IMAGE2
    WB_IMAGE3
    WB_IMAGE4
    WB_IMAGE5
    WB_DECODE_FAST                              WB_DECODE_MEDIUM                                WB_DECODE_SLOW
    REGISTER_WBM_OUTPUTS
    REGISTER_WBS_OUTPUTS
    PCI_DECODE_MIN                              PCI_DECODE_MED                                  PCI_DECODE_MAX
    WB_DECODE_MIN                               WB_DECODE_MED                                   WB_DECODE_MAX
    PCI33                                               PCI66
    WB_CLK10                                    WB_CLK66                                                WB_CLK100
    ACTIVE_LOW_OE                               ACTIVE_HIGH_OE
 
-----------------------------------------------------------------------------------------
  Follows combinations of defines used in a script file for regression testing !!!
-----------------------------------------------------------------------------------------
 
  "REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI33+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2"
  "REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI33+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE5"
  "REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_IMAGE5"
  "REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE5+WB_IMAGE4"
  "REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+PCI_IMAGE0+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4"
  "REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL"
  "REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE4"
  "REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"
  "REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE3"
  "REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI33+WB_CLK66+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE3"
  "REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2"
  "REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI33+WB_CLK10+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"
  ""
 
=========================================================================================
*/
 
 
 
 
 
 
 
 
 
 
 
 
 

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_regression_constants.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_regression_constants.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// - Tadej Markovic (tadej@opencores.org) ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`//`
43
44			`///////////////////////////////////////////////////////////////////////////////`
45			`//// ===================================================================== ////`
46			`//// Following PCI_USER_CONSTANTS are just for regression testing purposes ////`
47			`//// (script for running regression is prepared for NC-Sim) ////`
48			`//// ////`
49			`//// For description of defines see pci_user_constants.v file ! ////`
50			`//// ===================================================================== ////`
51			`///////////////////////////////////////////////////////////////////////////////`
52
53			`// Fifo implementation defines:`
54			`// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.`
55			`// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),`
56			`// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used`
57			`// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )`
58			`// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with`
59			`// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port`
60			`// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).`
61			`// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and`
62			`// WB_FIFO_RAM_ADDR_LENGTH.`
63
64			`ifdef REGR_FIFO_SMALL_XILINX // with Xilinx FPGA parameters only
65			`define WBW_ADDR_LENGTH 3
66			`define WBR_ADDR_LENGTH 4
67			`define PCIW_ADDR_LENGTH 4
68			`define PCIR_ADDR_LENGTH 3
69
70			`define FPGA
71			`define XILINX
72
73			`define WB_RAM_DONT_SHARE
74			//`define PCI_RAM_DONT_SHARE
75
76			`ifdef FPGA
77			`ifdef XILINX
78			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
79			`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition
80			`define PCI_XILINX_RAMB4
81			//`define WB_XILINX_RAMB4
82			//`define PCI_XILINX_DIST_RAM
83			`define WB_XILINX_DIST_RAM
84			`endif
85			`else
86			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
87			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
88			`define WB_ARTISAN_SDP
89			`define PCI_ARTISAN_SDP
90			`endif
91			`else
92			`ifdef REGR_FIFO_MEDIUM_ARTISAN // with Artisan parameter only
93			`define WBW_ADDR_LENGTH 7
94			`define WBR_ADDR_LENGTH 6
95			`define PCIW_ADDR_LENGTH 7
96			`define PCIR_ADDR_LENGTH 8
97
98			//`define FPGA
99			//`define XILINX
100
101			//`define WB_RAM_DONT_SHARE
102			`define PCI_RAM_DONT_SHARE
103
104			`ifdef FPGA
105			`ifdef XILINX
106			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
107			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
108			`define PCI_XILINX_RAMB4
109			`define WB_XILINX_RAMB4
110			//`define PCI_XILINX_DIST_RAM
111			//`define WB_XILINX_DIST_RAM
112			`endif
113			`else
114			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
115			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
116			`define WB_ARTISAN_SDP
117			`define PCI_ARTISAN_SDP
118			`endif
119			`else
120			`ifdef REGR_FIFO_SMALL_GENERIC // without any parameters only (generic)
121			`define WBW_ADDR_LENGTH 3
122			`define WBR_ADDR_LENGTH 4
123			`define PCIW_ADDR_LENGTH 4
124			`define PCIR_ADDR_LENGTH 3
125
126			//`define FPGA
127			//`define XILINX
128
129			`define WB_RAM_DONT_SHARE
130			//`define PCI_RAM_DONT_SHARE
131
132			`ifdef FPGA
133			`ifdef XILINX
134			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
135			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
136			`define PCI_XILINX_RAMB4
137			`define WB_XILINX_RAMB4
138			//`define PCI_XILINX_DIST_RAM
139			//`define WB_XILINX_DIST_RAM
140			`endif
141			`else
142			`define PCI_FIFO_RAM_ADDR_LENGTH 5 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
143			`define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
144			//`define WB_ARTISAN_SDP
145			//`define PCI_ARTISAN_SDP
146			`endif
147			`else
148			`ifdef REGR_FIFO_MEDIUM_GENERIC // without any parameters only (generic)
149			`define WBW_ADDR_LENGTH 7
150			`define WBR_ADDR_LENGTH 6
151			`define PCIW_ADDR_LENGTH 7
152			`define PCIR_ADDR_LENGTH 8
153
154			//`define FPGA
155			//`define XILINX
156
157			//`define WB_RAM_DONT_SHARE
158			`define PCI_RAM_DONT_SHARE
159
160			`ifdef FPGA
161			`ifdef XILINX
162			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
163			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
164			`define PCI_XILINX_RAMB4
165			`define WB_XILINX_RAMB4
166			//`define PCI_XILINX_DIST_RAM
167			//`define WB_XILINX_DIST_RAM
168			`endif
169			`else
170			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
171			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
172			//`define WB_ARTISAN_SDP
173			//`define PCI_ARTISAN_SDP
174			`endif
175			`else
176			`ifdef REGR_FIFO_LARGE_GENERIC // without any parameters only (generic)
177			`define WBW_ADDR_LENGTH 10
178			`define WBR_ADDR_LENGTH 10
179			`define PCIW_ADDR_LENGTH 10
180			`define PCIR_ADDR_LENGTH 10
181
182			//`define FPGA
183			//`define XILINX
184
185			//`define WB_RAM_DONT_SHARE
186			//`define PCI_RAM_DONT_SHARE
187
188			`ifdef FPGA
189			`ifdef XILINX
190			`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
191			`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
192			`define PCI_XILINX_RAMB4
193			`define WB_XILINX_RAMB4
194			//`define PCI_XILINX_DIST_RAM
195			//`define WB_XILINX_DIST_RAM
196			`endif
197			`else
198			`define PCI_FIFO_RAM_ADDR_LENGTH 11 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
199			`define WB_FIFO_RAM_ADDR_LENGTH 11 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
200			//`define WB_ARTISAN_SDP
201			//`define PCI_ARTISAN_SDP
202			`endif
203			`else
204			`endif
205			`endif
206			`endif
207			`endif
208			`endif
209
210			`// number defined here specifies how many MS bits in PCI address are compared with base address, to decode`
211			`// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number`
212			`// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,`
213			`// you have to define a number of minimum sized image and enlarge others by specifying different address mask.`
214			`// smaller the number here, faster the decoder operation`
215			`ifdef PCI_DECODE_MIN
216			`define PCI_NUM_OF_DEC_ADDR_LINES 3
217			`else
218			`ifdef PCI_DECODE_MED
219			`define PCI_NUM_OF_DEC_ADDR_LINES 12
220			`else
221			`ifdef PCI_DECODE_MAX
222			`define PCI_NUM_OF_DEC_ADDR_LINES 20
223			`endif
224			`endif
225			`endif
226
227			`// initial value for PCI image address masks. Address masks can be defined in enabled state,`
228			`// to allow device independent software to detect size of image and map base addresses to`
229			`// memory space. If initial mask for an image is defined as 0, then device independent software`
230			`// won't detect base address implemented and device dependent software will have to configure`
231			`// address masks as well as base addresses!`
232			`define PCI_AM0 20'hffff_f
233			`define PCI_AM1 20'hffff_f
234			`define PCI_AM2 20'hffff_f
235			`define PCI_AM3 20'hffff_f
236			`define PCI_AM4 20'hffff_f
237			`define PCI_AM5 20'hffff_f
238
239			`// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,`
240			`// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D`
241			`// Device independent software sets the base addresses acording to MEMORY or IO maping!`
242			`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
243			`define PCI_BA1_MEM_IO 1'b0
244			`define PCI_BA2_MEM_IO 1'b0
245			`define PCI_BA3_MEM_IO 1'b0
246			`define PCI_BA4_MEM_IO 1'b1
247			`define PCI_BA5_MEM_IO 1'b1
248
249			`// number defined here specifies how many MS bits in WB address are compared with base address, to decode`
250			`// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number`
251			`// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,`
252			`// you have to define a number of minimum sized image and enlarge others by specifying different address mask.`
253			`// smaller the number here, faster the decoder operation`
254			`ifdef WB_DECODE_MIN
255			`define WB_NUM_OF_DEC_ADDR_LINES 3
256			`else
257			`ifdef WB_DECODE_MED
258			`define WB_NUM_OF_DEC_ADDR_LINES 12
259			`else
260			`ifdef WB_DECODE_MAX
261			`define WB_NUM_OF_DEC_ADDR_LINES 20
262			`endif
263			`endif
264			`endif
265
266			`// Base address for Configuration space access from WB bus. This value cannot be changed during runtime`
267			`ifdef WB_CNF_BASE_ZERO
268			`define WB_CONFIGURATION_BASE 20'h0000_0
269			`else
270			`define WB_CONFIGURATION_BASE 20'hF000_0
271			`endif
272
273			`/*-----------------------------------------------------------------------------------------------------------`
274			`[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !`
275			`Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.`
276			`Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used`
277			`together by application.`
278			`-----------------------------------------------------------------------------------------------------------*/`
279			`define HEADER_VENDOR_ID 16'h2321
280			`define HEADER_DEVICE_ID 16'h0001
281			`define HEADER_REVISION_ID 8'h01
282
283			`// MAX Retry counter value for WISHBONE Master state-machine`
284			`// This value is 8-bit because of 8-bit retry counter !!!`
285			`ifdef WB_RETRY_MAX
286			`define WB_RTY_CNT_MAX 8'hff
287			`else
288			`define WB_RTY_CNT_MAX 8'h1c
289			`endif
290
291			`/////////////////////////////////////////////////////////////////////////////////`
292			`//// ======================================================================= ////`
293			`//// Following PCI_TESTBENC_DEFINES are just for regression testing purposes ////`
294			`//// (script for running regression is prepared for NC-Sim) ////`
295			`//// ////`
296			`//// For description of defines see pci_testbench_defines.v file ! ////`
297			`//// ======================================================================= ////`
298			`/////////////////////////////////////////////////////////////////////////////////`
299
300			`// wishbone frequncy in GHz`
301			`ifdef WB_CLK10
302			`define WB_FREQ 0.01
303			`else
304			`ifdef WB_CLK66
305			`define WB_FREQ 0.066
306			`else
307			`ifdef WB_CLK100
308			`define WB_FREQ 0.1
309			`endif
310			`endif
311			`endif
312
313			`// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !`
314			`define TAR0_BASE_ADDR_0 32'h1000_0000
315			`define TAR0_BASE_ADDR_1 32'h2000_0000
316			`define TAR0_BASE_ADDR_2 32'h3000_0000
317			`define TAR0_BASE_ADDR_3 32'h4000_0000
318			`define TAR0_BASE_ADDR_4 32'h5000_0000
319			`define TAR0_BASE_ADDR_5 32'h6000_0000
320
321			`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
322			`define TAR0_ADDR_MASK_1 32'hFFFF_F000
323			`define TAR0_ADDR_MASK_2 32'hFFFF_F000
324			`define TAR0_ADDR_MASK_3 32'hFFFF_F000
325			`define TAR0_ADDR_MASK_4 32'hFFFF_F000
326			`define TAR0_ADDR_MASK_5 32'hFFFF_F000
327
328			`define TAR0_TRAN_ADDR_0 32'h5000_0000 // when BA0 is used to access configuration space, this is NOT important!
329			`define TAR0_TRAN_ADDR_1 32'h4000_0000
330			`define TAR0_TRAN_ADDR_2 32'h3000_0000
331			`define TAR0_TRAN_ADDR_3 32'h2000_0000
332			`define TAR0_TRAN_ADDR_4 32'h1000_0000
333			`define TAR0_TRAN_ADDR_5 32'h0000_0000
334
335			`// values of image registers of PCI behavioral target devices !`
336			`define BEH_TAR1_MEM_START 32'h7000_0000
337			`define BEH_TAR1_MEM_END 32'h7000_0FFF
338			`define BEH_TAR1_IO_START 32'h8000_0001
339			`define BEH_TAR1_IO_END 32'h8000_0FFF
340
341			`define BEH_TAR2_MEM_START 32'h9000_0000
342			`define BEH_TAR2_MEM_END 32'h9000_0FFF
343			`define BEH_TAR2_IO_START 32'hA000_0001
344			`define BEH_TAR2_IO_END 32'hA000_0FFF
345
346			`/*=======================================================================================`
347			`Following defines are used in a script file for regression testing !!!`
348			`=========================================================================================`
349
350			`REGRESSION`
351			`HOST GUEST`
352			`REGR_FIFO_SMALL_XILINX REGR_FIFO_MEDIUM_ARTISAN REGR_FIFO_LARGE_GENERIC`
353			`(REGR_FIFO_SMALL_GENERIC) (REGR_FIFO_MEDIUM_GENERIC)`
354			`ADDR_TRAN_IMPL`
355			`WB_RETRY_MAX`
356			`WB_CNF_BASE_ZERO`
357			`NO_CNF_IMAGE`
358			PCI_IMAGE0 // `ifdef HOST `ifdef NO_CNF_IMAGE `define PCI_IMAGE0
359			`PCI_IMAGE2`
360			`PCI_IMAGE3`
361			`PCI_IMAGE4`
362			`PCI_IMAGE5`
363			`WB_IMAGE2`
364			`WB_IMAGE3`
365			`WB_IMAGE4`
366			`WB_IMAGE5`
367			`WB_DECODE_FAST WB_DECODE_MEDIUM WB_DECODE_SLOW`
368			`REGISTER_WBM_OUTPUTS`
369			`REGISTER_WBS_OUTPUTS`
370			`PCI_DECODE_MIN PCI_DECODE_MED PCI_DECODE_MAX`
371			`WB_DECODE_MIN WB_DECODE_MED WB_DECODE_MAX`
372			`PCI33 PCI66`
373			`WB_CLK10 WB_CLK66 WB_CLK100`
374			`ACTIVE_LOW_OE ACTIVE_HIGH_OE`
375
376			`-----------------------------------------------------------------------------------------`
377			`Follows combinations of defines used in a script file for regression testing !!!`
378			`-----------------------------------------------------------------------------------------`
379
380			`"REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI33+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2"`
381			`"REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI33+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE5"`
382			`"REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_IMAGE5"`
383			`"REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+WB_RETRY_MAX+PCI_IMAGE0+PCI_IMAGE5+WB_IMAGE4"`
384			`"REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL+PCI_IMAGE0+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4"`
385			`"REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_LOW_OE+REGISTER_WBM_OUTPUTS+REGISTER_WBS_OUTPUTS+ADDR_TRAN_IMPL"`
386			`"REGRESSION+HOST+REGR_FIFO_SMALL_XILINX+WB_DECODE_FAST+PCI_DECODE_MAX+WB_DECODE_MIN+PCI66+WB_CLK100+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE4"`
387			`"REGRESSION+HOST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_MEDIUM+PCI_DECODE_MED+WB_DECODE_MED+PCI66+WB_CLK10+ACTIVE_HIGH_OE+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"`
388			`"REGRESSION+HOST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_SLOW+PCI_DECODE_MIN+WB_DECODE_MAX+PCI33+WB_CLK100+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE3"`
389			`"REGRESSION+GUEST+REGR_FIFO_SMALL_XILINX+WB_DECODE_SLOW+PCI_DECODE_MED+WB_DECODE_MIN+PCI33+WB_CLK66+ACTIVE_HIGH_OE+ADDR_TRAN_IMPL+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE3"`
390			`"REGRESSION+GUEST+REGR_FIFO_MEDIUM_ARTISAN+WB_DECODE_FAST+PCI_DECODE_MIN+WB_DECODE_MAX+PCI66+WB_CLK66+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+PCI_IMAGE0+PCI_IMAGE2+PCI_IMAGE3+PCI_IMAGE4+PCI_IMAGE5+WB_IMAGE2"`
391			`"REGRESSION+GUEST+REGR_FIFO_LARGE_GENERIC+WB_DECODE_MEDIUM+PCI_DECODE_MAX+WB_DECODE_MED+PCI33+WB_CLK10+ACTIVE_HIGH_OE+WB_RETRY_MAX+WB_CNF_BASE_ZERO+NO_CNF_IMAGE+WB_IMAGE2+WB_IMAGE3+WB_IMAGE4+WB_IMAGE5"`
392			`""`
393
394			`=========================================================================================`
395			`*/`
396
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